onur
33 lines
912 B
Systemverilog
33 lines
912 B
Systemverilog
`timescale 1ns/1ps
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`default_nettype none
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module tb_ethernet_crc32;
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logic [31:0] crc_in;
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logic [7:0] data_in;
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logic [31:0] crc_out;
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byte vector [0:8];
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integer i;
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ethernet_crc32 dut (.crc_in(crc_in), .data_in(data_in), .crc_out(crc_out));
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initial begin
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vector[0]="1"; vector[1]="2"; vector[2]="3"; vector[3]="4"; vector[4]="5";
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vector[5]="6"; vector[6]="7"; vector[7]="8"; vector[8]="9";
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crc_in = 32'hffffffff;
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data_in = 8'd0;
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#1;
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for (i = 0; i < 9; i = i + 1) begin
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data_in = vector[i];
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#1;
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crc_in = crc_out;
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#1;
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end
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if ((~crc_in) !== 32'hcbf43926)
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$fatal(1, "CRC check vector failed: got %08x expected cbf43926", ~crc_in);
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$display("PASS tb_ethernet_crc32: CRC-32('123456789') = cbf43926");
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$finish;
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end
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endmodule
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`default_nettype wire
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