onur
101 lines
4.2 KiB
Systemverilog
101 lines
4.2 KiB
Systemverilog
`timescale 1ns/1ps
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`default_nettype none
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module tb_ethernet_tx_mac;
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logic clk=0, rst=1;
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logic frame_start=0;
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logic [10:0] payload_length=11'd4;
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logic [7:0] payload_data;
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logic payload_valid, payload_ready;
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logic [7:0] gmii_txd;
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logic gmii_tx_en, gmii_tx_er, busy, frame_done;
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logic [63:0] frames, payload_bytes;
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byte payload [0:3];
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byte captured [0:255];
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byte body [0:59];
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integer payload_pos=0, cap_count=0, i;
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logic [31:0] reference_crc;
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always #4 clk=~clk;
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assign payload_data = payload[payload_pos];
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assign payload_valid = (payload_pos < 4);
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ethernet_tx_mac dut (
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.clk(clk), .rst(rst), .frame_start(frame_start), .payload_length(payload_length),
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.payload_data(payload_data), .payload_valid(payload_valid), .payload_ready(payload_ready),
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.gmii_txd(gmii_txd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er),
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.busy(busy), .frame_done(frame_done), .frames_transmitted(frames),
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.payload_bytes_transmitted(payload_bytes)
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);
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always @(posedge clk) begin
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if (!rst && gmii_tx_en) begin
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captured[cap_count] = gmii_txd;
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cap_count = cap_count + 1;
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if (gmii_tx_er) $fatal(1, "unexpected GMII TX error");
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end
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if (!rst && payload_ready && payload_valid)
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payload_pos <= payload_pos + 1;
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end
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function automatic [31:0] crc_byte(input [31:0] cin, input [7:0] din);
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reg [31:0] c;
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integer b;
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begin
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c=cin;
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for (b=0;b<8;b=b+1)
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c=(c[0]^din[b]) ? ((c>>1)^32'hedb88320) : (c>>1);
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crc_byte=c;
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end
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endfunction
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initial begin
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payload[0]=8'hde; payload[1]=8'had; payload[2]=8'hbe; payload[3]=8'hef;
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repeat(4) @(posedge clk); rst=0;
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@(posedge clk); frame_start=1;
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@(posedge clk); frame_start=0;
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wait(frame_done);
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@(posedge clk);
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if (cap_count != 72) $fatal(1, "frame byte count %0d expected 72", cap_count);
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for (i=0;i<7;i=i+1) if(captured[i]!==8'h55) $fatal(1,"bad preamble byte %0d",i);
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if(captured[7]!==8'hd5) $fatal(1,"bad SFD");
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for (i=0;i<6;i=i+1) body[i]=8'hff;
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body[6]=8'h02; body[7]=8'h27; body[8]=8'h71; body[9]=8'h00; body[10]=8'h00; body[11]=8'h01;
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body[12]=8'h88; body[13]=8'hb5;
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body[14]=8'hde; body[15]=8'had; body[16]=8'hbe; body[17]=8'hef;
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for(i=18;i<60;i=i+1) body[i]=8'h00;
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for(i=0;i<60;i=i+1) if(captured[8+i]!==body[i])
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$fatal(1,"body mismatch byte %0d got %02x expected %02x",i,captured[8+i],body[i]);
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reference_crc=32'hffffffff;
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for(i=0;i<60;i=i+1) reference_crc=crc_byte(reference_crc,body[i]);
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reference_crc=~reference_crc;
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if(captured[68]!==reference_crc[7:0] || captured[69]!==reference_crc[15:8] ||
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captured[70]!==reference_crc[23:16] || captured[71]!==reference_crc[31:24])
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$fatal(1,"FCS mismatch got %02x%02x%02x%02x expected %08x",
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captured[71],captured[70],captured[69],captured[68],reference_crc);
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if(frames!==64'd1 || payload_bytes!==64'd4) $fatal(1,"MAC counters incorrect");
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// Reset while idle, then send another complete frame. No TX_EN fragment
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// may appear during reset or before the new preamble.
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rst=1; payload_pos=0; cap_count=0;
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repeat(3) begin @(posedge clk); if(gmii_tx_en) $fatal(1,"TX_EN asserted during idle reset"); end
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rst=0;
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repeat(2) @(posedge clk);
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frame_start=1; @(posedge clk); frame_start=0;
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wait(frame_done); @(posedge clk);
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if(cap_count!=72) $fatal(1,"post-reset frame malformed: %0d bytes",cap_count);
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for(i=0;i<7;i=i+1) if(captured[i]!==8'h55) $fatal(1,"post-reset preamble byte %0d",i);
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reference_crc=32'hffffffff;
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for(i=0;i<60;i=i+1) reference_crc=crc_byte(reference_crc,body[i]);
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reference_crc=~reference_crc;
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if({captured[71],captured[70],captured[69],captured[68]}!==reference_crc)
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$fatal(1,"post-reset FCS mismatch");
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$display("PASS tb_ethernet_tx_mac: frame/padding/FCS/IFG and reset-between-frames verified");
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$finish;
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end
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initial begin #10000; $fatal(1,"MAC test timeout"); end
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endmodule
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`default_nettype wire
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