Add the missing TPS2121 status pull-up (R108) and correct the power-mux docs

The power mux's status output had no pull-up, which broke the USB current
budget interlock.

TPS2121 ST is an open-drain output; the datasheet lists RST = 6-20 kOhm under
Recommended Operating Conditions, alongside RILM, so it is an external part.
ST is driven low only while IN2 (the J3 external 5 V header) is sourcing OUT,
and is high impedance whenever IN1 (the J7 USB-C input) is sourcing. U10 gate 2
inverts MUX_ST into EXT_SELECTED, and MAIN_EN = USB_3A_OK OR EXT_SELECTED
enables the 15 A core buck. With MUX_ST floating on USB-C power, a drift low
asserts MAIN_EN no matter what the TUSB320 advertised, so the board would try
to bring up the core rail on a 500 mA port. Every other open-drain net here
already has its pull-up (R7/R8, R30, R33/R34, R98/R104/R105/R106); this one was
missed.

R108 (10 k, VCC3V3_AUX -> MUX_ST) is appended at the end of design_data.py
rather than beside the mux: reference designators are assigned in call order,
so inserting it mid-file would renumber every later resistor and invalidate the
routed board. Placed at (53.0, 101.6), 2.4 mm from the U10 gate it holds up,
on a site checked clear of existing copper, and routed with close_remaining.py.

Also corrects POWER_TREE.md, which credited PR1 for giving the external input
priority. PR1 = GND actually *disables* priority mode; CP2 (tied to VCC3V3_AUX)
is what selects IN2. Since CP2 derives from the mux's own output the behaviour
is two-phase - highest-voltage wins at cold start, IN2 unconditionally once the
aux rail is up - so with both inputs connected there can be one seamless
switchover at startup. Documented, with the numbers: both eFuses UV 3.98 V /
OV 5.80 V, ILIM 2.69 A (USB-C) and 4.04 A (header), mux OV 5.69 V / ILIM 4.5 A.
The two inputs are never summed: both eFuses block reverse current and the mux
bonds exactly one input at a time.

board_routed.kicad_sch/.kicad_sym are now gitignored byte copies of the tracked
schematic; kicad-cli needs them beside the board for --schematic-parity, and
deleting them in the previous commit had silently disabled that check.

Verified: ERC 0/0, DRC 0 violations, 0 unconnected, every net one copper group,
schematic parity unchanged at the 402 pre-existing warnings.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d

scripts/design_data.py

@@ -224,13 +224,19 @@ add_ic("U9", "TPS2121", "TPS2121RUXR", "Texas Instruments", "board:Texas_RUX0012
     p(4, "OV2", "MUX_OV2", "input"), p(5, "OV1", "MUX_OV1", "input"), p(6, "PR1", "GND", "input"),
     p(7, "IN1", "USB5_PROT", "power_in"), p(8, "OUT", "SYS5", "power_out"), p(9, "ST", "MUX_ST", "output"),
     p(10, "ILM", "MUX_ILM", "output"), p(11, "SS", "MUX_SS", "output"), p(12, "GND", "GND", "power_in")],
-    "4.5-A power mux; external input wins near-equal valid 5-V inputs")
+    "4.5-A power mux.  PR1=GND disables priority mode; CP2 tied to VCC3V3_AUX "
+    "is what selects IN2 (external 5 V) once the aux rail is up")
 r("442K", "USB5_PROT", "MUX_OV1", description="TPS2121 IN1 5.75-V OV divider top")
 r("100K", "MUX_OV1", "GND", description="TPS2121 IN1 OV divider bottom")
 r("442K", "EXT5_PROT", "MUX_OV2", description="TPS2121 IN2 5.75-V OV divider top")
 r("100K", "MUX_OV2", "GND", description="TPS2121 IN2 OV divider bottom")
 r("22.1K", "MUX_ILM", "GND", description="TPS2121 4.5-A typical output limit")
 c("10nF", "MUX_SS", "GND", description="TPS2121 soft-start")
+# ST is open-drain and needs an external 6-20 kohm pull-up (TPS2121 data
+# sheet, Recommended Operating Conditions, RST).  It is added at the end of
+# this file rather than here: reference designators are assigned in call
+# order, so inserting a resistor mid-file would renumber every later one and
+# invalidate the routed board.
 for _ in range(2):
     c("47uF", "SYS5", "GND", footprint="Capacitor_SMD:C_1210_3225Metric", description="5-V system bulk")
 
@@ -755,6 +761,16 @@ add_ic("U35", "TUSB320LAI", "TUSB320LAIRSW(R)", "Texas Instruments",
 r("900K", "VBUS_RAW", "PWR_USB_VBUS_DET", description="TUSB320 VBUS_DET current limiter")
 c("100nF", "VCC3V3_AUX", "GND", description="TUSB320 local bypass")
 
+# TPS2121 ST is an open-drain status output: it is driven low only while IN2
+# (the external 5 V header) is sourcing OUT, and is high-impedance whenever IN1
+# (USB-C) is sourcing or the output is off.  U10 gate 2 inverts it into
+# EXT_SELECTED, and MAIN_EN = USB_3A_OK OR EXT_SELECTED enables the core buck,
+# so without this pull-up the gate input floats on USB-C power and MAIN_EN can
+# assert regardless of what the TUSB320 advertised.  10 k is inside the
+# datasheet's 6-20 kohm range and matches the other open-drain pull-ups here.
+r("10K", "VCC3V3_AUX", "MUX_ST",
+  description="TPS2121 open-drain status pull-up (RST, 6-20 kohm)")
+
 
 def validate() -> None:
     refs = [x.ref for x in components]

scripts/generate_pcb.py

@@ -198,6 +198,8 @@ SPECIAL.update({
     "C126": (136.0, 78.0, 0), "C127": (90.0, 100.5, 0),
     "R104": (83.0, 86.8, 0), "R105": (83.0, 88.0, 0),
     "R106": (83.0, 89.2, 0), "C128": (93.0, 88.0, 0),
+    # TPS2121 open-drain status pull-up, beside the U10 gate it holds up.
+    "R108": (53.0, 101.6, 0),
 })