Initial Ti375 GNSS IMU board design and documentation

2026-08-15 18:09:17 +03:00
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+# Ana komponent seçimi ve kapasite sınırları
+
+Bu tablolardaki akım değerleri komponent datasheet kapasitesini veya tasarımda
+ayarlanan limiti gösterir. Kartın tamamının aynı anda bu değerleri verebildiği
+anlamına gelmez. Gerçek sürekli güç; 5 V kaynağı, power-path limiti, PCB bakırı,
+indüktör kaybı, ortam sıcaklığı ve termal ölçümle sınırlandırılır.
+
+## İşlem, RF, sensör ve debug komponentleri
+
+| Ref | Parça | Besleme / kapasite | Seçilme nedeni ve karttaki görevi |
+|---|---|---|---|
+| U1 | Efinix Ti375C529C3 | 0.95 V core; 1.8 V AUX/HSIO/config; 3.0/3.3 V HVIO | C529 paket, standart-power C3 core seçeneği. GNSS örnekleme, SafeSPI, QSPI, JTAG ve PMOD mantığını taşır. FPGA akımı HDL kullanımına bağlıdır; sabit bir tüketim değeri kabul edilmez, Efinity power estimator ile hesaplanmalıdır. |
+| U21 | MAX2771ETI+ | 2.7–3.3 V; datasheet varsayılan GNSS modunda yaklaşık 26–27 mA tipik | Tek çip GNSS RF/PLL/IF/ADC. Kartta 3.0 V analog ve dijital LDO'lardan beslenir; iki dahili LNA kapalı, SAW çıkışı doğrudan `MIXIN_HI` girişine gider. |
+| U22 | SCH16T-K01-1 | V3P3 3.0–3.6 V; VDDIO 1.7–3.6 V; 41 mA nominal, 47 mA maksimum | 6 eksen yüksek performanslı IMU. Tam parça varyantı K01-1; 3.3 V SafeSPI ve DRY/SYNC arayüzü kullanılır. |
+| U26 | IS25WP512M-JLLE | 1.8 V, 512 Mbit | Ti375 active-serial konfigürasyon belleği; x1/x2/x4 I/O pinleri doğrudan dedicated config ball'larına gider. |
+| U2 | FT4232H-56Q | 3.3 V I/O, dahili 1.8 V core regülatörü; USB 2.0 High-Speed | Tek USB üzerinden iki JTAG, iki UART ve bir debug GPIO sağlar. FPGA kapalıyken back-power olmaması için çıkışlar U29/U30 ile izole edilir. |
+| U3 | 93LC56BT-I/OT | 3.3 V, x16 organizasyon | FT4232H USB descriptor ve kanal modlarını kalıcı tutar. |
+| U5 | TUSB320LAI | 3.3 V AUX | USB-C UFP/sink rolü, CC1/CC2 üzerindeki entegre Rd ve Type-C akım ilanı algılama. USB'den ana ray yalnızca 3 A ilanı algılandığında etkinleşir. |
+| U6 | TPD2EUSB30A | USB2 düşük kapasitans ESD koruması | D+/D− hattını konektöre yakın korur; yüksek hızlı diferansiyel hattın yükünü düşük tutar. |
+| U23 | Epson TG2016SMN | 3.0 V; 16.368 MHz, ±0.5 ppm | MAX2771 PLL referansı. 10 nF ile MAX2771 XTAL girişine AC bağlanır. |
+| U24 | Epson SG-210STF | 3.0 V; 40.000 MHz, ±25 ppm | MAX2771 ADC sampling clock ve FPGA sistem/capture clockunun ortak kaynağı. İki ayrı 33 ohm source-series kol kullanılır. |
+| U25 | ECS-2520MV | 3.3 V; 12.000 MHz | FT4232H ana saat kaynağı. |
+| FL1 | SF14-1582M5UUS2 | 1565.19–1585.65 MHz; 1.2 dB tipik insertion loss | GPS L1/L1C ön seçim SAW filtresi. |
+| D1 | ESD501DPYR | Yaklaşık 0.3 pF, 12 V RF ESD elemanı | SMA girişini RF hattını fazla yüklemeden korur. |
+| L4 | 0402HPH-56NXJRW | 56 nH; 330 mA; SRF 2.1 GHz; Q yaklaşık 64 | 3.3/5 V aktif anten beslemesini SMA merkez iletkenine veren bias-tee choke. |
+
+## Güç giriş ve regülatör komponentleri
+
+| Ref | Parça | Datasheet / ayarlanan kapasite | Tasarımdaki kullanım |
+|---|---|---|---|
+| U7 | TPS259470A | 2.7–23 V eFuse, cihaz ailesi 5.5 A; RILM ile yaklaşık 2.69 A tipik | USB VBUS için UV≈4.0 V, OV≈5.8 V, current/inrush/reverse-current koruması. USB yolu 3 A Type-C sınırının altında tutulur. |
+| U8 | TPS259470A | 2.7–23 V eFuse; RILM ile yaklaşık 4.04 A tipik | Harici regüle 5 V girişi için aynı korumalar. |
+| U9 | TPS2121 | 2.8–22 V; 4.5 A ayarlanabilir limit; 56 mΩ tipik RON | USB ve harici 5 V arasında reverse-blocking power mux. Geçerli ve yakın gerilimlerde harici giriş önceliklidir. |
+| U12 | TPS7A2033 | 300 mA LDO | Supervisor, Type-C ve FTDI için her zaman açık `VCC3V3_AUX`. |
+| U13 | TPS6287B15 | 2.7–6 V giriş; 15 A sınıfı | Ti375 `VCC0V95` core/VCCA/VDD_SOC rayı. 100 nH, 30 A saturation sınıfı XEL4030 ve differential remote sense kullanır. |
+| U14 | TPS62867 | 2.4–5.5 V giriş; 6 A sınıfı | `VCC1V8` FPGA AUX/config/HSIO rayı. 240 nH, 6.6 A sınıfı indüktör. |
+| U15 | TPS62867 | 2.4–5.5 V giriş; 6 A sınıfı | `VCC3V3` FPGA HVIO/IMU/PMOD rayı. 240 nH, 6.6 A sınıfı indüktör. |
+| U16 | LM3880MF-1AA | 2.7–5.5 V; 1→2→3 ve ters kapanış sırası; yaklaşık 10 ms/kademe seçimi | Core PG geldikten sonra 1.8 V, 3.3 V ve final sequence flag üretir. Çıkışlar open-drain'dir. |
+| U17 | TPS7A2030 | 300 mA LDO | `VCC3V0_RF`: MAX2771 RF/PLL/IF/VCO analog beslemeleri. |
+| U18 | TPS7A2030 | 300 mA LDO | `VCC3V0_DIG`: MAX2771 dijital/ADC ve Ti375 3.0 V bankı. |
+| U19 | TPS7A2030 | 300 mA LDO | `VCC3V0_CLK`: 16.368 MHz TCXO ve 40 MHz XO. |
+| U20 | TPS7A2033 | 300 mA LDO | Aktif anten için temiz 3.3 V seçeneği. |
+| U27 | TPS22944 | Sabit 100 mA current limit | J5 ile seçilen 3.3 V veya 5 V anten biasını sınırlar; `ANT_BIAS_OC` fault çıkışı vardır. |
+| U28 | TPS3808G30 | VDD 1.7–6.5 V; 3.0 V nominal için 2.79 V threshold; CT açıkken 20 ms | Son oluşan 3.0 V FPGA bankını izler ve reset bırakma gecikmesini sağlar. |
+
+## Mantık ve power-domain elemanları
+
+| Ref | Parça | Besleme | Görev |
+|---|---|---|---|
+| U10 | SN74LVC2G02 | 3.3 V AUX | TUSB320'nin 3 A ilanını decode eder ve mux statusunu tersler. |
+| U11 | SN74LVC1G32 | 3.3 V AUX | Geçerli USB 3 A veya seçilmiş harici 5 V koşulundan `MAIN_EN` üretir. |
+| U29 | SN74LVC244A | FPGA 3.3 V | FTDI'den FPGA'ya JTAG/UART çıkış bufferı; Ioff ve ortak aktif-düşük OE. |
+| U30 | SN74LVC1G125 | FPGA 3.3 V | Channel-D debug GPIO için tri-state Ioff buffer. |
+| U31 | SN74LVC1G07 | 3.3 V AUX | FTDI reset isteğini CRESET_N'e açık-drenç aktarır. |
+| U32 | SN74LVC1G07 | 3.3 V AUX | All-power-valid sonucunu CRESET_N'e açık-drenç aktarır. |
+| U33 | SN74LVC1G07 | 1.8 V | Harici/manual reseti 1.8 V CRESET domainine açık-drenç aktarır. |
+| U34 | SN74LVC08A | 3.3 V AUX | Core/1.8/3.3/3.0/sequence valid sinyallerinin dört kapılı AND ağacı. |
+| Q1 | MMBT3904 | Ayrık transistor | `ALL_FPGA_POWER_OK` geçerliyken aktif-düşük FTDI buffer OE üretir. |
+
+## Güç kapasitesi nasıl okunmalı?
+
+- USB girişinde kullanılabilir sürekli akım U7 ayarı ve gerçek Type-C kaynak
+  ilanıyla sınırlıdır; konektörden rastgele 3 A çekildiği varsayılmaz.
+- Harici girişte U8 yaklaşık 4.04 A, U9 ise 4.5 A ayarlıdır; dolayısıyla nominal
+  üst sınır eFuse tarafıdır.
+- 15 A ve 6 A converter değerleri silikon sınıfıdır. Aynı anda maksimum core,
+  1.8 V ve 3.3 V gücü talep etmek 5 V giriş bütçesini aşabilir.
+- PMOD besleme pinleri ayrı current-limit içermez ve ilgili FPGA rayını paylaşır.
+  Takılan modüllerin toplam akımı güç/termal bütçeye dahil edilmelidir.
+- LDO'larda 300 mA elektriksel sınıra yaklaşmadan önce `(VIN−VOUT) × IOUT`
+  paket kaybı ve bakır alanı kontrol edilmelidir.
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+# Ti375 FPGA pin seçimi
+
+Kesin ve makine tarafından doğrulanan kaynak `ti375_pinout.csv` dosyasıdır.
+Bu özet HDL tarafında kullanılacak sinyal adlarını, C529 ball'larını ve bank
+gerilimlerini okunabilir biçimde gösterir.
+
+## Sabit fonksiyonlar
+
+| Sinyal | Ball | Bank | Gerilim | Yön | Bağlantı |
+|---|---|---|---|---|---|
+| `HARD_TCK` | G10 | BR3/BR4 | 3.3 V | input | FT4232H BDBUS0 |
+| `HARD_TMS` | G12 | BR3/BR4 | 3.3 V | input | FT4232H BDBUS3 |
+| `HARD_TDI` | G9 | BR3/BR4 | 3.3 V | input | FT4232H BDBUS1 |
+| `HARD_TDO` | G13 | BR3/BR4 | 3.3 V | output | FT4232H BDBUS2 |
+| `FPGA_CRESET_N` | F9 | 4A/4B | 1.8 V | input | Power/FTDI/external reset fan-in |
+| `FPGA_CDONE` | F8 | 4A/4B | 1.8 V | output | TP14 ve 10k pull-up |
+| `QSPI_CS_N` | A7 | 4A/4B | 1.8 V | output | Flash CS_N |
+| `QSPI_IO3` | B7 | 4A/4B | 1.8 V | bidirectional | Flash IO3/HOLD_N |
+| `QSPI_IO2` | G5 | 4A/4B | 1.8 V | bidirectional | Flash IO2/WP_N |
+| `QSPI_SCLK` | G6 | 4A/4B | 1.8 V | output | Flash CCK |
+| `QSPI_IO0` | H4 | 4A/4B | 1.8 V | bidirectional | Flash IO0 |
+| `QSPI_IO1` | H5 | 4A/4B | 1.8 V | bidirectional | Flash IO1 |
+| `FPGA_TEST_N` | J2 | 4C | 1.8 V | input | 10k pull-up |
+| `FPGA_CSI` | J5 | 4A/4B | 1.8 V | input | 10k pull-up |
+
+## MAX2771
+
+| Sinyal | Ball | Bank | Gerilim | Yön |
+|---|---|---|---|---|
+| `MAX_CLKOUT` | B11 | BR0 | 3.0 V | input |
+| `MAX_I0` | D10 | BR0 | 3.0 V | input |
+| `MAX_I1` | D11 | BR0 | 3.0 V | input |
+| `MAX_Q0` | E10 | BR0 | 3.0 V | input |
+| `MAX_Q1` | E11 | BR0 | 3.0 V | input |
+| `MAX_LD` | F11 | BR0 | 3.0 V | input |
+| `MAX_SCLK` | F16 | TR0 | 3.0 V | output |
+| `MAX_CSN` | F17 | TR0 | 3.0 V | output |
+| `MAX_SDATA` | G16 | TR0 | 3.0 V | bidirectional |
+| `MAX_SHDN` | G17 | TR0 | 3.0 V | output |
+
+## SCH16T-K01
+
+| Sinyal | Ball | Bank | Gerilim | Yön |
+|---|---|---|---|---|
+| `IMU_SCK` | A8 | BR3/BR4 | 3.3 V | output |
+| `IMU_MOSI` | A9 | BR3/BR4 | 3.3 V | output |
+| `IMU_MISO` | B9 | BR3/BR4 | 3.3 V | input |
+| `IMU_CS` | B10 | BR3/BR4 | 3.3 V | output |
+| `IMU_DRY_SYNC` | A11 | TR1 | 3.3 V | bidirectional |
+| `IMU_EXTRESN` | C10 | BR3/BR4 | 3.3 V | output |
+
+## Saat ve USB debug
+
+| Sinyal | Ball | Gerilim | Yön | İşlev |
+|---|---|---|---|---|
+| `CLK_40M_FPGA` | U17 | 3.3 V | input | Clock-capable sistem/ADC saati |
+| `RISCV_TCK` | F12 | 3.3 V | input | FTDI interface A |
+| `RISCV_TDI` | V19 | 3.3 V | input | FTDI interface A |
+| `RISCV_TMS` | P18 | 3.3 V | input | FTDI interface A |
+| `RISCV_TDO` | T18 | 3.3 V | output | FTDI interface A |
+| `UART0_RX` | P17 | 3.3 V | input | FTDI channel C TX |
+| `UART0_TX` | R17 | 3.3 V | output | FTDI channel C RX |
+| `UART1_RX` | R18 | 3.3 V | input | FTDI channel D TX |
+| `UART1_TX` | T19 | 3.3 V | output | FTDI channel D RX |
+| `FTDI_DBG_GPIO` | U19 | 3.3 V | bidirectional | FTDI channel D debug |
+
+## 3.3 V PMOD pinleri
+
+| PMOD | Pin | FPGA ball | Bank |
+|---|---:|---|---|
+| JPMOD1 | 1 | U6 | BL2/BL3 |
+| JPMOD1 | 2 | V4 | BL2/BL3 |
+| JPMOD1 | 3 | A13 | TR1 |
+| JPMOD1 | 4 | C9 | BR3/BR4 |
+| JPMOD1 | 7 | C12 | TR1 |
+| JPMOD1 | 8 | C13 | TR1 |
+| JPMOD1 | 9 | C14 | TR1 |
+| JPMOD1 | 10 | D12 | TR1 |
+| JPMOD2 | 1 | V20 | TL1/TL5 |
+| JPMOD2 | 2 | D13 | TR2 |
+| JPMOD2 | 3 | E13 | TR2 |
+| JPMOD2 | 4 | E14 | TR2 |
+| JPMOD2 | 7 | E16 | TR2 |
+| JPMOD2 | 8 | F13 | TR2 |
+| JPMOD2 | 9 | E15 | TR2 |
+| JPMOD2 | 10 | F14 | TR2 |
+
+## 1.8 V PMOD pinleri
+
+1.8 V konnektörler Ti375 2E HSIO bankındaki düz diferansiyel çiftleri kullanır.
+Bu pinlerde config, PLL input/feedback veya dedicated clock görevi seçilmemiştir.
+Konnektör tek uçlu GPIO olarak kullanılabilir; kullanıcı HDL'i I/O standardını
+1.8 V seçmelidir.
+
+| PMOD | Pin | FPGA ball | HSIO çifti |
+|---|---:|---|---|
+| JPMOD3 | 1 | C20 | 51 P |
+| JPMOD3 | 2 | B20 | 51 N |
+| JPMOD3 | 3 | C17 | 52 P |
+| JPMOD3 | 4 | B17 | 52 N |
+| JPMOD3 | 7 | A16 | 53 P |
+| JPMOD3 | 8 | A17 | 53 N |
+| JPMOD3 | 9 | C19 | 54 P |
+| JPMOD3 | 10 | B19 | 54 N |
+| JPMOD4 | 1 | B14 | 55 P |
+| JPMOD4 | 2 | A14 | 55 N |
+| JPMOD4 | 3 | J18 | 56 P |
+| JPMOD4 | 4 | H18 | 56 N |
+| JPMOD4 | 7 | A18 | 57 P |
+| JPMOD4 | 8 | A19 | 57 N |
+| JPMOD4 | 9 | D16 | 58 P |
+| JPMOD4 | 10 | D17 | 58 N |
+
+Her Digilent 2x6 konnektörde pin 5/11 GND, pin 6/12 ilgili beslemedir.
+Konnektörler 5 V toleranslı değildir.
+
+## Neden diğer GPIO'lar dışarı çıkarılmadı?
+
+C529 paketindeki ball sayısı kullanıcı GPIO sayısı değildir. Paket; çok sayıda
+GND, core/AUX/VCCIO beslemesi, reference resistor, konfigürasyon, JTAG ve özel
+işlev ball'ı içerir. Tasarım yalnızca 32 PMOD GPIO'yu dışarı çıkarır. Geri kalan
+fabric GPIO'ların kullanıldı/boş durumu `unused_gpio_inventory.csv` dosyasında
+tek tek bulunur.
@@ -0,0 +1,175 @@
+# Arayüzler ve net bağlantıları
+
+Bu dokümanda ok yönü veri akışını gösterir. Parantez içindeki değer seri
+sonlandırma veya bias elemanıdır.
+
+## MAX2771 RF zinciri
+
+```text
+J2 SMA merkez
+  -> RF_SMA
+  -> D1 ESD501 (şönt ESD)
+  -> C83 27 pF DC block
+  -> RF_PRE_SAW
+  -> FL1 SF14-1582M5UUS2 GPS L1/L1C SAW
+  -> RF_POST_SAW
+  -> R39 0 ohm tuning link
+  -> MAX_MIXIN_HI
+  -> U21 pin 25 MIXIN_HI
+```
+
+`C84` (`RF_POST_SAW`-GND) ve `C85` (`MAX_MIXIN_HI`-GND) tuning şönt
+footprintleridir ve varsayılan olarak DNP'dir. Böylece VNA ölçümünden sonra
+pi-match kurulabilir. MAX2771'in LNAIN_HI/LNAIN_LO ve LNA çıkışları bağlı
+değildir; register 0 her iki LNA'yı kapatır ve yüksek-band mixer girişi seçilir.
+
+Aktif anten bias yolu:
+
+```text
+J5 pin 1 = temiz 3.3 V
+J5 pin 2 = ANT_BIAS_SEL
+J5 pin 3 = SYS5
+
+şönt 1-2 -> 3.3 V bias
+şönt 2-3 -> 5 V bias
+şönt yok -> OFF
+
+ANT_BIAS_SEL -> U27 TPS22944, 100 mA limit
+             -> ANT_BIAS_SW -> L4 56 nH -> RF_SMA -> anten
+```
+
+`TP3 ANT OC`, U27'nin aktif-düşük over-current göstergesidir. Bias devresi
+RF hattına L4 üzerinden girer; RF sinyali güç rayına taşınmamalıdır.
+
+## MAX2771 saat, SPI ve ADC arayüzü
+
+Saat ağacı:
+
+```text
+U23 16.368 MHz TCXO -> C90 10 nF -> U21 pin 3 XTAL
+
+U24 40.000 MHz XO --+-> R44 33R -> U21 pin 5 ADC_CLKIN
+                    +-> R56 33R -> U1 ball U17 CLK_40M_FPGA
+
+U21 pin 4 CLKOUT -> R45 22R -> U1 ball B11 MAX_CLKOUT
+```
+
+`MAX_CLKOUT`, ADC örnekleme saatinin FPGA'ya source-synchronous kopyasıdır.
+FPGA veri yakalama mantığı I/Q bitlerini bu saatle örneklemelidir.
+
+Üç telli kontrol arayüzü:
+
+| İşlev | FPGA | Seri eleman | MAX2771 |
+|---|---|---|---|
+| SCLK | U1 F16 `MAX_SCLK`, output, 3.0 V | R51 22R | U21 pin 8 `SCLK` |
+| CS_N | U1 F17 `MAX_CSN`, output, 3.0 V | R52 22R | U21 pin 9 `CSN` |
+| SDATA | U1 G16 `MAX_SDATA`, bidirectional, 3.0 V | R53 22R | U21 pin 7 `SDATA` |
+| Shutdown | U1 G17 `MAX_SHDN`, output, 3.0 V | R54 22R | U21 pin 18 `SHDN` |
+
+SDATA ayrı MOSI/MISO değildir; MAX2771'in tek bidirectional üç telli veri
+hattıdır. `R55=100 kohm`, MAX2771 tarafındaki SHDN pinini FPGA konfigüre olana
+kadar düşük tutar.
+
+ADC/status çıkışları:
+
+| MAX2771 pini | Seri eleman | FPGA ball/net | Yön |
+|---|---|---|---|
+| pin 10 Q1 | R49 22R | E11 `MAX_Q1` | MAX2771 -> FPGA |
+| pin 11 Q0 | R48 22R | E10 `MAX_Q0` | MAX2771 -> FPGA |
+| pin 12 I0 | R46 22R | D10 `MAX_I0` | MAX2771 -> FPGA |
+| pin 13 I1 | R47 22R | D11 `MAX_I1` | MAX2771 -> FPGA |
+| pin 17 LD | R50 22R | F11 `MAX_LD` | MAX2771 -> FPGA |
+| pin 4 CLKOUT | R45 22R | B11 `MAX_CLKOUT` | MAX2771 -> FPGA |
+
+Tüm bu pinler Ti375 BR0 bankındadır ve `VCC3V0_DIG=3.0 V` kullanır. SCLK,
+CSN, SDATA ve SHDN ise aynı 3.0 V standardındaki TR0 bankındadır.
+
+Başlangıç register görüntüsünün önemli seçimleri:
+
+| Register | Değer | Karar |
+|---|---|---|
+| 0x0 | `0xBEA71619` | MIXIN_HI, iki LNA kapalı, 23.4 MHz 5. derece LPF |
+| 0x3 | `0x698C0008` | Integer-N GPS L1 PLL |
+| 0x4 | `0x00C08080` | NDIV=1540, RDIV=16; 1575.42 MHz |
+| 0x7 | `0x110061B2` | Harici 40 MHz ADC sampling clock |
+| 0xA | `0x010061B4` | ADC sampling clocku CLKOUT'a yönlendir |
+
+Tam görüntü `max2771_registers.csv` dosyasındadır.
+
+## SCH16T-K01 SafeSPI arayüzü
+
+| İşlev | FPGA ball/net | Seri eleman | SCH16T pini | Yön |
+|---|---|---|---|---|
+| SCK | A8 `IMU_SCK` | R57 22R, FPGA yanında | pin 21 SCK | FPGA -> IMU |
+| MOSI | A9 `IMU_MOSI` | R58 22R, FPGA yanında | pin 23 MOSI | FPGA -> IMU |
+| CS_N | B10 `IMU_CS` | R59 22R, FPGA yanında | pin 22 CS | FPGA -> IMU |
+| MISO | B9 `IMU_MISO` | R60 22R, IMU yanında | pin 19 MISO | IMU -> FPGA |
+| Data-ready / sync | A11 `IMU_DRY_SYNC` | doğrudan | pin 20 DRY_SYNC | çift yönlü |
+| Harici reset | C10 `IMU_EXTRESN` | R61 10k pulldown | pin 6 EXTRESN | FPGA -> IMU |
+
+SafeSPI clock mode 0 kullanılır. SCH16T V3P3 girişleri `VCC3V3` üzerinden FB1
+600 ohm@100 MHz ferritle `IMU_3V3` rayına ayrılır. VDDIO doğrudan 3.3 V'tur.
+Murata'nın dahili regülatör pinlerinde C105 10 uF (`VREGA2`) ve C106 1 uF
+(`VREGD`) bulunur. `IMU_EXTRESN` pulldown nedeniyle FPGA resetten çıkıp pini
+aktif olarak yükseltmeden sensör çalışmaya başlamaz.
+
+## FPGA konfigürasyon flashı
+
+| IS25WP512M pini | Net | Ti375 ball / dedicated işlev |
+|---|---|---|
+| 1 CS_N | `QSPI_CS_N` | A7 / SSL_N |
+| 2 IO1 | `QSPI_IO1` | H5 / CDI1 |
+| 3 IO2 | `QSPI_IO2` | G5 / CDI2 |
+| 5 IO0 | `QSPI_IO0` | H4 / CDI0 |
+| 6 SCLK | `QSPI_SCLK` | G6 / CCK_PLLIN0 |
+| 7 IO3 | `QSPI_IO3` | B7 / CDI3 |
+| 8 VCC | `VCC1V8` | 1.8 V config domain |
+
+CS_N, IO2/WP_N ve IO3/HOLD_N 10 kohm ile 1.8 V'a çekilir. Ti375 `TEST_N`,
+`CSI` ve open-drain `CDONE` pinlerinde de Efinix'in istediği 10 kohm 1.8 V
+pull-up'lar vardır.
+
+## FT4232H arayüzleri
+
+| USB interface | FTDI pinleri | FPGA işlevi | FPGA ball'ları |
+|---|---|---|---|
+| A / interface 0 | ADBUS0 TCK, 1 TDI, 2 TDO, 3 TMS | RISC-V JTAG | F12, V19, T18, P18 |
+| B / interface 1 | BDBUS0 TCK, 1 TDI, 2 TDO, 3 TMS | FPGA hard JTAG | G10, G9, G13, G12 |
+| B | BDBUS4 | Aktif-düşük FPGA reset isteği | CRESET_N open-drain fan-in |
+| C / interface 2 | CDBUS0 TXD, CDBUS1 RXD | UART0 | P17 RX, R17 TX |
+| D / interface 3 | DDBUS0 TXD, DDBUS1 RXD | UART1 | R18 RX, T19 TX |
+| D | DDBUS2 | Debug GPIO | U19 |
+
+FTDI'den FPGA'ya giden TCK/TDI/TMS, UART RX ve debug çıkışları U29/U30
+bufferlarından ve ardından 33 ohm seri dirençlerden geçer. FPGA'dan FTDI'ye
+giden TDO/UART TX yönleri 33 ohm seri dirençlidir. JTAG hatlarının FPGA
+tarafında 10 kohm idle pull-up vardır.
+
+## USB-C güç ve veri
+
+- J1 CC1/CC2 -> U5 TUSB320LAI; PORT=GND ile UFP/sink.
+- J1 D+/D− -> U6 TPD2EUSB30A -> R63/R64 27 ohm -> U2 FT4232H.
+- J1 VBUS -> U7 TPS259470A -> `USB5_PROT` -> U9 TPS2121 -> `SYS5`.
+- Harici J3 5 V -> U8 TPS259470A -> `EXT5_PROT` -> U9 TPS2121 -> `SYS5`.
+- U10/U11, USB 3 A ilanı veya seçilmiş harici kaynak yoksa ana FPGA güç
+  converterlarını kapalı tutar.
+
+## Test noktaları
+
+| TP | Net | Amaç |
+|---|---|---|
+| TP1 | `U7_FLT` | USB eFuse fault |
+| TP2 | `U8_FLT` | Harici giriş eFuse fault |
+| TP3 | `ANT_BIAS_OC` | Aktif anten over-current |
+| TP4 | `VBUS_RAW` | USB VBUS |
+| TP5 | `EXT5_RAW` | Harici 5 V giriş |
+| TP6 | `SYS5` | Seçilmiş sistem 5 V |
+| TP7 | `VCC3V3_AUX` | Her zaman açık yardımcı 3.3 V |
+| TP8 | `VCC0V95` | FPGA core 0.95 V |
+| TP9 | `VCC1V8` | FPGA AUX/config 1.8 V |
+| TP10 | `VCC3V3` | FPGA/IMU/PMOD 3.3 V |
+| TP11 | `VCC3V0_RF` | MAX2771 analog 3.0 V |
+| TP12 | `VCC3V0_DIG` | MAX2771/FPGA bank 3.0 V |
+| TP13 | `FPGA_CRESET_N` | FPGA reset durumu |
+| TP14 | `FPGA_CDONE` | Konfigürasyon tamamlandı |
+| TP15 | `GND` | Ölçüm referansı |
@@ -0,0 +1,93 @@
+# Güç ağacı, sıralama ve reset
+
+## Giriş yolu
+
+```text
+USB-C VBUS -> U7 TPS259470A (2.69 A typ) -> USB5_PROT --+
+                                                          +-> U9 TPS2121 -> SYS5
+EXT_5V ----> U8 TPS259470A (4.04 A typ) -> EXT5_PROT --+
+```
+
+Her iki eFuse yaklaşık 4.0 V UV ve 5.8 V OV eşiğine, kontrollü output slew'a,
+fault test noktasına ve true reverse-current blocking'e sahiptir. U9 4.5 A
+limitli power mux'tur; yakın geçerli girişlerde harici 5 V yolu önceliklidir.
+
+USB yolunda TUSB320 CC ilanı U10 tarafından decode edilir. `MAIN_EN`, yalnızca
+USB kaynağı 3 A ilan ettiğinde veya harici giriş gerçekten U9 tarafından
+seçildiğinde yükselir. `VCC3V3_AUX` ise U12 üzerinden SYS5 var olduğu sürece
+supervisor/debug mantığını besler.
+
+## Ray üretimi
+
+| Sıra | Ray | Regülatör | Nominal kapasite | Yükler |
+|---:|---|---|---:|---|
+| 0 | `VCC3V3_AUX` | U12 TPS7A2033 | 300 mA | TUSB320, FT4232H I/O/regülatör, EEPROM, supervisor ve reset mantığı |
+| 1 | `VCC0V95` | U13 TPS6287B15 | 15 A sınıfı | Ti375 VCC/VCCA/VDD_SOC |
+| 2 | `VCC1V8` | U14 TPS62867 | 6 A sınıfı | Ti375 VCCAUX/config/HSIO, QSPI, iki 1.8 V PMOD |
+| 3 | `VCC3V3` | U15 TPS62867 | 6 A sınıfı | Ti375 HVIO, SCH16T, FTDI izolasyon bufferları, iki 3.3 V PMOD |
+| 4 | `VCC3V0_RF` | U17 TPS7A2030 | 300 mA | MAX2771 RF/PLL/IF/VCO |
+| 4 | `VCC3V0_DIG` | U18 TPS7A2030 | 300 mA | MAX2771 digital/ADC, Ti375 BR0/TR0 VCCIO |
+| 4 | `VCC3V0_CLK` | U19 TPS7A2030 | 300 mA | 16.368 MHz ve 40 MHz osilatörler |
+| bağımsız | `VCC3V3_ANT` | U20 TPS7A2033 | 300 mA | J5 3.3 V aktif anten seçeneği; U27 çıkışı 100 mA ile sınırlar |
+
+Bu tablo regulator sınıfını gösterir. Toplam çıkış gücü `SYS5` giriş gücünü,
+eFuse/mux limitini ve termal sınırı aşamaz.
+
+## FPGA açılış sırası
+
+1. `MAIN_EN`, U13 core buck'ı etkinleştirir.
+2. 0.95 V regülasyona girince U13 `CORE_PG` yükselir.
+3. `CORE_PG`, U16 LM3880'i başlatır.
+4. `SEQ_FLAG1` U14'ü açar; `VCC1V8` oluşur ve U14 `PG_1V8` verir.
+5. `SEQ_FLAG2` U15'i açar; `VCC3V3` oluşur ve U15 `PG_3V3` verir.
+6. 3.3 V LDO'ları açarak üç 3.0 V rayını oluşturur.
+7. U28 `VCC3V0_DIG > 2.79 V` gördükten sonra CT açık seçimiyle yaklaşık
+   20 ms bekler ve `FPGA_POWER_OK_N` bırakılır.
+8. U34 aşağıdaki mantığı üretir:
+
+```text
+ALL_FPGA_POWER_OK = CORE_PG
+                  AND PG_1V8
+                  AND PG_3V3
+                  AND FPGA_POWER_OK_N
+                  AND SEQ_FLAG3
+```
+
+9. Sonuç doğru olunca U32 CRESET_N'i bırakır ve Q1 U29/U30 buffer OE'yi açar.
+
+## Reset kaynakları
+
+| Kaynak | Koşul | CRESET yolu |
+|---|---|---|
+| Power valid | `ALL_FPGA_POWER_OK=0` | U32 açık-drenç çıkış low |
+| FTDI | BDBUS4 low | U31 açık-drenç çıkış low |
+| Kart butonu | SW1 basılı | U33 açık-drenç çıkış low |
+| Harici | J4 pin 1 GND'ye çekilir | 1k/4.7nF filtre, U33 açık-drenç output low |
+
+CRESET_N üzerinde tek pull-up R35=10 kohm ile `VCC1V8`'adır. Hiçbir reset
+sürücüsü high sürmez; dolayısıyla farklı power domain çıkışları çatışmaz.
+Harici reset pini dry-contact/open-drain girişidir, harici bir gerilim kaynağı
+değildir.
+
+## Kapanış davranışı
+
+Bir izlenen ray bozulduğunda ilgili PG düşer, U34 sonucu hemen düşük olur,
+CRESET_N çekilir ve FTDI'nin FPGA'ya doğru sürücüleri high-Z yapılır. Bu yapı
+yalnızca boot sırası için değil brown-out/back-power koruması için de kullanılır.
+LM3880 power-down sırasında FLAG3→FLAG2→FLAG1 ters sırasını uygular.
+
+## Ölçüm sırası
+
+İlk enerjilemede akım limitli laboratuvar kaynağı kullanılmalı ve şu sıra
+osiloskopla doğrulanmalıdır:
+
+1. TP6 `SYS5` ve TP7 `VCC3V3_AUX`.
+2. TP8 `VCC0V95`.
+3. TP9 `VCC1V8`.
+4. TP10 `VCC3V3`.
+5. TP12 `VCC3V0_DIG`.
+6. TP13 `FPGA_CRESET_N` ve TP14 `FPGA_CDONE`.
+
+TP13, son rail valid olduktan yaklaşık 20 ms sonra yükselmelidir. Boot
+tamamlandığında TP14 yükselmelidir. Gerçek inrush ve steady-state akımları
+ölçülmeden PMOD veya aktif anten yükü bağlanmamalıdır.
@@ -0,0 +1,40 @@
+# Türetilmiş tasarım verileri
+
+Bu klasördeki CSV/ISF dosyaları elle düzenlenecek ana tasarım kaynağı değildir;
+`scripts/design_data.py` ve `scripts/generate_design_tables.py` üzerinden tekrar
+üretilir.
+
+Okunabilir tasarım dokümanları:
+
+- `COMPONENT_SELECTION.md`: ana IC seçimi, besleme ve kapasite sınırları.
+- `INTERFACES.md`: RF, MAX2771, SafeSPI, QSPI, FTDI/USB ve test noktaları.
+- `FPGA_PINOUT.md`: FPGA ball/bank/gerilim ve dört PMOD eşlemesi.
+- `POWER_TREE.md`: giriş power-path, rail sıralaması, supervisor ve reset.
+
+| Dosya | Açıklama |
+|---|---|
+| `ti375_c529_package.csv` | Efinity 2025.2 Ti375C529 paket veritabanından çıkarılmış 529 ball kaydı |
+| `ti375_c529_package.meta.json` | Paket verisinin kaynak/sürüm metadatası |
+| `ti375_pinout.csv` | Kartta kullanılan sinyal, ball, bank, VCCIO, I/O standardı ve konnektör eşlemesi |
+| `unused_gpio_inventory.csv` | Kullanılan ve fiziksel olarak boş bırakılan fabric GPIO envanteri |
+| `ti375_pin_constraints.isf` | HDL/Efinity tarafı için pin ve I/O standardı constraintleri |
+| `max2771_registers.csv` | Kartın MAX2771 başlangıç register görüntüsü |
+
+Yeniden üretmek için:
+
+```bash
+python3 scripts/generate_design_tables.py
+```
+
+Script aşağıdaki koşulları doğrular:
+
+- Paket kaynağında tam 529 benzersiz ball bulunması.
+- Dedicated TCK/TMS/TDI/TDO, CRESET_N, CDONE ve JTAG_VCCIO_SEL adları.
+- Seçilen bankın istenen 3.3 V, 3.0 V veya 1.8 V I/O standardını desteklemesi.
+- PMOD tahsislerinde konfigürasyon/PLL/clock özel fonksiyonlarının yanlışlıkla
+  kullanılmaması.
+- MAX2771 ve SCH16T için ayrılmış pinlerle PMOD çakışması olmaması.
+
+Hard JTAG yalnızca kart üzerindeki FT4232H interface 1 üzerinden erişilir;
+harici ARM/JTAG headerı yoktur. `FPGA_CRESET_N`, açık-drenç power/FTDI/harici
+reset fan-in'i olarak belgelenmiştir.
@@ -0,0 +1,12 @@
+address,value_hex,default_hex,changed,purpose
+0x0,0xBEA71619,0xBEA41603,yes,"MIXIN_HI, both LNAs disabled, 23.4 MHz 5th-order LPF, 36 MHz mixer pole"
+0x1,0x20550288,0x20550288,no,Preserve MAX2771 documented reset/default value
+0x2,0x0EAFA1DC,0x0EAFA1DC,no,Preserve MAX2771 documented reset/default value
+0x3,0x698C0008,0x698C0008,no,Integer-N L1 PLL
+0x4,0x00C08080,0x00C00080,yes,"NDIV=1540, RDIV=16: 16.368 MHz / 16 * 1540 = 1575.42 MHz"
+0x5,0x08000070,0x08000070,no,Preserve MAX2771 documented reset/default value
+0x6,0x08000000,0x08000000,no,Preserve MAX2771 documented reset/default value
+0x7,0x110061B2,0x010061B2,yes,External 40 MHz ADC sampling clock on ADC_CLKIN
+0x8,0x01E0F401,0x01E0F401,no,Preserve MAX2771 documented reset/default value
+0x9,0x00C00002,0x00C00002,no,Preserve MAX2771 documented reset/default value
+0xA,0x010061B4,0x010061B0,yes,Route ADC sampling clock to CLKOUT for source-synchronous FPGA capture
@@ -0,0 +1,530 @@
+ball,official_pad_name,die_bank,package_bank,bank_class,allowed_vccio_v,direction,function,periphery_instances,instance_pin,special_capability,fabric_gpio
+A1,GND,,,HARD/POWER,,power,Ground,,,,no
+A2,GPIOB_P_30_CDI9_PLLIN0,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_30,P,PLL_INPUT;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+A3,GPIOB_N_32,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_32,N,DIFFERENTIAL_MEMBER,yes
+A4,GPIOB_P_32,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_32,P,DIFFERENTIAL_MEMBER,yes
+A5,GND,,,HARD/POWER,,power,Ground,,,,no
+A6,GPIOB_N_35,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_35,N,DIFFERENTIAL_MEMBER,yes
+A7,GPIOB_N_38_SSL_N,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_38,N,DIFFERENTIAL_MEMBER,yes
+A8,GPIOR_170,BR3,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_170,,,yes
+A9,GPIOR_171,BR3,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_171,,,yes
+A10,GND,,,HARD/POWER,,power,Ground,,,,no
+A11,GPIOR_93_PLLIN1,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_93,,PLL_INPUT,yes
+A12,GPIOR_95_CLK12,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_95,,CLOCK_CAPABLE,yes
+A13,GPIOR_94,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_94,,,yes
+A14,GPIOT_N_55,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_55,N,DIFFERENTIAL_MEMBER,yes
+A15,GND,,,HARD/POWER,,power,Ground,,,,no
+A16,GPIOT_P_53,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_53,P,DIFFERENTIAL_MEMBER,yes
+A17,GPIOT_N_53,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_53,N,DIFFERENTIAL_MEMBER,yes
+A18,GPIOT_P_57,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_57,P,DIFFERENTIAL_MEMBER,yes
+A19,GPIOT_N_57,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_57,N,DIFFERENTIAL_MEMBER,yes
+A20,GND,,,HARD/POWER,,power,Ground,,,,no
+A21,GPIOT_N_33_CLK16_N,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_33,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+A22,GPIOT_N_26,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_26,N,DIFFERENTIAL_MEMBER,yes
+A23,GND,,,HARD/POWER,,power,Ground,,,,no
+AA1,GND,,,HARD/POWER,,power,Ground,,,,no
+AA2,DDR0_DQ[6],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[6],,no
+AA3,VDDQX_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AA4,DDR0_DQS[0],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQS[0],,no
+AA5,GND,,,HARD/POWER,,power,Ground,,,,no
+AA6,DDR0_DQ[8],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[8],,no
+AA7,DDR0_DQS[1],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQS[1],,no
+AA8,DDR0_DQS_N[1],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQS_N[1],,no
+AA9,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AA10,GND,,,HARD/POWER,,power,Ground,,,,no
+AA11,DDR0_CKE[0],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CKE[0],,no
+AA12,NC,,,HARD/POWER,,,,,,,no
+AA13,DDR0_A[2],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,A[2],,no
+AA14,DDR0_A[3],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,A[3],,no
+AA15,GND,,,HARD/POWER,,power,Ground,,,,no
+AA16,DDR0_DQ[23],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[23],,no
+AA17,DDR0_DQS_N[2],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQS_N[2],,no
+AA18,VDDQX_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AA19,DDR0_DQ[28],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[28],,no
+AA20,GND,,,HARD/POWER,,power,Ground,,,,no
+AA21,DDR0_DQS[3],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQS[3],,no
+AA22,DDR0_DQ[25],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[25],,no
+AA23,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AB1,DDR0_DQ[7],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[7],,no
+AB2,DDR0_DQ[4],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[4],,no
+AB3,GND,,,HARD/POWER,,power,Ground,,,,no
+AB4,DDR0_DQS_N[0],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQS_N[0],,no
+AB5,DDR0_DQ[14],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[14],,no
+AB6,VDDQX_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AB7,DDR0_DM[1],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DM[1],,no
+AB8,GND,,,HARD/POWER,,power,Ground,,,,no
+AB9,DDR0_CS_N[2],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CS_N[2],,no
+AB10,DDR0_CS_N[1],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CS_N[1],,no
+AB11,DDR0_CK_N,DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CK_N,DIFFERENTIAL_MEMBER,no
+AB12,DDR0_A[0],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,A[0],,no
+AB13,GND,,,HARD/POWER,,power,Ground,,,,no
+AB14,NC,,,HARD/POWER,,,,,,,no
+AB15,DDR0_DM[2],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DM[2],,no
+AB16,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AB17,DDR0_DQS[2],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQS[2],,no
+AB18,GND,,,HARD/POWER,,power,Ground,,,,no
+AB19,DDR0_DQ[19],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[19],,no
+AB20,DDR0_DM[3],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DM[3],,no
+AB21,DDR0_DQS_N[3],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQS_N[3],,no
+AB22,GND,,,HARD/POWER,,power,Ground,,,,no
+AB23,DDR0_DQ[26],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[26],,no
+AC1,GND,,,HARD/POWER,,power,Ground,,,,no
+AC2,DDR0_DQ[5],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[5],,no
+AC3,DDR0_DM[0],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DM[0],,no
+AC4,VDDQX_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AC5,DDR0_DQ[15],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[15],,no
+AC6,GND,,,HARD/POWER,,power,Ground,,,,no
+AC7,DDR0_DQ[12],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[12],,no
+AC8,DDR0_DQ[13],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[13],,no
+AC9,GND,,,HARD/POWER,,power,Ground,,,,no
+AC10,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AC11,DDR0_CK,DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CK,,no
+AC12,GND,,,HARD/POWER,,power,Ground,,,,no
+AC13,DDR0_A[1],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,A[1],,no
+AC14,NC,,,HARD/POWER,,,,,,,no
+AC15,DDR0_A[4],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,A[4],,no
+AC16,GND,,,HARD/POWER,,power,Ground,,,,no
+AC17,DDR0_DQ[16],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[16],,no
+AC18,VDDQX_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AC19,DDR0_DQ[18],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[18],,no
+AC20,GND,,,HARD/POWER,,power,Ground,,,,no
+AC21,VDDQX_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AC22,DDR0_DQ[27],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[27],,no
+AC23,GND,,,HARD/POWER,,power,Ground,,,,no
+B1,GPIOB_P_21,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_21,P,DIFFERENTIAL_MEMBER,yes
+B2,GPIOB_N_30_CDI8,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_30,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+B3,GND,,,HARD/POWER,,power,Ground,,,,no
+B4,GPIOB_N_31,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_31,N,DIFFERENTIAL_MEMBER,yes
+B5,GPIOB_N_34,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_34,N,DIFFERENTIAL_MEMBER,yes
+B6,GPIOB_P_35,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_35,P,DIFFERENTIAL_MEMBER,yes
+B7,GPIOB_P_38_CDI3,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_38,P,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+B8,GND,,,HARD/POWER,,power,Ground,,,,no
+B9,GPIOR_168,BR3,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_168,,,yes
+B10,GPIOR_169,BR3,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_169,,,yes
+B11,GPIOR_143_CLK9,BR0,BR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_143,,CLOCK_CAPABLE,yes
+B12,GPIOR_96_CLK13,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_96,,CLOCK_CAPABLE,yes
+B13,VCCIO33_TR1,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,power,VCCIO Power,,,,no
+B14,GPIOT_P_55,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_55,P,DIFFERENTIAL_MEMBER,yes
+B15,GPIOT_P_62_PLLIN0,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_62,P,PLL_INPUT;DIFFERENTIAL_MEMBER,yes
+B16,GPIOT_N_62,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_62,N,DIFFERENTIAL_MEMBER,yes
+B17,GPIOT_N_52,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_52,N,DIFFERENTIAL_MEMBER,yes
+B18,VCCIO2E,2E,2E,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+B19,GPIOT_N_54,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_54,N,DIFFERENTIAL_MEMBER,yes
+B20,GPIOT_N_51,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_51,N,DIFFERENTIAL_MEMBER,yes
+B21,GPIOT_P_33_CLK16_P,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_33,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+B22,GPIOT_N_27,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_27,N,DIFFERENTIAL_MEMBER,yes
+B23,GPIOT_P_26,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_26,P,DIFFERENTIAL_MEMBER,yes
+C1,GND,,,HARD/POWER,,power,Ground,,,,no
+C2,GPIOB_N_21,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_21,N,DIFFERENTIAL_MEMBER,yes
+C3,GPIOB_P_27,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_27,P,DIFFERENTIAL_MEMBER,yes
+C4,GPIOB_P_31,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_31,P,DIFFERENTIAL_MEMBER,yes
+C5,GPIOB_P_34,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_34,P,DIFFERENTIAL_MEMBER,yes
+C6,VCCIO4A_4B,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+C7,GPIOB_N_41,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_41,N,DIFFERENTIAL_MEMBER,yes
+C8,JTAG_VCCIO_SEL,4A,4A_4B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+C9,GPIOR_166,BR3,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_166,,,yes
+C10,GPIOR_167,BR3,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_167,,,yes
+C11,VCCIO33_BR0,BR0,BR0,HVIO,1.8;2.5;3.0;3.3,power,VCCIO Power,,,,no
+C12,GPIOR_99,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_99,,,yes
+C13,GPIOR_98,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_98,,,yes
+C14,GPIOR_97,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_97,,,yes
+C15,GPIOT_N_59,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_59,N,DIFFERENTIAL_MEMBER,yes
+C16,VCCIO2E,2E,2E,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+C17,GPIOT_P_52,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_52,P,DIFFERENTIAL_MEMBER,yes
+C18,GPIOT_N_60,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_60,N,DIFFERENTIAL_MEMBER,yes
+C19,GPIOT_P_54,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_54,P,DIFFERENTIAL_MEMBER,yes
+C20,GPIOT_P_51,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_51,P,DIFFERENTIAL_MEMBER,yes
+C21,GND,,,HARD/POWER,,power,Ground,,,,no
+C22,GPIOT_P_27,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_27,P,DIFFERENTIAL_MEMBER,yes
+C23,GND,,,HARD/POWER,,power,Ground,,,,no
+D1,GPIOB_P_20_CLK7_P,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_20,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+D2,GPIOB_N_20_CLK7_N,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_20,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+D3,GPIOB_N_27,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_27,N,DIFFERENTIAL_MEMBER,yes
+D4,VCCIO4A_4B,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+D5,GPIOB_N_37_CDI4,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_37,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+D6,GPIOB_P_37_CDI5,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_37,P,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+D7,GPIOB_P_41,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_41,P,DIFFERENTIAL_MEMBER,yes
+D8,GPIOB_N_44_CLK11_N,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_44,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+D9,VCCIO33_BR3_BR4,BR4,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,power,VCCIO Power,,,,no
+D10,GPIOR_144,BR0,BR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_144,,,yes
+D11,GPIOR_142_CLK8,BR0,BR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_142,,CLOCK_CAPABLE,yes
+D12,GPIOR_100,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_100,,,yes
+D13,GPIOR_102,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_102,,,yes
+D14,GND,,,HARD/POWER,,power,Ground,,,,no
+D15,GPIOT_P_59_PLLIN0,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_59,P,PLL_INPUT;DIFFERENTIAL_MEMBER,yes
+D16,GPIOT_P_58,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_58,P,DIFFERENTIAL_MEMBER,yes
+D17,GPIOT_N_58,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_58,N,DIFFERENTIAL_MEMBER,yes
+D18,GPIOT_P_60_EXTFB,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_60,P,PLL_EXTFB;DIFFERENTIAL_MEMBER,yes
+D19,GND,,,HARD/POWER,,power,Ground,,,,no
+D20,GPIOT_N_36_CLK19_N,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_36,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+D21,GPIOT_N_29,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_29,N,DIFFERENTIAL_MEMBER,yes
+D22,GPIOT_P_25,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_25,P,DIFFERENTIAL_MEMBER,yes
+D23,GPIOT_N_25,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_25,N,DIFFERENTIAL_MEMBER,yes
+E1,GPIOB_P_18_CLK5_P,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_18,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+E2,VCCIO4C,4C,4C,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+E3,GPIOB_P_24_CDI15,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_24,P,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+E4,GPIOB_N_36_CDI6,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_36,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+E5,GPIOB_P_36_CDI7,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_36,P,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+E6,GPIOB_N_42,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_42,N,DIFFERENTIAL_MEMBER,yes
+E7,GND,,,HARD/POWER,,power,Ground,,,,no
+E8,GPIOB_P_44_CLK11_P,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_44,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+E9,GPIOR_165_PLLIN1,BR3,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_165,,PLL_INPUT,yes
+E10,GPIOR_145_PLLIN1,BR0,BR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_145,,PLL_INPUT,yes
+E11,GPIOR_140_PLLIN1,BR0,BR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_140,,PLL_INPUT,yes
+E12,GND,,,HARD/POWER,,power,Ground,,,,no
+E13,GPIOR_103,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_103,,,yes
+E14,GPIOR_104,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_104,,,yes
+E15,GPIOR_107,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_107,,,yes
+E16,GPIOR_105,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_105,,,yes
+E17,GND,,,HARD/POWER,,power,Ground,,,,no
+E18,GPIOT_N_61,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_61,N,DIFFERENTIAL_MEMBER,yes
+E19,GPIOT_N_64_CLK15_N,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_64,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+E20,GPIOT_P_36_CLK19_P,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_36,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+E21,GPIOT_P_29,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_29,P,DIFFERENTIAL_MEMBER,yes
+E22,VCCIO2C,2C,2C,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+E23,GPIOT_N_23,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_23,N,DIFFERENTIAL_MEMBER,yes
+F1,GPIOB_N_18_CLK5_N,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_18,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+F2,GPIOB_P_17_CLK4_P,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_17,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+F3,GPIOB_N_24_CDI14,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_24,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+F4,GPIOB_N_33,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_33,N,DIFFERENTIAL_MEMBER,yes
+F5,VCCIO4A_4B,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+F6,GPIOB_P_42,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_42,P,DIFFERENTIAL_MEMBER,yes
+F7,VQPS,BR,BR,HARD/POWER,,power,,,,,no
+F8,CDONE,4A,4A_4B,HSIO,1.2;1.35;1.5;1.8,output,Configuration,,,,no
+F9,CRESET_N,4A,4A_4B,HSIO,1.2;1.35;1.5;1.8,input,Configuration,,,DIFFERENTIAL_MEMBER,no
+F10,GND,,,HARD/POWER,,power,Ground,,,,no
+F11,GPIOR_141,BR0,BR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_141,,,yes
+F12,GPIOR_101_PLLIN1,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_101,,PLL_INPUT,yes
+F13,GPIOR_106,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_106,,,yes
+F14,GPIOR_108,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_108,,,yes
+F15,VCCIO33_TR2,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,power,VCCIO Power,,,,no
+F16,GPIOR_90,TR0,TR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_90,,,yes
+F17,GPIOR_91,TR0,TR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_91,,,yes
+F18,GPIOT_P_61_EXTFB,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_61,P,PLL_EXTFB;DIFFERENTIAL_MEMBER,yes
+F19,GPIOT_P_64_CLK15_P,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_64,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+F20,VCCIO2C,2C,2C,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+F21,GPIOT_P_35_CLK18_P,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_35,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+F22,GPIOT_N_35_CLK18_N,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_35,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+F23,GPIOT_P_23_PLLIN0,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_23,P,PLL_INPUT;DIFFERENTIAL_MEMBER,yes
+G1,GPIOB_P_23_CBSEL1,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_23,P,CONFIG_BOOT_SELECT;DIFFERENTIAL_MEMBER,yes
+G2,GPIOB_N_17_CLK4_N,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_17,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+G3,GND,,,HARD/POWER,,power,Ground,,,,no
+G4,GPIOB_P_33,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_33,P,DIFFERENTIAL_MEMBER,yes
+G5,GPIOB_N_39_CDI2,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_39,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+G6,GPIOB_P_39_CCK_PLLIN0,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_39,P,PLL_INPUT;DIFFERENTIAL_MEMBER,yes
+G7,VCCA_BR,BR,BR,HARD/POWER,,power,,,,,no
+G8,GND,,,HARD/POWER,,power,Ground,,,,no
+G9,TDI,BR4,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,input,Configuration,JTAG_USER1;JTAG_USER2;JTAG_USER3;JTAG_USER4,,,no
+G10,TCK,BR4,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,input,Configuration,JTAG_USER1;JTAG_USER2;JTAG_USER3;JTAG_USER4,,,no
+G11,VCCAUX,,,HARD/POWER,,power,,,,,no
+G12,TMS,BR4,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,input,Configuration,JTAG_USER1;JTAG_USER2;JTAG_USER3;JTAG_USER4,,,no
+G13,TDO,BR4,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,output,Configuration,JTAG_USER1;JTAG_USER2;JTAG_USER3;JTAG_USER4,,,no
+G14,VCCAUX,,,HARD/POWER,,power,,,,,no
+G15,GPIOR_88_PLLIN1,TR0,TR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_88,,PLL_INPUT,yes
+G16,GPIOR_89,TR0,TR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_89,,,yes
+G17,GPIOR_92,TR0,TR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_92,,,yes
+G18,VCCIO2E,2E,2E,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+G19,GPIOT_N_63_CLK14_N,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_63,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+G20,GPIOT_N_34_CLK17_N,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_34,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+G21,GPIOT_P_28,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_28,P,DIFFERENTIAL_MEMBER,yes
+G22,GPIOT_N_28,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_28,N,DIFFERENTIAL_MEMBER,yes
+G23,GND,,,HARD/POWER,,power,Ground,,,,no
+H1,GND,,,HARD/POWER,,power,Ground,,,,no
+H2,GPIOB_N_23_CBSEL0,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_23,N,CONFIG_BOOT_SELECT;DIFFERENTIAL_MEMBER,yes
+H3,GPIOB_P_28,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_28,P,DIFFERENTIAL_MEMBER,yes
+H4,GPIOB_N_40_CDI0,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_40,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+H5,GPIOB_P_40_CDI1_EXTFB,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_40,P,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+H6,VCCIO4A_4B,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+H7,VCCAUX,,,HARD/POWER,,power,,,,,no
+H8,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+H9,GND,,,HARD/POWER,,power,Ground,,,,no
+H10,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+H11,GND,,,HARD/POWER,,power,Ground,,,,no
+H12,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+H13,GND,,,HARD/POWER,,power,Ground,,,,no
+H14,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+H15,GND,,,HARD/POWER,,power,Ground,,,,no
+H16,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+H17,VCCIO33_TR0,TR0,TR0,HVIO,1.8;2.5;3.0;3.3,power,VCCIO Power,,,,no
+H18,GPIOT_N_56,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_56,N,DIFFERENTIAL_MEMBER,yes
+H19,GPIOT_P_63_CLK14_P,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_63,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+H20,GPIOT_P_34_CLK17_P,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_34,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+H21,VCCIO2C,2C,2C,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+H22,GPIOT_P_24_EXTFB,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_24,P,PLL_EXTFB;DIFFERENTIAL_MEMBER,yes
+H23,GPIOT_N_24,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_24,N,DIFFERENTIAL_MEMBER,yes
+J1,GPIOB_P_19_NSTATUS_CLK6_P,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_19,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+J2,GPIOB_N_19_TEST_N_CLK6_N,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_19,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+J3,GPIOB_N_28,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_28,N,DIFFERENTIAL_MEMBER,yes
+J4,VCCIO4C,4C,4C,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+J5,GPIOB_N_43_CSI_CLK10_N,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_43,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+J6,GPIOB_P_43_CSO_CLK10_P,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_43,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+J7,REF_RES_4A,4A,4A_4B,HSIO,1.2;1.35;1.5;1.8,input,,,,,no
+J8,GND,,,HARD/POWER,,power,Ground,,,,no
+J9,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+J10,GND,,,HARD/POWER,,power,Ground,,,,no
+J11,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+J12,GND,,,HARD/POWER,,power,Ground,,,,no
+J13,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+J14,GND,,,HARD/POWER,,power,Ground,,,,no
+J15,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+J16,GND,,,HARD/POWER,,power,Ground,,,,no
+J17,REF_RES_2E,2E,2E,HSIO,1.2;1.35;1.5;1.8,input,,,,,no
+J18,GPIOT_P_56,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_56,P,DIFFERENTIAL_MEMBER,yes
+J19,GND,,,HARD/POWER,,power,Ground,,,,no
+J20,GPIOT_P_17,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_17,P,DIFFERENTIAL_MEMBER,yes
+J21,GPIOT_P_16,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_16,P,DIFFERENTIAL_MEMBER,yes
+J22,GPIOT_P_10_CLK27_P,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_10,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+J23,GPIOT_N_10_CLK27_N,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_10,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+K1,GPIOB_P_14_CDI19_CLK1_P,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_14,P,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+K2,GND,,,HARD/POWER,,power,Ground,,,,no
+K3,GPIOB_P_29_CDI11_EXTFB,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_29,P,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+K4,GPIOB_N_29_CDI10,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_29,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+K5,GPIOB_P_26_EXTSPICLK,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_26,P,CLOCK_CAPABLE;EXT_SPI;DIFFERENTIAL_MEMBER,yes
+K6,GPIOB_P_25_CDI13,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_25,P,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+K7,REF_RES_4B,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,input,,,,,no
+K8,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+K9,GND,,,HARD/POWER,,power,Ground,,,,no
+K10,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+K11,GND,,,HARD/POWER,,power,Ground,,,,no
+K12,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+K13,GND,,,HARD/POWER,,power,Ground,,,,no
+K14,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+K15,GND,,,HARD/POWER,,power,Ground,,,,no
+K16,VCCA_TR,TR,TR,HARD/POWER,,power,,,,,no
+K17,GND,,,HARD/POWER,,power,Ground,,,,no
+K18,GPIOT_P_49_EXTFB,2D,2D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_49,P,PLL_EXTFB;DIFFERENTIAL_MEMBER,yes
+K19,GPIOT_N_49,2D,2D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_49,N,DIFFERENTIAL_MEMBER,yes
+K20,GPIOT_N_17,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_17,N,DIFFERENTIAL_MEMBER,yes
+K21,GPIOT_N_16,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_16,N,DIFFERENTIAL_MEMBER,yes
+K22,VCCIO2B,2B,2B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+K23,GPIOT_P_21,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_21,P,DIFFERENTIAL_MEMBER,yes
+L1,GPIOB_N_14_CDI18_CLK1_N,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_14,N,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+L2,GPIOB_P_15_CDI17_CLK2_P,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_15,P,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+L3,GPIOB_P_11,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_11,P,DIFFERENTIAL_MEMBER,yes
+L4,GPIOB_N_26_SSU_N,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_26,N,DIFFERENTIAL_MEMBER,yes
+L5,VCCIO4C,4C,4C,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+L6,GPIOB_N_25_CDI12,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_25,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+L7,VCCAUX,,,HARD/POWER,,power,,,,,no
+L8,GND,,,HARD/POWER,,power,Ground,,,,no
+L9,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+L10,GND,,,HARD/POWER,,power,Ground,,,,no
+L11,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+L12,GND,,,HARD/POWER,,power,Ground,,,,no
+L13,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+L14,GND,,,HARD/POWER,,power,Ground,,,,no
+L15,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+L16,VCCAUX,,,HARD/POWER,,power,,,,,no
+L17,GPIOT_P_50_PLLIN0,2D,2D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_50,P,PLL_INPUT;DIFFERENTIAL_MEMBER,yes
+L18,GPIOT_N_50,2D,2D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_50,N,DIFFERENTIAL_MEMBER,yes
+L19,GPIOT_P_20,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_20,P,DIFFERENTIAL_MEMBER,yes
+L20,VCCIO2B,2B,2B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+L21,GPIOT_P_11_CLK30_P,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_11,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+L22,GPIOT_N_11_CLK30_N,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_11,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+L23,GPIOT_N_21,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_21,N,DIFFERENTIAL_MEMBER,yes
+M1,GPIOB_P_09,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_09,P,DIFFERENTIAL_MEMBER,yes
+M2,GPIOB_N_15_CDI16_CLK2_N,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_15,N,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+M3,VCCIO4D,4D,4D,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+M4,GPIOB_N_11,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_11,N,DIFFERENTIAL_MEMBER,yes
+M5,GPIOB_P_22,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_22,P,DIFFERENTIAL_MEMBER,yes
+M6,GPIOB_N_22,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_22,N,DIFFERENTIAL_MEMBER,yes
+M7,REF_RES_4D,4D,4D,HSIO,1.2;1.35;1.5;1.8,input,,,,,no
+M8,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+M9,GND,,,HARD/POWER,,power,Ground,,,,no
+M10,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+M11,GND,,,HARD/POWER,,power,Ground,,,,no
+M12,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+M13,GND,,,HARD/POWER,,power,Ground,,,,no
+M14,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+M15,GND,,,HARD/POWER,,power,Ground,,,,no
+M16,GPIOT_P_43,2D,2D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_43,P,DIFFERENTIAL_MEMBER,yes
+M17,GPIOT_N_43,2D,2D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_43,N,DIFFERENTIAL_MEMBER,yes
+M18,VCCIO2D,2D,2D,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+M19,GPIOT_N_20,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_20,N,DIFFERENTIAL_MEMBER,yes
+M20,GPIOT_P_13_PLLIN0,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_13,P,PLL_INPUT;DIFFERENTIAL_MEMBER,yes
+M21,GPIOT_P_22,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_22,P,DIFFERENTIAL_MEMBER,yes
+M22,GPIOT_N_22,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_22,N,DIFFERENTIAL_MEMBER,yes
+M23,GND,,,HARD/POWER,,power,Ground,,,,no
+N1,GND,,,HARD/POWER,,power,Ground,,,,no
+N2,GPIOB_N_09,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_09,N,DIFFERENTIAL_MEMBER,yes
+N3,GPIOB_P_13_CDI21_CLK0_P,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_13,P,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+N4,GPIOB_N_12,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_12,N,DIFFERENTIAL_MEMBER,yes
+N5,GPIOB_P_12,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_12,P,DIFFERENTIAL_MEMBER,yes
+N6,GND,,,HARD/POWER,,power,Ground,,,,no
+N7,GPIOB_P_08_CDI22_EXTFB,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_08,P,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+N8,GND,,,HARD/POWER,,power,Ground,,,,no
+N9,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+N10,GND,,,HARD/POWER,,power,Ground,,,,no
+N11,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+N12,GND,,,HARD/POWER,,power,Ground,,,,no
+N13,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+N14,GND,,,HARD/POWER,,power,Ground,,,,no
+N15,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+N16,GND,,,HARD/POWER,,power,Ground,,,,no
+N17,GPIOT_P_40_CLK23_P,2D,2D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_40,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+N18,GPIOT_N_40_CLK23_N,2D,2D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_40,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+N19,GPIOT_P_14_EXTFB,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_14,P,PLL_EXTFB;DIFFERENTIAL_MEMBER,yes
+N20,GPIOT_N_13,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_13,N,DIFFERENTIAL_MEMBER,yes
+N21,VCCIO2B,2B,2B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+N22,GPIOT_P_15,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_15,P,DIFFERENTIAL_MEMBER,yes
+N23,GPIOT_N_15,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_15,N,DIFFERENTIAL_MEMBER,yes
+P1,GPIOB_N_16_CLK3_N,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_16,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+P2,GPIOB_P_16_CLK3_P,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_16,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+P3,GPIOB_N_13_CDI20_CLK0_N,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_13,N,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+P4,VCCIO4D,4D,4D,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+P5,GPIOB_P_06_CDI26_EXTFB,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_06,P,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+P6,GPIOB_P_05_CDI28_PLLIN0,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_05,P,PLL_INPUT;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+P7,GPIOB_N_08,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_08,N,DIFFERENTIAL_MEMBER,yes
+P8,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+P9,GND,,,HARD/POWER,,power,Ground,,,,no
+P10,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+P11,GND,,,HARD/POWER,,power,Ground,,,,no
+P12,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+P13,GND,,,HARD/POWER,,power,Ground,,,,no
+P14,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+P15,GND,,,HARD/POWER,,power,Ground,,,,no
+P16,VCCAUX,,,HARD/POWER,,power,,,,,no
+P17,GPIOL_84,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_84,,,yes
+P18,GPIOL_80_CLK29,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_80,,CLOCK_CAPABLE,yes
+P19,GND,,,HARD/POWER,,power,Ground,,,,no
+P20,GPIOT_N_14,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_14,N,DIFFERENTIAL_MEMBER,yes
+P21,GPIOT_P_18,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_18,P,DIFFERENTIAL_MEMBER,yes
+P22,GPIOT_N_18,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_18,N,DIFFERENTIAL_MEMBER,yes
+P23,GPIOT_P_09_CLK26_P,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_09,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+R1,GPIOB_P_04_CDI30_EXTFB,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_04,P,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+R2,VCCIO4D,4D,4D,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+R3,GPIOB_N_07_CDI23,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_07,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+R4,GPIOB_P_07_CDI24_PLLIN0,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_07,P,PLL_INPUT;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+R5,GPIOB_N_06_CDI25,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_06,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+R6,GPIOB_N_05_CDI27,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_05,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+R7,VCCAUX,,,HARD/POWER,,power,,,,,no
+R8,GND,,,HARD/POWER,,power,Ground,,,,no
+R9,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+R10,GND,,,HARD/POWER,,power,Ground,,,,no
+R11,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+R12,GND,,,HARD/POWER,,power,Ground,,,,no
+R13,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+R14,GND,,,HARD/POWER,,power,Ground,,,,no
+R15,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+R16,GND,,,HARD/POWER,,power,Ground,,,,no
+R17,GPIOL_85_PLLIN1,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_85,,PLL_INPUT,yes
+R18,GPIOL_87_PLLIN1,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_87,,PLL_INPUT,yes
+R19,GPIOT_P_19,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_19,P,DIFFERENTIAL_MEMBER,yes
+R20,GPIOT_N_19,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_19,N,DIFFERENTIAL_MEMBER,yes
+R21,GPIOT_P_12_CLK31_P,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_12,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+R22,VCCIO2B,2B,2B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+R23,GPIOT_N_09_CLK26_N,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_09,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+T1,GPIOB_N_04_CDI29,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_04,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+T2,GPIOB_N_10,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_10,N,DIFFERENTIAL_MEMBER,yes
+T3,GPIOB_P_10,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_10,P,DIFFERENTIAL_MEMBER,yes
+T4,GPIOL_27_CLK25,BL3,BL2_BL3,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_27,,CLOCK_CAPABLE,yes
+T5,GND,,,HARD/POWER,,power,Ground,,,,no
+T6,VDD_SOC,SOC,SOC,HARD/POWER,,power,,,,,no
+T7,GND,,,HARD/POWER,,power,Ground,,,,no
+T8,VCCA_BL2,BL,BL,HARD/POWER,,power,,,,,no
+T9,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+T10,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+T11,GND,,,HARD/POWER,,power,Ground,,,,no
+T12,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+T13,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+T14,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+T15,GND,,,HARD/POWER,,power,Ground,,,,no
+T16,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+T17,VCCIO33_TL1_TL5,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,power,VCCIO Power,,,,no
+T18,GPIOL_83,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_83,,,yes
+T19,GPIOL_86,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_86,,,yes
+T20,VCCIO2A,2A,2A,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+T21,GPIOT_N_12_CLK31_N,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_12,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+T22,GPIOT_P_08_PLLIN0,2A,2A,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_08,P,PLL_INPUT;DIFFERENTIAL_MEMBER,yes
+T23,GPIOT_N_08,2A,2A,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_08,N,DIFFERENTIAL_MEMBER,yes
+U1,GPIOB_N_03_CDI31,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_03,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+U2,GPIOB_P_03_PLLIN0,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_03,P,PLL_INPUT;DIFFERENTIAL_MEMBER,yes
+U3,VCCIO4D,4D,4D,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+U4,GPIOL_25_PLLIN1,BL2,BL2_BL3,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_25,,PLL_INPUT,yes
+U5,GPIOL_34_PLLIN1,BL3,BL2_BL3,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_34,,PLL_INPUT,yes
+U6,GPIOL_24,BL2,BL2_BL3,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_24,,,yes
+U7,VDD_SOC,SOC,SOC,HARD/POWER,,power,,,,,no
+U8,VCCA_BL0_BL1,BL,BL,HARD/POWER,,power,,,,,no
+U9,GND,,,HARD/POWER,,power,Ground,,,,no
+U10,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+U11,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+U12,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+U13,GND,,,HARD/POWER,,power,Ground,,,,no
+U14,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+U15,VCCA_TL2,TL,TL,HARD/POWER,,power,,,,,no
+U16,VCCA_TL0_TL1,TL,TL,HARD/POWER,,power,,,,,no
+U17,GPIOL_79_CLK28,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_79,,CLOCK_CAPABLE,yes
+U18,GND,,,HARD/POWER,,power,Ground,,,,no
+U19,GPIOL_52_PLLIN1,TL1,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_52,,PLL_INPUT,yes
+U20,REF_RES_2A,2A,2A,HSIO,1.2;1.35;1.5;1.8,input,,,,,no
+U21,GPIOT_P_05,2A,2A,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_05,P,DIFFERENTIAL_MEMBER,yes
+U22,GPIOT_N_05,2A,2A,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_05,N,DIFFERENTIAL_MEMBER,yes
+U23,GND,,,HARD/POWER,,power,Ground,,,,no
+V1,GND,,,HARD/POWER,,power,Ground,,,,no
+V2,GPIOL_26_CLK24,BL3,BL2_BL3,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_26,,CLOCK_CAPABLE,yes
+V3,GPIOL_32_PLLIN1,BL3,BL2_BL3,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_32,,PLL_INPUT,yes
+V4,GPIOL_23,BL2,BL2_BL3,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_23,,,yes
+V5,VCCIO33_BL2_BL3,BL3,BL2_BL3,HVIO,1.8;2.5;3.0;3.3,power,VCCIO Power,,,,no
+V6,VDD_SOC,SOC,SOC,HARD/POWER,,power,,,,,no
+V7,GND,,,HARD/POWER,,power,Ground,,,,no
+V8,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+V9,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+V10,VDDQ_CK_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+V11,GND,,,HARD/POWER,,power,Ground,,,,no
+V12,VDDPLL_MCB_TOP_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+V13,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+V14,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+V15,GND,,,HARD/POWER,,power,Ground,,,,no
+V16,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+V17,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+V18,VCCIO33_TL1_TL5,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,power,VCCIO Power,,,,no
+V19,GPIOL_46,TL1,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_46,,,yes
+V20,GPIOL_45,TL1,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_45,,,yes
+V21,GND,,,HARD/POWER,,power,Ground,,,,no
+V22,GPIOT_P_07_EXTFB,2A,2A,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_07,P,PLL_EXTFB;DIFFERENTIAL_MEMBER,yes
+V23,GPIOT_N_07,2A,2A,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_07,N,DIFFERENTIAL_MEMBER,yes
+W1,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W2,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W3,VDDQX_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W4,GND,,,HARD/POWER,,power,Ground,,,,no
+W5,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W6,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W7,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W8,DDR0_DQ[11],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[11],,no
+W9,GND,,,HARD/POWER,,power,Ground,,,,no
+W10,DDR0_CKE[1],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CKE[1],,no
+W11,DDR0_CAL,DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CAL,,no
+W12,NC,,,HARD/POWER,,,,,,,no
+W13,NC,,,HARD/POWER,,,,,,,no
+W14,GND,,,HARD/POWER,,power,Ground,,,,no
+W15,DDR0_DQ[21],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[21],,no
+W16,DDR0_DQ[20],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[20],,no
+W17,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W18,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W19,GND,,,HARD/POWER,,power,Ground,,,,no
+W20,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W21,VDDQX_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W22,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W23,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+Y1,DDR0_DQ[0],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[0],,no
+Y2,GND,,,HARD/POWER,,power,Ground,,,,no
+Y3,DDR0_DQ[1],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[1],,no
+Y4,DDR0_DQ[2],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[2],,no
+Y5,DDR0_DQ[3],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[3],,no
+Y6,DDR0_DQ[10],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[10],,no
+Y7,GND,,,HARD/POWER,,power,Ground,,,,no
+Y8,DDR0_DQ[9],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[9],,no
+Y9,DDR0_CS_N[3],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CS_N[3],,no
+Y10,DDR0_CS_N[0],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CS_N[0],,no
+Y11,DDR0_RST_N,DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,RST_N,DIFFERENTIAL_MEMBER,no
+Y12,GND,,,HARD/POWER,,power,Ground,,,,no
+Y13,NC,,,HARD/POWER,,,,,,,no
+Y14,DDR0_A[5],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,A[5],,no
+Y15,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+Y16,DDR0_DQ[22],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[22],,no
+Y17,GND,,,HARD/POWER,,power,Ground,,,,no
+Y18,DDR0_DQ[17],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[17],,no
+Y19,DDR0_DQ[30],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[30],,no
+Y20,DDR0_DQ[29],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[29],,no
+Y21,DDR0_DQ[31],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[31],,no
+Y22,GND,,,HARD/POWER,,power,Ground,,,,no
+Y23,DDR0_DQ[24],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[24],,no
@@ -0,0 +1,27 @@
+{
+  "device": "Ti375C529",
+  "fabric_gpio_count": 227,
+  "mapped_device": "opx_466x964_b56_d28_bc529",
+  "package": "529-ball FBGA",
+  "package_banks": [
+    "2A",
+    "2B",
+    "2C",
+    "2D",
+    "2E",
+    "4A_4B",
+    "4C",
+    "4D",
+    "BL2_BL3",
+    "BR0",
+    "BR3_BR4",
+    "TL1_TL5",
+    "TR0",
+    "TR1",
+    "TR2"
+  ],
+  "package_status": "final",
+  "row_count": 529,
+  "source_database": "/tools/efinix/efinity/2025.2/pt/db/resource/Ti375C529.db",
+  "source_sha256": "ef752ff9cb71fed702254a9ee4dc74050fc33ab01f03b2a327a8e034864cfbe6"
+}
@@ -0,0 +1,74 @@
+# Efinity interface constraints generated from the official Ti375C529 database.
+# Verify port names against the final RTL top level before importing.
+set_pin_assignment -pin_name U17 -port_name CLK_40M_FPGA
+set_pin_assignment -pin_name F8 -port_name FPGA_CDONE
+set_pin_assignment -pin_name F9 -port_name FPGA_CRESET_N
+set_pin_assignment -pin_name J5 -port_name FPGA_CSI
+set_pin_assignment -pin_name J2 -port_name FPGA_TEST_N
+set_pin_assignment -pin_name U19 -port_name FTDI_DBG_GPIO
+set_pin_assignment -pin_name G10 -port_name HARD_TCK
+set_pin_assignment -pin_name G9 -port_name HARD_TDI
+set_pin_assignment -pin_name G13 -port_name HARD_TDO
+set_pin_assignment -pin_name G12 -port_name HARD_TMS
+set_pin_assignment -pin_name B10 -port_name IMU_CS
+set_pin_assignment -pin_name A11 -port_name IMU_DRY_SYNC
+set_pin_assignment -pin_name C10 -port_name IMU_EXTRESN
+set_pin_assignment -pin_name B9 -port_name IMU_MISO
+set_pin_assignment -pin_name A9 -port_name IMU_MOSI
+set_pin_assignment -pin_name A8 -port_name IMU_SCK
+set_pin_assignment -pin_name B11 -port_name MAX_CLKOUT
+set_pin_assignment -pin_name F17 -port_name MAX_CSN
+set_pin_assignment -pin_name D10 -port_name MAX_I0
+set_pin_assignment -pin_name D11 -port_name MAX_I1
+set_pin_assignment -pin_name F11 -port_name MAX_LD
+set_pin_assignment -pin_name E10 -port_name MAX_Q0
+set_pin_assignment -pin_name E11 -port_name MAX_Q1
+set_pin_assignment -pin_name F16 -port_name MAX_SCLK
+set_pin_assignment -pin_name G16 -port_name MAX_SDATA
+set_pin_assignment -pin_name G17 -port_name MAX_SHDN
+set_pin_assignment -pin_name U6 -port_name PMOD1_1
+set_pin_assignment -pin_name D12 -port_name PMOD1_10
+set_pin_assignment -pin_name V4 -port_name PMOD1_2
+set_pin_assignment -pin_name A13 -port_name PMOD1_3
+set_pin_assignment -pin_name C9 -port_name PMOD1_4
+set_pin_assignment -pin_name C12 -port_name PMOD1_7
+set_pin_assignment -pin_name C13 -port_name PMOD1_8
+set_pin_assignment -pin_name C14 -port_name PMOD1_9
+set_pin_assignment -pin_name V20 -port_name PMOD2_1
+set_pin_assignment -pin_name F14 -port_name PMOD2_10
+set_pin_assignment -pin_name D13 -port_name PMOD2_2
+set_pin_assignment -pin_name E13 -port_name PMOD2_3
+set_pin_assignment -pin_name E14 -port_name PMOD2_4
+set_pin_assignment -pin_name E16 -port_name PMOD2_7
+set_pin_assignment -pin_name F13 -port_name PMOD2_8
+set_pin_assignment -pin_name E15 -port_name PMOD2_9
+set_pin_assignment -pin_name C20 -port_name PMOD3_1
+set_pin_assignment -pin_name B19 -port_name PMOD3_10
+set_pin_assignment -pin_name B20 -port_name PMOD3_2
+set_pin_assignment -pin_name C17 -port_name PMOD3_3
+set_pin_assignment -pin_name B17 -port_name PMOD3_4
+set_pin_assignment -pin_name A16 -port_name PMOD3_7
+set_pin_assignment -pin_name A17 -port_name PMOD3_8
+set_pin_assignment -pin_name C19 -port_name PMOD3_9
+set_pin_assignment -pin_name B14 -port_name PMOD4_1
+set_pin_assignment -pin_name D17 -port_name PMOD4_10
+set_pin_assignment -pin_name A14 -port_name PMOD4_2
+set_pin_assignment -pin_name J18 -port_name PMOD4_3
+set_pin_assignment -pin_name H18 -port_name PMOD4_4
+set_pin_assignment -pin_name A18 -port_name PMOD4_7
+set_pin_assignment -pin_name A19 -port_name PMOD4_8
+set_pin_assignment -pin_name D16 -port_name PMOD4_9
+set_pin_assignment -pin_name A7 -port_name QSPI_CS_N
+set_pin_assignment -pin_name H4 -port_name QSPI_IO0
+set_pin_assignment -pin_name H5 -port_name QSPI_IO1
+set_pin_assignment -pin_name G5 -port_name QSPI_IO2
+set_pin_assignment -pin_name B7 -port_name QSPI_IO3
+set_pin_assignment -pin_name G6 -port_name QSPI_SCLK
+set_pin_assignment -pin_name F12 -port_name RISCV_TCK
+set_pin_assignment -pin_name V19 -port_name RISCV_TDI
+set_pin_assignment -pin_name T18 -port_name RISCV_TDO
+set_pin_assignment -pin_name P18 -port_name RISCV_TMS
+set_pin_assignment -pin_name P17 -port_name UART0_RX
+set_pin_assignment -pin_name R17 -port_name UART0_TX
+set_pin_assignment -pin_name R18 -port_name UART1_RX
+set_pin_assignment -pin_name T19 -port_name UART1_TX
@@ -0,0 +1,73 @@
+signal,ball,official_pin_name,die_bank,package_bank,vccio,io_standard,direction,clock_capability,special_function,subsystem,connector,connector_pin,note
+IMU_DRY_SYNC,A11,GPIOR_93_PLLIN1,TR1,TR1,3.3 V,3.3 V LVCMOS,bidirectional,no,PLL_INPUT,sch16t,on-board,,Murata multiplexed Data Ready output / SYNC input
+PMOD1_3,A13,GPIOR_94,TR1,TR1,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr1,JPMOD1,3,PMOD 1 pin 3
+PMOD4_2,A14,GPIOT_N_55,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD4,2,PMOD 4 pin 2; HSIO pair 55 N
+PMOD3_7,A16,GPIOT_P_53,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD3,7,PMOD 3 pin 7; HSIO pair 53 P
+PMOD3_8,A17,GPIOT_N_53,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD3,8,PMOD 3 pin 8; HSIO pair 53 N
+PMOD4_7,A18,GPIOT_P_57,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD4,7,PMOD 4 pin 7; HSIO pair 57 P
+PMOD4_8,A19,GPIOT_N_57,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD4,8,PMOD 4 pin 8; HSIO pair 57 N
+QSPI_CS_N,A7,GPIOB_N_38_SSL_N,4B,4A_4B,1.8 V,1.8 V LVCMOS,output,no,DIFFERENTIAL_MEMBER,configuration,on-board,,SPI-active SSL_N
+IMU_SCK,A8,GPIOR_170,BR3,BR3_BR4,3.3 V,3.3 V LVCMOS,output,no,,sch16t,on-board,,SafeSPI mode-0 clock
+IMU_MOSI,A9,GPIOR_171,BR3,BR3_BR4,3.3 V,3.3 V LVCMOS,output,no,,sch16t,on-board,,SafeSPI controller-to-sensor data
+IMU_CS,B10,GPIOR_169,BR3,BR3_BR4,3.3 V,3.3 V LVCMOS,output,no,,sch16t,on-board,,SafeSPI active-low chip select
+MAX_CLKOUT,B11,GPIOR_143_CLK9,BR0,BR0,3.0 V,3.0 V LVCMOS,input,yes,CLOCK_CAPABLE,max2771,on-board,,Source-synchronous ADC capture clock on dedicated clock-capable input
+PMOD4_1,B14,GPIOT_P_55,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD4,1,PMOD 4 pin 1; HSIO pair 55 P
+PMOD3_4,B17,GPIOT_N_52,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD3,4,PMOD 3 pin 4; HSIO pair 52 N
+PMOD3_10,B19,GPIOT_N_54,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD3,10,PMOD 3 pin 10; HSIO pair 54 N
+PMOD3_2,B20,GPIOT_N_51,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD3,2,PMOD 3 pin 2; HSIO pair 51 N
+QSPI_IO3,B7,GPIOB_P_38_CDI3,4B,4A_4B,1.8 V,1.8 V LVCMOS,bidirectional,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,configuration,on-board,,SPI-active CDI3
+IMU_MISO,B9,GPIOR_168,BR3,BR3_BR4,3.3 V,3.3 V LVCMOS,input,no,,sch16t,on-board,,SafeSPI sensor-to-controller data
+IMU_EXTRESN,C10,GPIOR_167,BR3,BR3_BR4,3.3 V,3.3 V LVCMOS,output,no,,sch16t,on-board,,External active-low reset
+PMOD1_7,C12,GPIOR_99,TR1,TR1,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr1,JPMOD1,7,PMOD 1 pin 7
+PMOD1_8,C13,GPIOR_98,TR1,TR1,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr1,JPMOD1,8,PMOD 1 pin 8
+PMOD1_9,C14,GPIOR_97,TR1,TR1,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr1,JPMOD1,9,PMOD 1 pin 9
+PMOD3_3,C17,GPIOT_P_52,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD3,3,PMOD 3 pin 3; HSIO pair 52 P
+PMOD3_9,C19,GPIOT_P_54,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD3,9,PMOD 3 pin 9; HSIO pair 54 P
+PMOD3_1,C20,GPIOT_P_51,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD3,1,PMOD 3 pin 1; HSIO pair 51 P
+PMOD1_4,C9,GPIOR_166,BR3,BR3_BR4,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_3v3,JPMOD1,4,PMOD 1 pin 4; plain HVIO GPIO
+MAX_I0,D10,GPIOR_144,BR0,BR0,3.0 V,3.0 V LVCMOS,input,no,,max2771,on-board,,ADC I bit 0
+MAX_I1,D11,GPIOR_142_CLK8,BR0,BR0,3.0 V,3.0 V LVCMOS,input,yes,CLOCK_CAPABLE,max2771,on-board,,ADC I bit 1; clock-capable pad retained in same BR0 bank
+PMOD1_10,D12,GPIOR_100,TR1,TR1,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr1,JPMOD1,10,PMOD 1 pin 10
+PMOD2_2,D13,GPIOR_102,TR2,TR2,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr2,JPMOD2,2,PMOD 2 pin 2
+PMOD4_9,D16,GPIOT_P_58,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD4,9,PMOD 4 pin 9; HSIO pair 58 P
+PMOD4_10,D17,GPIOT_N_58,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD4,10,PMOD 4 pin 10; HSIO pair 58 N
+MAX_Q0,E10,GPIOR_145_PLLIN1,BR0,BR0,3.0 V,3.0 V LVCMOS,input,no,PLL_INPUT,max2771,on-board,,ADC Q bit 0; PLL-capable pad in same BR0 bank
+MAX_Q1,E11,GPIOR_140_PLLIN1,BR0,BR0,3.0 V,3.0 V LVCMOS,input,no,PLL_INPUT,max2771,on-board,,ADC Q bit 1; PLL-capable pad in same BR0 bank
+PMOD2_3,E13,GPIOR_103,TR2,TR2,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr2,JPMOD2,3,PMOD 2 pin 3
+PMOD2_4,E14,GPIOR_104,TR2,TR2,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr2,JPMOD2,4,PMOD 2 pin 4
+PMOD2_9,E15,GPIOR_107,TR2,TR2,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr2,JPMOD2,9,PMOD 2 pin 9
+PMOD2_7,E16,GPIOR_105,TR2,TR2,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr2,JPMOD2,7,PMOD 2 pin 7
+MAX_LD,F11,GPIOR_141,BR0,BR0,3.0 V,3.0 V LVCMOS,input,no,,max2771,on-board,,PLL lock status
+RISCV_TCK,F12,GPIOR_101_PLLIN1,TR2,TR2,3.3 V,3.3 V LVCMOS,input,no,PLL_INPUT,secondary_jtag,on-board,,Fabric RISC-V JTAG clock moved off the plain-GPIO PMOD allocation
+PMOD2_8,F13,GPIOR_106,TR2,TR2,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr2,JPMOD2,8,PMOD 2 pin 8
+PMOD2_10,F14,GPIOR_108,TR2,TR2,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr2,JPMOD2,10,PMOD 2 pin 10
+MAX_SCLK,F16,GPIOR_90,TR0,TR0,3.0 V,3.0 V LVCMOS,output,no,,max2771,on-board,,Three-wire serial clock
+MAX_CSN,F17,GPIOR_91,TR0,TR0,3.0 V,3.0 V LVCMOS,output,no,,max2771,on-board,,Three-wire active-low chip select
+FPGA_CDONE,F8,CDONE,4A,4A_4B,1.8 V,1.8 V LVCMOS,output,no,,configuration,on-board,,Configuration status test point
+FPGA_CRESET_N,F9,CRESET_N,4A,4A_4B,1.8 V,1.8 V LVCMOS,input,no,DIFFERENTIAL_MEMBER,configuration,on-board,,"Open-drain fan-in of all-rail-valid, FTDI, and filtered external/manual reset requests"
+HARD_TCK,G10,TCK,BR4,BR3_BR4,3.3 V,3.3 V LVCMOS,input,no,,hard_jtag,on-board,,Dedicated hard TAP TCK; FT4232H interface 1 BDBUS0 through power-domain isolation
+HARD_TMS,G12,TMS,BR4,BR3_BR4,3.3 V,3.3 V LVCMOS,input,no,,hard_jtag,on-board,,Dedicated hard TAP TMS; FT4232H interface 1 BDBUS3 through power-domain isolation
+HARD_TDO,G13,TDO,BR4,BR3_BR4,3.3 V,3.3 V LVCMOS,output,no,,hard_jtag,on-board,,Dedicated hard TAP TDO; FT4232H interface 1 BDBUS2 through power-domain isolation
+MAX_SDATA,G16,GPIOR_89,TR0,TR0,3.0 V,3.0 V LVCMOS,bidirectional,no,,max2771,on-board,,Single bidirectional three-wire serial data; not split MOSI/MISO
+MAX_SHDN,G17,GPIOR_92,TR0,TR0,3.0 V,3.0 V LVCMOS,output,no,,max2771,on-board,,MAX2771 hardware shutdown control
+QSPI_IO2,G5,GPIOB_N_39_CDI2,4B,4A_4B,1.8 V,1.8 V LVCMOS,bidirectional,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,configuration,on-board,,SPI-active CDI2
+QSPI_SCLK,G6,GPIOB_P_39_CCK_PLLIN0,4B,4A_4B,1.8 V,1.8 V LVCMOS,output,no,PLL_INPUT;DIFFERENTIAL_MEMBER,configuration,on-board,,SPI-active CCK; official CCK_PLLIN0 pin
+HARD_TDI,G9,TDI,BR4,BR3_BR4,3.3 V,3.3 V LVCMOS,input,no,,hard_jtag,on-board,,Dedicated hard TAP TDI; FT4232H interface 1 BDBUS1 through power-domain isolation
+PMOD4_4,H18,GPIOT_N_56,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD4,4,PMOD 4 pin 4; HSIO pair 56 N
+QSPI_IO0,H4,GPIOB_N_40_CDI0,4B,4A_4B,1.8 V,1.8 V LVCMOS,bidirectional,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,configuration,on-board,,SPI-active CDI0
+QSPI_IO1,H5,GPIOB_P_40_CDI1_EXTFB,4B,4A_4B,1.8 V,1.8 V LVCMOS,bidirectional,no,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,configuration,on-board,,SPI-active CDI1
+PMOD4_3,J18,GPIOT_P_56,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD4,3,PMOD 4 pin 3; HSIO pair 56 P
+FPGA_TEST_N,J2,GPIOB_N_19_TEST_N_CLK6_N,4C,4C,1.8 V,1.8 V LVCMOS,input,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,configuration,on-board,,Mandatory external weak pull-up disables test mode during configuration
+FPGA_CSI,J5,GPIOB_N_43_CSI_CLK10_N,4B,4A_4B,1.8 V,1.8 V LVCMOS,input,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,configuration,on-board,,Mandatory external weak pull-up selects this FPGA throughout configuration
+UART0_RX,P17,GPIOL_84,TL5,TL1_TL5,3.3 V,3.3 V LVCMOS,input,no,,ft4232,on-board,,FT4232H channel C TXD to FPGA RX
+RISCV_TMS,P18,GPIOL_80_CLK29,TL5,TL1_TL5,3.3 V,3.3 V LVCMOS,input,yes,CLOCK_CAPABLE,secondary_jtag,on-board,,Clock-capable fabric pin; official development-kit assignment
+UART0_TX,R17,GPIOL_85_PLLIN1,TL5,TL1_TL5,3.3 V,3.3 V LVCMOS,output,no,PLL_INPUT,ft4232,on-board,,FPGA TX to FT4232H channel C RXD
+UART1_RX,R18,GPIOL_87_PLLIN1,TL5,TL1_TL5,3.3 V,3.3 V LVCMOS,input,no,PLL_INPUT,ft4232,on-board,,FT4232H channel D TXD to FPGA RX
+RISCV_TDO,T18,GPIOL_83,TL5,TL1_TL5,3.3 V,3.3 V LVCMOS,output,no,,secondary_jtag,on-board,,Official development-kit hardened RISC-V JTAG assignment
+UART1_TX,T19,GPIOL_86,TL5,TL1_TL5,3.3 V,3.3 V LVCMOS,output,no,,ft4232,on-board,,FPGA TX to FT4232H channel D RXD
+CLK_40M_FPGA,U17,GPIOL_79_CLK28,TL5,TL1_TL5,3.3 V,3.3 V LVCMOS,input,yes,CLOCK_CAPABLE,clock,on-board,,40 MHz oscillator branch on clock-capable pin
+FTDI_DBG_GPIO,U19,GPIOL_52_PLLIN1,TL1,TL1_TL5,3.3 V,3.3 V LVCMOS,bidirectional,no,PLL_INPUT,ft4232,on-board,,Channel D debug GPIO/test point; PLL-capable
+PMOD1_1,U6,GPIOL_24,BL2,BL2_BL3,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_3v3,JPMOD1,1,PMOD 1 pin 1; plain HVIO GPIO
+RISCV_TDI,V19,GPIOL_46,TL1,TL1_TL5,3.3 V,3.3 V LVCMOS,input,no,,secondary_jtag,on-board,,Official development-kit hardened RISC-V JTAG assignment
+PMOD2_1,V20,GPIOL_45,TL1,TL1_TL5,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_3v3,JPMOD2,1,PMOD 2 pin 1; plain HVIO GPIO
+PMOD1_2,V4,GPIOL_23,BL2,BL2_BL3,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_3v3,JPMOD1,2,PMOD 1 pin 2; plain HVIO GPIO
@@ -0,0 +1,228 @@
+ball,official_pin_name,package_bank,bank_class,selected_vccio,io_standard,clock_capability,special_function,status,signal,connector,connector_pin,note
+A11,GPIOR_93_PLLIN1,TR1,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,used,IMU_DRY_SYNC,on-board,,Murata multiplexed Data Ready output / SYNC input
+A12,GPIOR_95_CLK12,TR1,HVIO,3.3 V,3.3 V LVCMOS,yes,CLOCK_CAPABLE,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+A13,GPIOR_94,TR1,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD1_3,JPMOD1,3,PMOD 1 pin 3
+A14,GPIOT_N_55,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD4_2,JPMOD4,2,PMOD 4 pin 2; HSIO pair 55 N
+A16,GPIOT_P_53,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD3_7,JPMOD3,7,PMOD 3 pin 7; HSIO pair 53 P
+A17,GPIOT_N_53,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD3_8,JPMOD3,8,PMOD 3 pin 8; HSIO pair 53 N
+A18,GPIOT_P_57,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD4_7,JPMOD4,7,PMOD 4 pin 7; HSIO pair 57 P
+A19,GPIOT_N_57,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD4_8,JPMOD4,8,PMOD 4 pin 8; HSIO pair 57 N
+A2,GPIOB_P_30_CDI9_PLLIN0,4C,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+A21,GPIOT_N_33_CLK16_N,2C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+A22,GPIOT_N_26,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+A3,GPIOB_N_32,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+A4,GPIOB_P_32,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+A6,GPIOB_N_35,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+A7,GPIOB_N_38_SSL_N,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,QSPI_CS_N,on-board,,SPI-active SSL_N
+A8,GPIOR_170,BR3_BR4,HVIO,3.3 V,3.3 V LVCMOS,no,,used,IMU_SCK,on-board,,SafeSPI mode-0 clock
+A9,GPIOR_171,BR3_BR4,HVIO,3.3 V,3.3 V LVCMOS,no,,used,IMU_MOSI,on-board,,SafeSPI controller-to-sensor data
+B1,GPIOB_P_21,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B10,GPIOR_169,BR3_BR4,HVIO,3.3 V,3.3 V LVCMOS,no,,used,IMU_CS,on-board,,SafeSPI active-low chip select
+B11,GPIOR_143_CLK9,BR0,HVIO,3.0 V,3.0 V LVCMOS,yes,CLOCK_CAPABLE,used,MAX_CLKOUT,on-board,,Source-synchronous ADC capture clock on dedicated clock-capable input
+B12,GPIOR_96_CLK13,TR1,HVIO,3.3 V,3.3 V LVCMOS,yes,CLOCK_CAPABLE,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B14,GPIOT_P_55,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD4_1,JPMOD4,1,PMOD 4 pin 1; HSIO pair 55 P
+B15,GPIOT_P_62_PLLIN0,2E,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B16,GPIOT_N_62,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B17,GPIOT_N_52,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD3_4,JPMOD3,4,PMOD 3 pin 4; HSIO pair 52 N
+B19,GPIOT_N_54,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD3_10,JPMOD3,10,PMOD 3 pin 10; HSIO pair 54 N
+B2,GPIOB_N_30_CDI8,4C,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B20,GPIOT_N_51,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD3_2,JPMOD3,2,PMOD 3 pin 2; HSIO pair 51 N
+B21,GPIOT_P_33_CLK16_P,2C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B22,GPIOT_N_27,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B23,GPIOT_P_26,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B4,GPIOB_N_31,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B5,GPIOB_N_34,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B6,GPIOB_P_35,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B7,GPIOB_P_38_CDI3,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,used,QSPI_IO3,on-board,,SPI-active CDI3
+B9,GPIOR_168,BR3_BR4,HVIO,3.3 V,3.3 V LVCMOS,no,,used,IMU_MISO,on-board,,SafeSPI sensor-to-controller data
+C10,GPIOR_167,BR3_BR4,HVIO,3.3 V,3.3 V LVCMOS,no,,used,IMU_EXTRESN,on-board,,External active-low reset
+C12,GPIOR_99,TR1,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD1_7,JPMOD1,7,PMOD 1 pin 7
+C13,GPIOR_98,TR1,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD1_8,JPMOD1,8,PMOD 1 pin 8
+C14,GPIOR_97,TR1,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD1_9,JPMOD1,9,PMOD 1 pin 9
+C15,GPIOT_N_59,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+C17,GPIOT_P_52,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD3_3,JPMOD3,3,PMOD 3 pin 3; HSIO pair 52 P
+C18,GPIOT_N_60,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+C19,GPIOT_P_54,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD3_9,JPMOD3,9,PMOD 3 pin 9; HSIO pair 54 P
+C2,GPIOB_N_21,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+C20,GPIOT_P_51,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD3_1,JPMOD3,1,PMOD 3 pin 1; HSIO pair 51 P
+C22,GPIOT_P_27,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+C3,GPIOB_P_27,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+C4,GPIOB_P_31,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+C5,GPIOB_P_34,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+C7,GPIOB_N_41,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+C9,GPIOR_166,BR3_BR4,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD1_4,JPMOD1,4,PMOD 1 pin 4; plain HVIO GPIO
+D1,GPIOB_P_20_CLK7_P,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D10,GPIOR_144,BR0,HVIO,3.0 V,3.0 V LVCMOS,no,,used,MAX_I0,on-board,,ADC I bit 0
+D11,GPIOR_142_CLK8,BR0,HVIO,3.0 V,3.0 V LVCMOS,yes,CLOCK_CAPABLE,used,MAX_I1,on-board,,ADC I bit 1; clock-capable pad retained in same BR0 bank
+D12,GPIOR_100,TR1,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD1_10,JPMOD1,10,PMOD 1 pin 10
+D13,GPIOR_102,TR2,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD2_2,JPMOD2,2,PMOD 2 pin 2
+D15,GPIOT_P_59_PLLIN0,2E,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D16,GPIOT_P_58,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD4_9,JPMOD4,9,PMOD 4 pin 9; HSIO pair 58 P
+D17,GPIOT_N_58,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD4_10,JPMOD4,10,PMOD 4 pin 10; HSIO pair 58 N
+D18,GPIOT_P_60_EXTFB,2E,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D2,GPIOB_N_20_CLK7_N,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D20,GPIOT_N_36_CLK19_N,2C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D21,GPIOT_N_29,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D22,GPIOT_P_25,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D23,GPIOT_N_25,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D3,GPIOB_N_27,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D5,GPIOB_N_37_CDI4,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D6,GPIOB_P_37_CDI5,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D7,GPIOB_P_41,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D8,GPIOB_N_44_CLK11_N,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E1,GPIOB_P_18_CLK5_P,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E10,GPIOR_145_PLLIN1,BR0,HVIO,3.0 V,3.0 V LVCMOS,no,PLL_INPUT,used,MAX_Q0,on-board,,ADC Q bit 0; PLL-capable pad in same BR0 bank
+E11,GPIOR_140_PLLIN1,BR0,HVIO,3.0 V,3.0 V LVCMOS,no,PLL_INPUT,used,MAX_Q1,on-board,,ADC Q bit 1; PLL-capable pad in same BR0 bank
+E13,GPIOR_103,TR2,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD2_3,JPMOD2,3,PMOD 2 pin 3
+E14,GPIOR_104,TR2,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD2_4,JPMOD2,4,PMOD 2 pin 4
+E15,GPIOR_107,TR2,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD2_9,JPMOD2,9,PMOD 2 pin 9
+E16,GPIOR_105,TR2,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD2_7,JPMOD2,7,PMOD 2 pin 7
+E18,GPIOT_N_61,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E19,GPIOT_N_64_CLK15_N,2E,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E20,GPIOT_P_36_CLK19_P,2C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E21,GPIOT_P_29,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E23,GPIOT_N_23,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E3,GPIOB_P_24_CDI15,4C,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E4,GPIOB_N_36_CDI6,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E5,GPIOB_P_36_CDI7,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E6,GPIOB_N_42,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E8,GPIOB_P_44_CLK11_P,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E9,GPIOR_165_PLLIN1,BR3_BR4,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F1,GPIOB_N_18_CLK5_N,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F11,GPIOR_141,BR0,HVIO,3.0 V,3.0 V LVCMOS,no,,used,MAX_LD,on-board,,PLL lock status
+F12,GPIOR_101_PLLIN1,TR2,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,used,RISCV_TCK,on-board,,Fabric RISC-V JTAG clock moved off the plain-GPIO PMOD allocation
+F13,GPIOR_106,TR2,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD2_8,JPMOD2,8,PMOD 2 pin 8
+F14,GPIOR_108,TR2,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD2_10,JPMOD2,10,PMOD 2 pin 10
+F16,GPIOR_90,TR0,HVIO,3.0 V,3.0 V LVCMOS,no,,used,MAX_SCLK,on-board,,Three-wire serial clock
+F17,GPIOR_91,TR0,HVIO,3.0 V,3.0 V LVCMOS,no,,used,MAX_CSN,on-board,,Three-wire active-low chip select
+F18,GPIOT_P_61_EXTFB,2E,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F19,GPIOT_P_64_CLK15_P,2E,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F2,GPIOB_P_17_CLK4_P,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F21,GPIOT_P_35_CLK18_P,2C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F22,GPIOT_N_35_CLK18_N,2C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F23,GPIOT_P_23_PLLIN0,2C,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F3,GPIOB_N_24_CDI14,4C,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F4,GPIOB_N_33,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F6,GPIOB_P_42,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G1,GPIOB_P_23_CBSEL1,4C,HSIO,1.8 V,1.8 V LVCMOS,no,CONFIG_BOOT_SELECT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G15,GPIOR_88_PLLIN1,TR0,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G16,GPIOR_89,TR0,HVIO,3.0 V,3.0 V LVCMOS,no,,used,MAX_SDATA,on-board,,Single bidirectional three-wire serial data; not split MOSI/MISO
+G17,GPIOR_92,TR0,HVIO,3.0 V,3.0 V LVCMOS,no,,used,MAX_SHDN,on-board,,MAX2771 hardware shutdown control
+G19,GPIOT_N_63_CLK14_N,2E,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G2,GPIOB_N_17_CLK4_N,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G20,GPIOT_N_34_CLK17_N,2C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G21,GPIOT_P_28,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G22,GPIOT_N_28,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G4,GPIOB_P_33,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G5,GPIOB_N_39_CDI2,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,used,QSPI_IO2,on-board,,SPI-active CDI2
+G6,GPIOB_P_39_CCK_PLLIN0,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;DIFFERENTIAL_MEMBER,used,QSPI_SCLK,on-board,,SPI-active CCK; official CCK_PLLIN0 pin
+H18,GPIOT_N_56,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD4_4,JPMOD4,4,PMOD 4 pin 4; HSIO pair 56 N
+H19,GPIOT_P_63_CLK14_P,2E,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+H2,GPIOB_N_23_CBSEL0,4C,HSIO,1.8 V,1.8 V LVCMOS,no,CONFIG_BOOT_SELECT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+H20,GPIOT_P_34_CLK17_P,2C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+H22,GPIOT_P_24_EXTFB,2C,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+H23,GPIOT_N_24,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+H3,GPIOB_P_28,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+H4,GPIOB_N_40_CDI0,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,used,QSPI_IO0,on-board,,SPI-active CDI0
+H5,GPIOB_P_40_CDI1_EXTFB,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,used,QSPI_IO1,on-board,,SPI-active CDI1
+J1,GPIOB_P_19_NSTATUS_CLK6_P,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+J18,GPIOT_P_56,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD4_3,JPMOD4,3,PMOD 4 pin 3; HSIO pair 56 P
+J2,GPIOB_N_19_TEST_N_CLK6_N,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,used,FPGA_TEST_N,on-board,,Mandatory external weak pull-up disables test mode during configuration
+J20,GPIOT_P_17,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+J21,GPIOT_P_16,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+J22,GPIOT_P_10_CLK27_P,2B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+J23,GPIOT_N_10_CLK27_N,2B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+J3,GPIOB_N_28,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+J5,GPIOB_N_43_CSI_CLK10_N,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,used,FPGA_CSI,on-board,,Mandatory external weak pull-up selects this FPGA throughout configuration
+J6,GPIOB_P_43_CSO_CLK10_P,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K1,GPIOB_P_14_CDI19_CLK1_P,4D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K18,GPIOT_P_49_EXTFB,2D,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K19,GPIOT_N_49,2D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K20,GPIOT_N_17,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K21,GPIOT_N_16,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K23,GPIOT_P_21,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K3,GPIOB_P_29_CDI11_EXTFB,4C,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K4,GPIOB_N_29_CDI10,4C,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K5,GPIOB_P_26_EXTSPICLK,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;EXT_SPI;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K6,GPIOB_P_25_CDI13,4C,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L1,GPIOB_N_14_CDI18_CLK1_N,4D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L17,GPIOT_P_50_PLLIN0,2D,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L18,GPIOT_N_50,2D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L19,GPIOT_P_20,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L2,GPIOB_P_15_CDI17_CLK2_P,4D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L21,GPIOT_P_11_CLK30_P,2B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L22,GPIOT_N_11_CLK30_N,2B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L23,GPIOT_N_21,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L3,GPIOB_P_11,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L4,GPIOB_N_26_SSU_N,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L6,GPIOB_N_25_CDI12,4C,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M1,GPIOB_P_09,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M16,GPIOT_P_43,2D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M17,GPIOT_N_43,2D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M19,GPIOT_N_20,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M2,GPIOB_N_15_CDI16_CLK2_N,4D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M20,GPIOT_P_13_PLLIN0,2B,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M21,GPIOT_P_22,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M22,GPIOT_N_22,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M4,GPIOB_N_11,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M5,GPIOB_P_22,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M6,GPIOB_N_22,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N17,GPIOT_P_40_CLK23_P,2D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N18,GPIOT_N_40_CLK23_N,2D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N19,GPIOT_P_14_EXTFB,2B,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N2,GPIOB_N_09,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N20,GPIOT_N_13,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N22,GPIOT_P_15,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N23,GPIOT_N_15,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N3,GPIOB_P_13_CDI21_CLK0_P,4D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N4,GPIOB_N_12,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N5,GPIOB_P_12,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N7,GPIOB_P_08_CDI22_EXTFB,4D,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P1,GPIOB_N_16_CLK3_N,4D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P17,GPIOL_84,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,no,,used,UART0_RX,on-board,,FT4232H channel C TXD to FPGA RX
+P18,GPIOL_80_CLK29,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,yes,CLOCK_CAPABLE,used,RISCV_TMS,on-board,,Clock-capable fabric pin; official development-kit assignment
+P2,GPIOB_P_16_CLK3_P,4D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P20,GPIOT_N_14,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P21,GPIOT_P_18,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P22,GPIOT_N_18,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P23,GPIOT_P_09_CLK26_P,2B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P3,GPIOB_N_13_CDI20_CLK0_N,4D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P5,GPIOB_P_06_CDI26_EXTFB,4D,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P6,GPIOB_P_05_CDI28_PLLIN0,4D,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P7,GPIOB_N_08,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R1,GPIOB_P_04_CDI30_EXTFB,4D,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R17,GPIOL_85_PLLIN1,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,used,UART0_TX,on-board,,FPGA TX to FT4232H channel C RXD
+R18,GPIOL_87_PLLIN1,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,used,UART1_RX,on-board,,FT4232H channel D TXD to FPGA RX
+R19,GPIOT_P_19,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R20,GPIOT_N_19,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R21,GPIOT_P_12_CLK31_P,2B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R23,GPIOT_N_09_CLK26_N,2B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R3,GPIOB_N_07_CDI23,4D,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R4,GPIOB_P_07_CDI24_PLLIN0,4D,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R5,GPIOB_N_06_CDI25,4D,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R6,GPIOB_N_05_CDI27,4D,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+T1,GPIOB_N_04_CDI29,4D,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+T18,GPIOL_83,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,no,,used,RISCV_TDO,on-board,,Official development-kit hardened RISC-V JTAG assignment
+T19,GPIOL_86,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,no,,used,UART1_TX,on-board,,FPGA TX to FT4232H channel D RXD
+T2,GPIOB_N_10,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+T21,GPIOT_N_12_CLK31_N,2B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+T22,GPIOT_P_08_PLLIN0,2A,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+T23,GPIOT_N_08,2A,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+T3,GPIOB_P_10,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+T4,GPIOL_27_CLK25,BL2_BL3,HVIO,3.3 V,3.3 V LVCMOS,yes,CLOCK_CAPABLE,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+U1,GPIOB_N_03_CDI31,4D,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+U17,GPIOL_79_CLK28,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,yes,CLOCK_CAPABLE,used,CLK_40M_FPGA,on-board,,40 MHz oscillator branch on clock-capable pin
+U19,GPIOL_52_PLLIN1,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,used,FTDI_DBG_GPIO,on-board,,Channel D debug GPIO/test point; PLL-capable
+U2,GPIOB_P_03_PLLIN0,4D,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+U21,GPIOT_P_05,2A,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+U22,GPIOT_N_05,2A,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+U4,GPIOL_25_PLLIN1,BL2_BL3,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+U5,GPIOL_34_PLLIN1,BL2_BL3,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+U6,GPIOL_24,BL2_BL3,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD1_1,JPMOD1,1,PMOD 1 pin 1; plain HVIO GPIO
+V19,GPIOL_46,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,no,,used,RISCV_TDI,on-board,,Official development-kit hardened RISC-V JTAG assignment
+V2,GPIOL_26_CLK24,BL2_BL3,HVIO,3.3 V,3.3 V LVCMOS,yes,CLOCK_CAPABLE,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+V20,GPIOL_45,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD2_1,JPMOD2,1,PMOD 2 pin 1; plain HVIO GPIO
+V22,GPIOT_P_07_EXTFB,2A,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+V23,GPIOT_N_07,2A,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+V3,GPIOL_32_PLLIN1,BL2_BL3,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+V4,GPIOL_23,BL2_BL3,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD1_2,JPMOD1,2,PMOD 1 pin 2; plain HVIO GPIO