Initial Ti375 GNSS IMU board design and documentation

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# Donanım mimarisi
## Ana dosyalar
- `board.kicad_sch`: güncel hiyerarşik KiCad 10 şeması.
- `board.kicad_pcb`: güncel, placed fakat unrouted PCB.
- `board.kicad_pro`: net-class, diff-pair ve proje ayarları.
- `board.kicad_dru`: üreticiye ve kontrollü empedansa özgü DRC kuralları.
- `board.kicad_sym` ve `board.pretty/`: projeye özel sembol ve footprintler.
`board_prerouted`, `board_plane_stitched` ve eski `board_power_routed` dosyaları
ara çalışma ürünleridir. Güncel reset/netlist revizyonundan önce oluşturulmuş
routing dosyaları yeni tasarım için kaynak kabul edilmez.
## Güç mimarisi
1. USB-C VBUS veya harici 5 V koruma ve power-path devresinden sonra `SYS5`
rayını oluşturur.
2. TPS6287B15, FPGA core/VCCA/VDD_SOC için 0.95 V üretir.
3. `CORE_PG`, LM3880 sıralayıcıyı başlatır.
4. LM3880 önce TPS62867 1.8 V rayını, ardından TPS62867 3.3 V rayını etkinleştirir.
5. 3.3 V üzerinden MAX2771 ve ilgili FPGA bankları için ayrı düşük gürültülü
3.0 V LDO'lar beslenir.
6. TPS3808, `VCC3V0_DIG` rayını izler ve geçerli olduktan sonra 20 ms gecikmeyle
power-good verir.
7. Core PG, 1.8 V PG, 3.3 V PG, TPS3808 sonucu ve LM3880 FLAG3,
`ALL_FPGA_POWER_OK` mantığında birlikte doğrulanır.
FPGA besleme rayları:
| Ray | Görev |
|---|---|
| `VCC0V95` | FPGA core, VCCA ve SoC çekirdeği |
| `VCC1V8` | VCCAUX, konfigürasyon/flash ve 1.8 V HSIO bankları |
| `VCC3V3` | 3.3 V FPGA I/O bankları ve çevre birimleri |
| `VCC3V0_DIG` | MAX2771 dijital ve ilgili 3.0 V FPGA bankı |
| `VCC3V0_RF` | MAX2771 analog RF beslemesi |
| `VCC3V0_CLK` | Düşük gürültülü saat beslemesi |
| `VCC3V3_AUX` | Her zaman açık supervisor ve USB debug mantığı |
## Reset mimarisi
`FPGA_CRESET_N`, 1.8 V'a pull-up edilen aktif-düşük konfigürasyon resetidir.
Aşağıdaki üç bağımsız SN74LVC1G07 açık-drenç yolu bu hattı yalnızca aşağı
çekebilir:
- FT4232H interface 1 `BDBUS4` yazılım reset isteği.
- `ALL_FPGA_POWER_OK` geçersiz olduğunda power-fault reseti.
- Filtrelenmiş kart üstü buton veya `J4 EXT RESET_N` harici reset isteği.
`J4` harici kaynağı aktif-düşük open-drain/contact-closure kullanımına göre
tasarlanmıştır. Harici pine gerilim uygulanmamalı; pin GND'ye çekilmelidir.
## JTAG ve USB debug
| FT4232H arayüzü | Görev | Sinyaller |
|---|---|---|
| Interface 0 / A | RISC-V JTAG | ADBUS0..3 |
| Interface 1 / B | FPGA hard JTAG | BDBUS0..3 |
| Interface 1 / BDBUS4 | FPGA reset | Aktif-düşük reset isteği |
| Interface 2 / C | UART0 | TX/RX |
| Interface 3 / D | UART1 ve debug GPIO | TX/RX/DBG |
FTDI her zaman açık yardımcı raydan beslenir. FPGA'ya doğru sürülen sinyaller
FPGA 3.3 V rayından beslenen Ioff özellikli bufferlardan geçer. Bu bufferların
enable girişi yalnızca `ALL_FPGA_POWER_OK` geçerliyken açılır; kapalı FPGA I/O
pinlerinin debug arayüzü üzerinden back-power edilmesi engellenir.
Hard JTAG TCK/TMS/TDI/TDO ve RISC-V JTAG sinyallerinde 10 kohm idle pull-up,
seri hatlarda 33 ohm kaynak sönümleme dirençleri bulunur. Ayrı ARM/JTAG headerı
yoktur.
## PMOD ve FPGA pin politikası
- `JPMOD1`, `JPMOD2`: Digilent 2x6, 3.3 V.
- `JPMOD3`, `JPMOD4`: Digilent 2x6, 1.8 V.
- Her PMOD'da 8 GPIO, 2 GND ve 2 besleme pini vardır.
- Konfigürasyon, PLL feedback, özel clock ve kartta kullanılan MAX2771/IMU
pinleri PMOD tahsisine dahil edilmez.
- Kesin ball/net eşlemesi `../docs/ti375_pinout.csv` dosyasındadır.
## RF ve yüksek hızlı routing kuralları
- RF katı üst katmanda, JLC08161H-3313 stackup için 0.164 mm genişlik ve
0.200 mm coplanar GND aralığıyla 50 ohm CPWG olarak tasarlanır.
- SMA, ESD, bias-tee, SAW ve MAX2771 MIXIN_HI arasındaki RF güzergâhında dijital
route veya via kullanılmaz.
- USB2 diferansiyel çift 0.135 mm hat ve 0.150 mm coupled gap kuralındadır.
- RF ve USB geometrisi `scripts/finalize_routing.py` tarafından deterministik
olarak kurulur; Freerouter çıktısındaki kritik hatlar kullanılmaz.
- L2 ve L7 kesintisiz GND referans katmanlarıdır. L4 bölünmüş DC güç katmanıdır.
## Üretime çıkış şartı
Bu revizyonda placement kontrolleri geçmiştir fakat `board.kicad_pcb` üzerinde
track yoktur. Üretim öncesinde routing akışı tamamlanmalı; zone'lar doldurulmalı;
ERC, DRC, schematic parity, Gerber ve drill incelemesi tekrar yapılmalıdır.
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(version 1)
# The edge-launch SMA copper must reach the routed board edge by construction.
(rule "J2 edge-launch lands"
(condition "A.Reference == 'J2' || B.Reference == 'J2'")
(constraint edge_clearance (min -0.01mm)))
# The manufacturer USB-C locating holes are 0.194 mm from grounded shell
# lands. This exception is internal to the qualified connector footprint.
(rule "USB-C locating-hole clearance"
(condition "A.Reference == 'J1' && B.Reference == 'J1'")
(constraint hole_clearance (min 0.19mm)))
# RZV0024A is an ultra-dense high-current package. Its adjusted corner lands
# and thermal zones meet the selected JLCPCB 0.10-mm copper rule.
(rule "TPS6287B RZV internal clearance"
(condition "A.Reference == 'U13' && B.Reference == 'U13'")
(constraint clearance (min 0.10mm)))
# A 0.45-mm dogbone via at the centre of four 0.8-mm-pitch BGA lands has
# 0.1407-mm geometric clearance. This local rule is still well above the
# selected fabricator's 0.10-mm copper minimum; clocks retain 0.15 mm outside
# the U1 escape field.
(rule "Ti375 0.8-mm BGA dogbone clearance"
(condition "A.Reference == 'U1' || B.Reference == 'U1'")
(constraint clearance (min 0.14mm)))
# JLC08161H-3313 L1/L2 geometry. Net-class widths are routing defaults only;
# these rules make the controlled-impedance geometries actual DRC limits.
(rule "GNSS 50-ohm CPWG geometry"
(condition "A.NetClass == 'RF50_CPWG'")
(constraint track_width (min 0.164mm) (opt 0.164mm) (max 0.164mm)))
(rule "GNSS RF stays on top layer"
(condition "A.NetClass == 'RF50_CPWG' && A.Type == 'Track' && A.Layer != 'F.Cu'")
(constraint disallow track))
(rule "USB2 90-ohm differential geometry"
(condition "A.NetClass == 'USB90_DIFF'")
(constraint track_width (min 0.135mm) (opt 0.135mm) (max 0.135mm)))
(rule "USB2 coupled gap"
(condition "A.NetClass == 'USB90_DIFF' && AB.isCoupledDiffPair()")
(constraint diff_pair_gap (min 0.15mm) (opt 0.15mm) (max 0.15mm)))
(rule "Clock trunk width outside Ti375 escape"
(condition "A.NetClass == 'CLOCK' && A.Type == 'Track' && !A.insideCourtyard('U1')")
(constraint track_width (min 0.15mm)))
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{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"apply_defaults_to_fp_barcodes": false,
"apply_defaults_to_fp_dimensions": false,
"apply_defaults_to_fp_fields": false,
"apply_defaults_to_fp_shapes": false,
"apply_defaults_to_fp_text": false,
"board_outline_line_width": 0.05,
"copper_line_width": 0.2,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.05,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": true,
"text_position": 0,
"units_format": 0
},
"fab_line_width": 0.1,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.1,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.8,
"height": 1.27,
"width": 1.27
},
"silk_line_width": 0.1,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.1,
"silk_text_upright": false,
"zones": {
"border_display_style": 2,
"border_hatch_pitch": 0.5,
"corner_radius": 0.0,
"corner_smoothing": 0,
"fill_mode": 0,
"hatch_gap": 1.5,
"hatch_orientation": 0.0,
"hatch_smoothing_level": 0,
"hatch_smoothing_value": 0.1,
"hatch_thickness": 1.0,
"min_clearance": 0.5,
"min_island_area": 10.0,
"min_thickness": 0.25,
"pad_connection": 1,
"remove_islands": 0,
"thermal_relief_gap": 0.5,
"thermal_relief_spoke_width": 0.5
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"creepage": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_filters_mismatch": "ignore",
"footprint_symbol_field_mismatch": "warning",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_to_hole": "warning",
"holes_co_located": "warning",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"mirrored_text_on_front_layer": "warning",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"missing_tuning_profile": "warning",
"net_conflict": "warning",
"nonmirrored_text_on_back_layer": "warning",
"npth_inside_courtyard": "error",
"padstack": "warning",
"pth_inside_courtyard": "error",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_on_edge_cuts": "error",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_angle": "error",
"track_dangling": "warning",
"track_not_centered_on_via": "ignore",
"track_on_post_machined_layer": "error",
"track_segment_length": "error",
"track_width": "error",
"tracks_crossing": "error",
"tuning_profile_track_geometries": "ignore",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.1,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.25,
"min_groove_width": 0.0,
"min_hole_clearance": 0.19,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.225,
"min_track_width": 0.1,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.45,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_onpthpad": true,
"td_onroundshapesonly": false,
"td_onsmdpad": true,
"td_ontrackend": false,
"td_onvia": true
}
],
"teardrop_parameters": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 1.0
},
"diff_pair_skew_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
},
"single_track_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
}
},
"via_dimensions": [],
"zones_allow_external_fillets": false
},
"ipc2581": {
"bom_rev": "",
"dist": "",
"distpn": "",
"internal_id": "",
"mfg": "",
"mpn": "",
"sch_revision": ""
},
"layer_pairs": [],
"layer_presets": [],
"viewports": []
},
"boards": [],
"component_class_settings": {
"assignments": [],
"meta": {
"version": 0
},
"sheet_component_classes": {
"enabled": false
}
},
"cvpcb": {
"equivalence_files": []
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "board.kicad_pro",
"version": 3
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.15,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.135,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 2147483647,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.12,
"tuning_profile": "",
"via_diameter": 0.45,
"via_drill": 0.225,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "BGA_ESCAPE",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": -1,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"tuning_profile": "",
"via_diameter": 0.45,
"via_drill": 0.225,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "CLOCK",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": -1,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"tuning_profile": "",
"via_diameter": 0.45,
"via_drill": 0.225,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "POWER",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": -1,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.4,
"tuning_profile": "",
"via_diameter": 0.45,
"via_drill": 0.225,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "RF50_CPWG",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": -1,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.164,
"tuning_profile": "",
"via_diameter": 0.45,
"via_drill": 0.225,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.15,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.135,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "USB90_DIFF",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": -1,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.135,
"tuning_profile": "",
"via_diameter": 0.45,
"via_drill": 0.225,
"wire_width": 6
}
],
"meta": {
"version": 5
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "RF50_CPWG",
"pattern": "RF_SMA"
},
{
"netclass": "RF50_CPWG",
"pattern": "RF_PRE_SAW"
},
{
"netclass": "RF50_CPWG",
"pattern": "RF_POST_SAW"
},
{
"netclass": "RF50_CPWG",
"pattern": "MAX_MIXIN_HI"
},
{
"netclass": "USB90_DIFF",
"pattern": "USB_D_P"
},
{
"netclass": "USB90_DIFF",
"pattern": "USB_D_N"
},
{
"netclass": "USB90_DIFF",
"pattern": "FTDI_D_P"
},
{
"netclass": "USB90_DIFF",
"pattern": "FTDI_D_N"
},
{
"netclass": "CLOCK",
"pattern": "MAX_CLKOUT*"
},
{
"netclass": "CLOCK",
"pattern": "MAX_SCLK*"
},
{
"netclass": "CLOCK",
"pattern": "MAX_ADC_CLKIN"
},
{
"netclass": "CLOCK",
"pattern": "QSPI_SCLK"
},
{
"netclass": "CLOCK",
"pattern": "CLK_40M_FPGA"
},
{
"netclass": "CLOCK",
"pattern": "OSC40_OUT"
},
{
"netclass": "CLOCK",
"pattern": "TCXO16_OUT"
},
{
"netclass": "CLOCK",
"pattern": "FTDI_OSC12"
},
{
"netclass": "CLOCK",
"pattern": "FTDI_OSCI"
},
{
"netclass": "CLOCK",
"pattern": "IMU_SCK*"
},
{
"netclass": "CLOCK",
"pattern": "*TCK*"
},
{
"netclass": "POWER",
"pattern": "VCC*"
},
{
"netclass": "POWER",
"pattern": "SYS5"
},
{
"netclass": "POWER",
"pattern": "VBUS_RAW"
},
{
"netclass": "POWER",
"pattern": "USB5_PROT"
},
{
"netclass": "POWER",
"pattern": "EXT5_*"
},
{
"netclass": "POWER",
"pattern": "GND"
},
{
"netclass": "POWER",
"pattern": "CORE_SW"
},
{
"netclass": "POWER",
"pattern": "BUCK1V8_SW"
},
{
"netclass": "POWER",
"pattern": "BUCK3V3_SW"
},
{
"netclass": "POWER",
"pattern": "ANT_BIAS_SEL"
},
{
"netclass": "POWER",
"pattern": "ANT_BIAS_SW"
},
{
"netclass": "POWER",
"pattern": "FTDI_1V8"
},
{
"netclass": "POWER",
"pattern": "FTDI_VPHY"
},
{
"netclass": "POWER",
"pattern": "FTDI_VPLL"
},
{
"netclass": "POWER",
"pattern": "IMU_3V3"
},
{
"netclass": "POWER",
"pattern": "IMU_VREGA2"
},
{
"netclass": "POWER",
"pattern": "IMU_VREGD"
},
{
"netclass": "POWER",
"pattern": "USB_SHIELD"
},
{
"netclass": "BGA_ESCAPE",
"pattern": "EXP_*"
},
{
"netclass": "BGA_ESCAPE",
"pattern": "PMOD*"
}
]
},
"pcbnew": {
"last_paths": {
"idf": "",
"netlist": "",
"plot": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"bus_aliases": {},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"top_level_sheets": []
},
"sheets": [],
"text_variables": {},
"tuning_profiles": {
"meta": {
"version": 0
},
"tuning_profiles_impedance_geometric": []
}
}
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,31 @@
(footprint "Amphenol_20021121_00010C4LF"
(version 20240108)
(generator "board-footprints")
(layer "F.Cu")
(descr "Amphenol Minitek127 20021121-00010C4LF vertical SMT 2x5")
(attr smd)
(property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15))))
(property "Value" "" (at 0 5 0) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15))))
(fp_rect (start -3.5 -2.3) (end 3.5 2.3)
(stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
(fp_rect (start -3.7 -3) (end 3.7 3)
(stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
(fp_line (start -3.5 -2.35) (end 3.5 -2.35) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 3.5 -2.35) (end 3.5 2.35) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 3.5 2.35) (end -3.5 2.35) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start -3.5 2.35) (end -3.5 -2.35) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_circle (center -3.8 2.3) (end -3.55 2.3) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
(pad "1" smd roundrect (at -2.54 1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "2" smd roundrect (at -2.54 -1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "3" smd roundrect (at -1.27 1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "4" smd roundrect (at -1.27 -1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "5" smd roundrect (at 0 1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "6" smd roundrect (at 0 -1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "7" smd roundrect (at 1.27 1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "8" smd roundrect (at 1.27 -1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "9" smd roundrect (at 2.54 1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "10" smd roundrect (at 2.54 -1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(embedded_fonts no)
)
@@ -0,0 +1,23 @@
(footprint "Coilcraft_XEL4030"
(version 20240108)
(generator "board-footprints")
(layer "F.Cu")
(descr "Coilcraft XEL4030 recommended land, March 2026")
(attr smd)
(property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15))))
(property "Value" "" (at 0 5 0) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15))))
(fp_rect (start -2 -2) (end 2 2)
(stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
(fp_rect (start -2.5 -2.4) (end 2.5 2.4)
(stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
(fp_line (start -2.075 -2.075) (end 2.075 -2.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 2.075 -2.075) (end 2.075 2.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 2.075 2.075) (end -2.075 2.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start -2.075 2.075) (end -2.075 -2.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_circle (center -2.2 -2) (end -1.95 -2) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
(pad "1" smd roundrect (at -1.675 0) (size 0.98 3.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "2" smd roundrect (at 1.675 0) (size 0.98 3.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(embedded_fonts no)
)
@@ -0,0 +1,30 @@
(footprint "Digilent_PMOD_2x6_P2.54mm"
(version 20240108)
(generator "board-footprints")
(layer "F.Cu")
(descr "Digilent PMOD 2x6, 2.54-mm pitch, row-wise pins 1-6 and 7-12")
(attr through_hole)
(property "Reference" "REF**" (at 6.35 -2.5 0) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15))))
(property "Value" "" (at 6.35 5 0) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15))))
(fp_rect (start -1.27 -1.27) (end 13.97 3.81)
(stroke (width 0.15) (type default)) (fill none) (layer "F.SilkS"))
(fp_rect (start -1.5 -1.5) (end 14.2 4.04)
(stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
(fp_circle (center -0.8 -0.8) (end -0.5 -0.8)
(stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
(pad "1" thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
(pad "2" thru_hole circle (at 2.54 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
(pad "3" thru_hole circle (at 5.08 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
(pad "4" thru_hole circle (at 7.62 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
(pad "5" thru_hole circle (at 10.16 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
(pad "6" thru_hole circle (at 12.7 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
(pad "7" thru_hole circle (at 0 2.54) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
(pad "8" thru_hole circle (at 2.54 2.54) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
(pad "9" thru_hole circle (at 5.08 2.54) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
(pad "10" thru_hole circle (at 7.62 2.54) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
(pad "11" thru_hole circle (at 10.16 2.54) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
(pad "12" thru_hole circle (at 12.7 2.54) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
(embedded_fonts no)
)
@@ -0,0 +1,25 @@
(footprint "Epson_TG2016SMN"
(version 20240108)
(generator "board-footprints")
(layer "F.Cu")
(descr "Epson TG2016SMN official 2.0 x 1.6 mm land")
(attr smd)
(property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15))))
(property "Value" "" (at 0 5 0) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15))))
(fp_rect (start -1 -0.8) (end 1 0.8)
(stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
(fp_rect (start -1.5 -1.3) (end 1.5 1.3)
(stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
(fp_line (start -1.075 -0.875) (end 1.075 -0.875) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 1.075 -0.875) (end 1.075 0.875) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 1.075 0.875) (end -1.075 0.875) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start -1.075 0.875) (end -1.075 -0.875) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_circle (center -1.35 -0.85) (end -1.1 -0.85) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
(pad "1" smd roundrect (at -0.825 -0.565) (size 0.6 0.75) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "2" smd roundrect (at -0.825 0.565) (size 0.6 0.75) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "3" smd roundrect (at 0.825 0.565) (size 0.6 0.75) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "4" smd roundrect (at 0.825 -0.565) (size 0.6 0.75) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(embedded_fonts no)
)
@@ -0,0 +1,94 @@
(footprint "FTDI_VQFN56_EP5p9"
(version 20240108)
(generator "board-footprints")
(layer "F.Cu")
(descr "FTDI FT4232H-56Q VQFN56 land from TN_166; 5.9-mm EP")
(attr smd)
(property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15))))
(property "Value" "" (at 0 5 0) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15))))
(fp_rect (start -4 -4) (end 4 4)
(stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
(fp_rect (start -4.6 -4.6) (end 4.6 4.6)
(stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
(fp_line (start -4.075 -4.075) (end 4.075 -4.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 4.075 -4.075) (end 4.075 4.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 4.075 4.075) (end -4.075 4.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start -4.075 4.075) (end -4.075 -4.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_circle (center -4.4 -3.85) (end -4.15 -3.85) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
(pad "1" smd roundrect (at -4 -3.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "2" smd roundrect (at -4 -2.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "3" smd roundrect (at -4 -2.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "4" smd roundrect (at -4 -1.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "5" smd roundrect (at -4 -1.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "6" smd roundrect (at -4 -0.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "7" smd roundrect (at -4 -0.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "8" smd roundrect (at -4 0.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "9" smd roundrect (at -4 0.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "10" smd roundrect (at -4 1.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "11" smd roundrect (at -4 1.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "12" smd roundrect (at -4 2.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "13" smd roundrect (at -4 2.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "14" smd roundrect (at -4 3.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "15" smd roundrect (at -3.25 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "16" smd roundrect (at -2.75 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "17" smd roundrect (at -2.25 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "18" smd roundrect (at -1.75 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "19" smd roundrect (at -1.25 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "20" smd roundrect (at -0.75 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "21" smd roundrect (at -0.25 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "22" smd roundrect (at 0.25 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "23" smd roundrect (at 0.75 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "24" smd roundrect (at 1.25 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "25" smd roundrect (at 1.75 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "26" smd roundrect (at 2.25 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "27" smd roundrect (at 2.75 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "28" smd roundrect (at 3.25 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "29" smd roundrect (at 4 3.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "30" smd roundrect (at 4 2.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "31" smd roundrect (at 4 2.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "32" smd roundrect (at 4 1.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "33" smd roundrect (at 4 1.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "34" smd roundrect (at 4 0.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "35" smd roundrect (at 4 0.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "36" smd roundrect (at 4 -0.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "37" smd roundrect (at 4 -0.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "38" smd roundrect (at 4 -1.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "39" smd roundrect (at 4 -1.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "40" smd roundrect (at 4 -2.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "41" smd roundrect (at 4 -2.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "42" smd roundrect (at 4 -3.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "43" smd roundrect (at 3.25 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "44" smd roundrect (at 2.75 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "45" smd roundrect (at 2.25 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "46" smd roundrect (at 1.75 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "47" smd roundrect (at 1.25 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "48" smd roundrect (at 0.75 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "49" smd roundrect (at 0.25 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "50" smd roundrect (at -0.25 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "51" smd roundrect (at -0.75 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "52" smd roundrect (at -1.25 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "53" smd roundrect (at -1.75 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "54" smd roundrect (at -2.25 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "55" smd roundrect (at -2.75 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "56" smd roundrect (at -3.25 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "57" smd rect (at 0 0) (size 5.9 5.9) (layers "F.Cu" "F.Mask"))
(pad "" smd roundrect (at -2.22 -2.22) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "" smd roundrect (at -2.22 -0.74) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "" smd roundrect (at -2.22 0.74) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "" smd roundrect (at -2.22 2.22) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "" smd roundrect (at -0.74 -2.22) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "" smd roundrect (at -0.74 -0.74) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "" smd roundrect (at -0.74 0.74) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "" smd roundrect (at -0.74 2.22) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "" smd roundrect (at 0.74 -2.22) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "" smd roundrect (at 0.74 -0.74) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "" smd roundrect (at 0.74 0.74) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "" smd roundrect (at 0.74 2.22) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "" smd roundrect (at 2.22 -2.22) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "" smd roundrect (at 2.22 -0.74) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "" smd roundrect (at 2.22 0.74) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "" smd roundrect (at 2.22 2.22) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
(embedded_fonts no)
)
@@ -0,0 +1,23 @@
(footprint "Kyocera_600L_0402"
(version 20240108)
(generator "board-footprints")
(layer "F.Cu")
(descr "KYOCERA AVX 600L 0402 recommended land")
(attr smd)
(property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15))))
(property "Value" "" (at 0 5 0) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15))))
(fp_rect (start -0.5 -0.25) (end 0.5 0.25)
(stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
(fp_rect (start -1.1 -0.6) (end 1.1 0.6)
(stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
(fp_line (start -0.575 -0.325) (end 0.575 -0.325) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 0.575 -0.325) (end 0.575 0.325) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 0.575 0.325) (end -0.575 0.325) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start -0.575 0.325) (end -0.575 -0.325) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_circle (center -0.7 -0.25) (end -0.45 -0.25) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
(pad "1" smd roundrect (at -0.65 0) (size 0.9 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "2" smd roundrect (at 0.65 0) (size 0.9 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(embedded_fonts no)
)
@@ -0,0 +1,26 @@
(footprint "Kyocera_SF14_5pad"
(version 20240108)
(generator "board-footprints")
(layer "F.Cu")
(descr "KYOCERA SF14-1582M5UUS2 SAW; official five-pad land")
(attr smd)
(property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15))))
(property "Value" "" (at 0 5 0) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15))))
(fp_rect (start -0.55 -0.45) (end 0.55 0.45)
(stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
(fp_rect (start -0.9 -0.75) (end 0.9 0.75)
(stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
(fp_line (start -0.6 -0.5) (end 0.6 -0.5) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 0.6 -0.5) (end 0.6 0.5) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 0.6 0.5) (end -0.6 0.5) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start -0.6 0.5) (end -0.6 -0.5) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_circle (center -0.8 0) (end -0.55 0) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
(pad "1" smd roundrect (at -0.5 0) (size 0.25 0.325) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "2" smd roundrect (at 0 0.2875) (size 0.25 0.325) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "3" smd roundrect (at 0.5 0.2875) (size 0.25 0.325) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "4" smd roundrect (at 0.5 -0.2875) (size 0.25 0.325) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "5" smd roundrect (at 0 -0.2875) (size 0.25 0.325) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(embedded_fonts no)
)
@@ -0,0 +1,23 @@
(footprint "Murata_DFE201612E"
(version 20240108)
(generator "board-footprints")
(layer "F.Cu")
(descr "Murata DFE201612E recommended land J(E)TE243A-0006")
(attr smd)
(property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15))))
(property "Value" "" (at 0 5 0) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15))))
(fp_rect (start -1 -0.8) (end 1 0.8)
(stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
(fp_rect (start -1.4 -1.2) (end 1.4 1.2)
(stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
(fp_line (start -1.075 -0.875) (end 1.075 -0.875) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 1.075 -0.875) (end 1.075 0.875) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 1.075 0.875) (end -1.075 0.875) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start -1.075 0.875) (end -1.075 -0.875) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_circle (center -1.2 -0.8) (end -0.95 -0.8) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
(pad "1" smd roundrect (at -0.8 0) (size 0.8 1.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "2" smd roundrect (at 0.8 0) (size 0.8 1.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(embedded_fonts no)
)
@@ -0,0 +1,47 @@
(footprint "Murata_SCH16T_K01"
(version 20240108)
(generator "board-footprints")
(layer "F.Cu")
(descr "Murata SCH16T-K01-1 official PCB land pattern")
(attr smd)
(property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15))))
(property "Value" "" (at 0 5 0) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15))))
(fp_rect (start -6.7 -5.9) (end 6.7 5.9)
(stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
(fp_rect (start -7.6 -6.4) (end 7.6 6.4)
(stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
(fp_line (start -6.775 -5.975) (end 6.775 -5.975) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 6.775 -5.975) (end 6.775 5.975) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 6.775 5.975) (end -6.775 5.975) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start -6.775 5.975) (end -6.775 -5.975) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_circle (center -7.15 -5.45) (end -6.9 -5.45) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
(pad "1" smd roundrect (at -6.165 -4.4) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "2" smd roundrect (at -6.165 -3.6) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "3" smd roundrect (at -6.165 -2.8) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "4" smd roundrect (at -6.165 -2) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "5" smd roundrect (at -6.165 -1.2) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "6" smd roundrect (at -6.165 -0.4) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "7" smd roundrect (at -6.165 0.4) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "8" smd roundrect (at -6.165 1.2) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "9" smd roundrect (at -6.165 2) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "10" smd roundrect (at -6.165 2.8) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "11" smd roundrect (at -6.165 3.6) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "12" smd roundrect (at -6.165 4.4) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "24" smd roundrect (at 6.165 -4.4) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "23" smd roundrect (at 6.165 -3.6) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "22" smd roundrect (at 6.165 -2.8) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "21" smd roundrect (at 6.165 -2) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "20" smd roundrect (at 6.165 -1.2) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "19" smd roundrect (at 6.165 -0.4) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "18" smd roundrect (at 6.165 0.4) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "17" smd roundrect (at 6.165 1.2) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "16" smd roundrect (at 6.165 2) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "15" smd roundrect (at 6.165 2.8) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "14" smd roundrect (at 6.165 3.6) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "13" smd roundrect (at 6.165 4.4) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(fp_text user "X+ ->" (at 0 -2) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.14))))
(fp_text user "Y+ ^" (at 0 0) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.14))))
(embedded_fonts no)
)
@@ -0,0 +1,23 @@
(footprint "Texas_DPY0002A_X1SON"
(version 20240108)
(generator "board-footprints")
(layer "F.Cu")
(descr "TI DPY0002A X1SON; ESD501 official land")
(attr smd)
(property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15))))
(property "Value" "" (at 0 5 0) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15))))
(fp_rect (start -0.5 -0.3) (end 0.5 0.3)
(stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
(fp_rect (start -0.7 -0.5) (end 0.7 0.5)
(stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
(fp_line (start -0.575 -0.375) (end 0.575 -0.375) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 0.575 -0.375) (end 0.575 0.375) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 0.575 0.375) (end -0.575 0.375) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start -0.575 0.375) (end -0.575 -0.375) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_circle (center -0.7 -0.3) (end -0.45 -0.3) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
(pad "1" smd roundrect (at -0.35 0) (size 0.3 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "2" smd roundrect (at 0.35 0) (size 0.3 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(embedded_fonts no)
)
@@ -0,0 +1,35 @@
(footprint "Texas_RPW0010A_QFN10"
(version 20240108)
(generator "board-footprints")
(layer "F.Cu")
(descr "TI RPW0010A VQFN-HR; TI land pattern 4225183/A")
(attr smd)
(property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15))))
(property "Value" "" (at 0 5 0) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15))))
(fp_rect (start -1 -1) (end 1 1)
(stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
(fp_rect (start -1.5 -1.5) (end 1.5 1.5)
(stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
(fp_line (start -1.175 -1.175) (end 1.175 -1.175) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 1.175 -1.175) (end 1.175 1.175) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 1.175 1.175) (end -1.175 1.175) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start -1.175 1.175) (end -1.175 -1.175) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_circle (center -1.45 -1.15) (end -1.2 -1.15) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
(pad "1" smd roundrect (at -0.725 -0.9) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "1" smd roundrect (at -0.9 -0.75) (size 0.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "4" smd roundrect (at -0.725 0.9) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "4" smd roundrect (at -0.9 0.75) (size 0.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "7" smd roundrect (at 0.725 0.9) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "7" smd roundrect (at 0.9 0.75) (size 0.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "10" smd roundrect (at 0.725 -0.9) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "10" smd roundrect (at 0.9 -0.75) (size 0.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "2" smd roundrect (at -0.9 -0.225) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "3" smd roundrect (at -0.9 0.225) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "5" smd roundrect (at -0.25 0) (size 0.3 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "6" smd roundrect (at 0.25 0) (size 0.3 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "8" smd roundrect (at 0.9 0.225) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "9" smd roundrect (at 0.9 -0.225) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(embedded_fonts no)
)
@@ -0,0 +1,30 @@
(footprint "Texas_RQY0009A_VQFN9"
(version 20240108)
(generator "board-footprints")
(layer "F.Cu")
(descr "TI RQY0009A VQFN-HR; TI land pattern 4225639/A")
(attr smd)
(property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15))))
(property "Value" "" (at 0 5 0) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15))))
(fp_rect (start -0.75 -1) (end 0.75 1)
(stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
(fp_rect (start -1.4 -1.6) (end 1.4 1.6)
(stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
(fp_line (start -0.875 -1.225) (end 0.875 -1.225) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 0.875 -1.225) (end 0.875 1.225) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 0.875 1.225) (end -0.875 1.225) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start -0.875 1.225) (end -0.875 -1.225) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_circle (center -1.05 -1.25) (end -0.8 -1.25) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
(pad "1" smd roundrect (at -0.5 -1.175) (size 0.25 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "9" smd roundrect (at 0 -1.175) (size 0.25 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "8" smd roundrect (at 0.5 -1.175) (size 0.25 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "4" smd roundrect (at -0.5 1.175) (size 0.25 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "5" smd roundrect (at 0 1.175) (size 0.25 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "6" smd roundrect (at 0.5 1.175) (size 0.25 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "2" smd roundrect (at -0.475 -0.4) (size 0.95 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "3" smd roundrect (at -0.475 0.4) (size 0.95 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "7" smd roundrect (at 0.475 0) (size 0.95 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(embedded_fonts no)
)
@@ -0,0 +1,33 @@
(footprint "Texas_RUX0012A_VQFN12"
(version 20240108)
(generator "board-footprints")
(layer "F.Cu")
(descr "TI RUX0012A VQFN-HR; TI land pattern 4224010/A")
(attr smd)
(property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15))))
(property "Value" "" (at 0 5 0) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15))))
(fp_rect (start -1.25 -1.25) (end 1.25 1.25)
(stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
(fp_rect (start -1.7 -1.7) (end 1.7 1.7)
(stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
(fp_line (start -1.325 -1.325) (end 1.325 -1.325) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 1.325 -1.325) (end 1.325 1.325) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 1.325 1.325) (end -1.325 1.325) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start -1.325 1.325) (end -1.325 -1.325) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_circle (center -1.45 -1.2) (end -1.2 -1.2) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
(pad "1" smd roundrect (at -0.675 -0.35) (size 1.05 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "2" smd roundrect (at -0.675 0.35) (size 1.05 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "8" smd roundrect (at 0.675 -0.35) (size 1.05 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "7" smd roundrect (at 0.675 0.35) (size 1.05 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "12" smd roundrect (at -0.75 -1.15) (size 0.2 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "11" smd roundrect (at -0.25 -1.15) (size 0.2 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "10" smd roundrect (at 0.25 -1.15) (size 0.2 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "9" smd roundrect (at 0.75 -1.15) (size 0.2 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "3" smd roundrect (at -0.75 1.15) (size 0.2 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "4" smd roundrect (at -0.25 1.15) (size 0.2 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "5" smd roundrect (at 0.25 1.15) (size 0.2 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "6" smd roundrect (at 0.75 1.15) (size 0.2 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(embedded_fonts no)
)
@@ -0,0 +1,56 @@
(footprint "Texas_RZV0024A_WQFN24"
(version 20240108)
(generator "board-footprints")
(layer "F.Cu")
(descr "TI RZV0024A WQFN-FCRLF; TI land pattern 4228538/A")
(attr smd)
(property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15))))
(property "Value" "" (at 0 5 0) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15))))
(fp_rect (start -1.525 -2.025) (end 1.525 2.025)
(stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
(fp_rect (start -1.75 -2.25) (end 1.75 2.25)
(stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
(fp_line (start -1.575 -2.075) (end 1.575 -2.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 1.575 -2.075) (end 1.575 2.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start 1.575 2.075) (end -1.575 2.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_line (start -1.575 2.075) (end -1.575 -2.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
(fp_circle (center -1.75 -2.1) (end -1.5 -2.1) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
(pad "1" smd roundrect (at -1.25 -1.825) (size 0.25 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "1" smd roundrect (at -1.325 -1.75) (size 0.45 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "8" smd roundrect (at -1.25 1.825) (size 0.25 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "8" smd roundrect (at -1.325 1.75) (size 0.45 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "13" smd roundrect (at 1.25 1.825) (size 0.25 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "13" smd roundrect (at 1.325 1.75) (size 0.45 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "20" smd roundrect (at 1.25 -1.825) (size 0.25 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "20" smd roundrect (at 1.325 -1.75) (size 0.45 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "2" smd roundrect (at -1.25 -1.25) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "3" smd roundrect (at -1.25 -0.75) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "4" smd roundrect (at -1.25 -0.25) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "5" smd roundrect (at -1.25 0.25) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "6" smd roundrect (at -1.25 0.75) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "7" smd roundrect (at -1.25 1.25) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "19" smd roundrect (at 1.25 -1.25) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "18" smd roundrect (at 1.25 -0.75) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "17" smd roundrect (at 1.25 -0.25) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "16" smd roundrect (at 1.25 0.25) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "15" smd roundrect (at 1.25 0.75) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "14" smd roundrect (at 1.25 1.25) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "24" smd roundrect (at -0.75 -1.75) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "23" smd roundrect (at -0.25 -1.75) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "22" smd roundrect (at 0.25 -1.75) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "21" smd roundrect (at 0.75 -1.75) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "9" smd roundrect (at -0.75 1.75) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "10" smd roundrect (at -0.25 1.75) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "11" smd roundrect (at 0.25 1.75) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "12" smd roundrect (at 0.75 1.75) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
(pad "25" smd rect (at -0.425 -0.65) (size 0.6 1.1) (layers "F.Cu" "F.Mask"))
(pad "" smd roundrect (at -0.425 -0.65) (size 0.48 0.92) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "25" smd rect (at 0.425 -0.65) (size 0.6 1.1) (layers "F.Cu" "F.Mask"))
(pad "" smd roundrect (at 0.425 -0.65) (size 0.48 0.92) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "25" smd rect (at 0 0.65) (size 1.45 1.1) (layers "F.Cu" "F.Mask"))
(pad "" smd roundrect (at -0.3625 0.65) (size 0.605 0.92) (layers "F.Paste") (roundrect_rratio 0.15))
(pad "" smd roundrect (at 0.3625 0.65) (size 0.605 0.92) (layers "F.Paste") (roundrect_rratio 0.15))
(embedded_fonts no)
)
+53
View File
@@ -0,0 +1,53 @@
EESchema Schematic File Version 4
LIBS:board-cache
EELAYER 29 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 7
Title "Ti375 C529 GNSS/IMU acquisition board"
Date "2026-08-15"
Rev "A0"
Comp "JLCPCB manufacture/assembly package"
Comment1 "USB-C 5 V primary; protected external 5 V; no back-feed"
Comment2 "GPS L1/L1C direct MAX2771 MIXIN_HI; selectable active-antenna bias"
Comment3 "Every Ti375 programmable GPIO has a documented disposition"
Comment4 "Generated source - see docs/design_audit.md"
$EndDescr
$Sheet
S 1400 1000 3600 1200
U 66000001
F0 "POWER USB" 60
F1 "power_usb.sch" 60
$EndSheet
$Sheet
S 6200 1000 3600 1200
U 66000002
F0 "RF CLOCK" 60
F1 "rf_clock.sch" 60
$EndSheet
$Sheet
S 1400 2900 3600 1200
U 66000003
F0 "IMU" 60
F1 "imu.sch" 60
$EndSheet
$Sheet
S 6200 2900 3600 1200
U 66000004
F0 "USB DEBUG" 60
F1 "usb_debug.sch" 60
$EndSheet
$Sheet
S 1400 4800 3600 1200
U 66000005
F0 "CONFIGURATION EXPANSION" 60
F1 "configuration_expansion.sch" 60
$EndSheet
$Sheet
S 6200 4800 3600 1200
U 66000006
F0 "FPGA" 60
F1 "fpga.sch" 60
$EndSheet
$EndSCHEMATC
+373
View File
@@ -0,0 +1,373 @@
EESchema Schematic File Version 4
LIBS:board-cache
EELAYER 29 0
EELAYER END
$Descr A0 46811 33110
encoding utf-8
Sheet 1 1
Title "Ti375 GNSS/IMU board - Configuration Expansion"
Date "2026-08-15"
Rev "A0"
Comp "Open hardware design for JLCPCB"
Comment1 "Generated from scripts/design_data.py; do not hand-edit"
Comment2 "No LEDs, no push buttons"
Comment3 "Ti375C529C3 / MAX2771 / SCH16T-K01-1"
Comment4 "JLC08161H-3313 eight-layer stack"
$EndDescr
$Comp
L BOARD_U26 U26
U 1 1 65050001
P 1800 1800
F 0 "U26" H 1800 1700 50 0000 C CNN
F 1 "512-Mbit QSPI flash" H 1800 1900 50 0000 C CNN
F 2 "Package_SON:WSON-8-1EP_6x5mm_P1.27mm_EP3.4x4.3mm" H 1800 1600 50 0001 C CNN
F 3 "" H 1800 1800 50 0001 C CNN
F 4 "IS25WP512M-JLLE" H 1800 1800 50 0001 C CNN "MPN"
F 5 "ISSI" H 1800 1800 50 0001 C CNN "Manufacturer"
1 1800 1800
1 0 0 -1
$EndComp
Wire Wire Line
1100 2000 950 2000
Text GLabel 950 2000 2 30 BiDi ~ 0
QSPI_CS_N
Wire Wire Line
2500 1950 2650 1950
Text GLabel 2650 1950 0 30 BiDi ~ 0
QSPI_IO1
Wire Wire Line
1100 1900 950 1900
Text GLabel 950 1900 2 30 BiDi ~ 0
QSPI_IO2
Wire Wire Line
2500 1850 2650 1850
Text GLabel 2650 1850 0 30 BiDi ~ 0
GND
Wire Wire Line
1100 1800 950 1800
Text GLabel 950 1800 2 30 BiDi ~ 0
QSPI_IO0
Wire Wire Line
2500 1750 2650 1750
Text GLabel 2650 1750 0 30 BiDi ~ 0
QSPI_SCLK
Wire Wire Line
1100 1700 950 1700
Text GLabel 950 1700 2 30 BiDi ~ 0
QSPI_IO3
Wire Wire Line
2500 1650 2650 1650
Text GLabel 2650 1650 0 30 BiDi ~ 0
VCC1V8
Wire Wire Line
1100 1600 950 1600
Text GLabel 950 1600 2 30 BiDi ~ 0
GND
$Comp
L BOARD_R84 R84
U 1 1 65050002
P 1800 2900
F 0 "R84" H 1800 2800 50 0000 C CNN
F 1 "10K" H 1800 3000 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 2700 50 0001 C CNN
F 3 "" H 1800 2900 50 0001 C CNN
F 4 "RC0402FR-0710KL" H 1800 2900 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 2900 50 0001 C CNN "Manufacturer"
1 1800 2900
1 0 0 -1
$EndComp
Wire Wire Line
1100 2900 950 2900
Text GLabel 950 2900 2 30 BiDi ~ 0
VCC1V8
Wire Wire Line
2500 2900 2650 2900
Text GLabel 2650 2900 0 30 BiDi ~ 0
QSPI_CS_N
$Comp
L BOARD_R87 R87
U 1 1 65050003
P 1800 3700
F 0 "R87" H 1800 3600 50 0000 C CNN
F 1 "10K" H 1800 3800 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 3500 50 0001 C CNN
F 3 "" H 1800 3700 50 0001 C CNN
F 4 "RC0402FR-0710KL" H 1800 3700 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 3700 50 0001 C CNN "Manufacturer"
1 1800 3700
1 0 0 -1
$EndComp
Wire Wire Line
1100 3700 950 3700
Text GLabel 950 3700 2 30 BiDi ~ 0
VCC1V8
Wire Wire Line
2500 3700 2650 3700
Text GLabel 2650 3700 0 30 BiDi ~ 0
QSPI_IO2
$Comp
L BOARD_R88 R88
U 1 1 65050004
P 1800 4500
F 0 "R88" H 1800 4400 50 0000 C CNN
F 1 "10K" H 1800 4600 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 4300 50 0001 C CNN
F 3 "" H 1800 4500 50 0001 C CNN
F 4 "RC0402FR-0710KL" H 1800 4500 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 4500 50 0001 C CNN "Manufacturer"
1 1800 4500
1 0 0 -1
$EndComp
Wire Wire Line
1100 4500 950 4500
Text GLabel 950 4500 2 30 BiDi ~ 0
VCC1V8
Wire Wire Line
2500 4500 2650 4500
Text GLabel 2650 4500 0 30 BiDi ~ 0
QSPI_IO3
$Comp
L BOARD_JPMOD1 JPMOD1
U 1 1 65050005
P 1800 5300
F 0 "JPMOD1" H 1800 5200 50 0000 C CNN
F 1 "PMOD 3.3 V" H 1800 5400 50 0000 C CNN
F 2 "board:Digilent_PMOD_2x6_P2.54mm" H 1800 5100 50 0001 C CNN
F 3 "" H 1800 5300 50 0001 C CNN
F 4 "67997-412HLF" H 1800 5300 50 0001 C CNN "MPN"
F 5 "Amphenol ICC" H 1800 5300 50 0001 C CNN "Manufacturer"
1 1800 5300
1 0 0 -1
$EndComp
Wire Wire Line
1100 5550 950 5550
Text GLabel 950 5550 2 30 BiDi ~ 0
PMOD1_1
Wire Wire Line
2500 5550 2650 5550
Text GLabel 2650 5550 0 30 BiDi ~ 0
PMOD1_2
Wire Wire Line
1100 5450 950 5450
Text GLabel 950 5450 2 30 BiDi ~ 0
PMOD1_3
Wire Wire Line
2500 5450 2650 5450
Text GLabel 2650 5450 0 30 BiDi ~ 0
PMOD1_4
Wire Wire Line
1100 5350 950 5350
Text GLabel 950 5350 2 30 BiDi ~ 0
GND
Wire Wire Line
2500 5350 2650 5350
Text GLabel 2650 5350 0 30 BiDi ~ 0
VCC3V3
Wire Wire Line
1100 5250 950 5250
Text GLabel 950 5250 2 30 BiDi ~ 0
PMOD1_7
Wire Wire Line
2500 5250 2650 5250
Text GLabel 2650 5250 0 30 BiDi ~ 0
PMOD1_8
Wire Wire Line
1100 5150 950 5150
Text GLabel 950 5150 2 30 BiDi ~ 0
PMOD1_9
Wire Wire Line
2500 5150 2650 5150
Text GLabel 2650 5150 0 30 BiDi ~ 0
PMOD1_10
Wire Wire Line
1100 5050 950 5050
Text GLabel 950 5050 2 30 BiDi ~ 0
GND
Wire Wire Line
2500 5050 2650 5050
Text GLabel 2650 5050 0 30 BiDi ~ 0
VCC3V3
$Comp
L BOARD_JPMOD2 JPMOD2
U 1 1 65050006
P 1800 6500
F 0 "JPMOD2" H 1800 6400 50 0000 C CNN
F 1 "PMOD 3.3 V" H 1800 6600 50 0000 C CNN
F 2 "board:Digilent_PMOD_2x6_P2.54mm" H 1800 6300 50 0001 C CNN
F 3 "" H 1800 6500 50 0001 C CNN
F 4 "67997-412HLF" H 1800 6500 50 0001 C CNN "MPN"
F 5 "Amphenol ICC" H 1800 6500 50 0001 C CNN "Manufacturer"
1 1800 6500
1 0 0 -1
$EndComp
Wire Wire Line
1100 6750 950 6750
Text GLabel 950 6750 2 30 BiDi ~ 0
PMOD2_1
Wire Wire Line
2500 6750 2650 6750
Text GLabel 2650 6750 0 30 BiDi ~ 0
PMOD2_2
Wire Wire Line
1100 6650 950 6650
Text GLabel 950 6650 2 30 BiDi ~ 0
PMOD2_3
Wire Wire Line
2500 6650 2650 6650
Text GLabel 2650 6650 0 30 BiDi ~ 0
PMOD2_4
Wire Wire Line
1100 6550 950 6550
Text GLabel 950 6550 2 30 BiDi ~ 0
GND
Wire Wire Line
2500 6550 2650 6550
Text GLabel 2650 6550 0 30 BiDi ~ 0
VCC3V3
Wire Wire Line
1100 6450 950 6450
Text GLabel 950 6450 2 30 BiDi ~ 0
PMOD2_7
Wire Wire Line
2500 6450 2650 6450
Text GLabel 2650 6450 0 30 BiDi ~ 0
PMOD2_8
Wire Wire Line
1100 6350 950 6350
Text GLabel 950 6350 2 30 BiDi ~ 0
PMOD2_9
Wire Wire Line
2500 6350 2650 6350
Text GLabel 2650 6350 0 30 BiDi ~ 0
PMOD2_10
Wire Wire Line
1100 6250 950 6250
Text GLabel 950 6250 2 30 BiDi ~ 0
GND
Wire Wire Line
2500 6250 2650 6250
Text GLabel 2650 6250 0 30 BiDi ~ 0
VCC3V3
$Comp
L BOARD_JPMOD3 JPMOD3
U 1 1 65050007
P 1800 7700
F 0 "JPMOD3" H 1800 7600 50 0000 C CNN
F 1 "PMOD 1.8 V" H 1800 7800 50 0000 C CNN
F 2 "board:Digilent_PMOD_2x6_P2.54mm" H 1800 7500 50 0001 C CNN
F 3 "" H 1800 7700 50 0001 C CNN
F 4 "67997-412HLF" H 1800 7700 50 0001 C CNN "MPN"
F 5 "Amphenol ICC" H 1800 7700 50 0001 C CNN "Manufacturer"
1 1800 7700
1 0 0 -1
$EndComp
Wire Wire Line
1100 7950 950 7950
Text GLabel 950 7950 2 30 BiDi ~ 0
PMOD3_1
Wire Wire Line
2500 7950 2650 7950
Text GLabel 2650 7950 0 30 BiDi ~ 0
PMOD3_2
Wire Wire Line
1100 7850 950 7850
Text GLabel 950 7850 2 30 BiDi ~ 0
PMOD3_3
Wire Wire Line
2500 7850 2650 7850
Text GLabel 2650 7850 0 30 BiDi ~ 0
PMOD3_4
Wire Wire Line
1100 7750 950 7750
Text GLabel 950 7750 2 30 BiDi ~ 0
GND
Wire Wire Line
2500 7750 2650 7750
Text GLabel 2650 7750 0 30 BiDi ~ 0
VCC1V8
Wire Wire Line
1100 7650 950 7650
Text GLabel 950 7650 2 30 BiDi ~ 0
PMOD3_7
Wire Wire Line
2500 7650 2650 7650
Text GLabel 2650 7650 0 30 BiDi ~ 0
PMOD3_8
Wire Wire Line
1100 7550 950 7550
Text GLabel 950 7550 2 30 BiDi ~ 0
PMOD3_9
Wire Wire Line
2500 7550 2650 7550
Text GLabel 2650 7550 0 30 BiDi ~ 0
PMOD3_10
Wire Wire Line
1100 7450 950 7450
Text GLabel 950 7450 2 30 BiDi ~ 0
GND
Wire Wire Line
2500 7450 2650 7450
Text GLabel 2650 7450 0 30 BiDi ~ 0
VCC1V8
$Comp
L BOARD_JPMOD4 JPMOD4
U 1 1 65050008
P 1800 8900
F 0 "JPMOD4" H 1800 8800 50 0000 C CNN
F 1 "PMOD 1.8 V" H 1800 9000 50 0000 C CNN
F 2 "board:Digilent_PMOD_2x6_P2.54mm" H 1800 8700 50 0001 C CNN
F 3 "" H 1800 8900 50 0001 C CNN
F 4 "67997-412HLF" H 1800 8900 50 0001 C CNN "MPN"
F 5 "Amphenol ICC" H 1800 8900 50 0001 C CNN "Manufacturer"
1 1800 8900
1 0 0 -1
$EndComp
Wire Wire Line
1100 9150 950 9150
Text GLabel 950 9150 2 30 BiDi ~ 0
PMOD4_1
Wire Wire Line
2500 9150 2650 9150
Text GLabel 2650 9150 0 30 BiDi ~ 0
PMOD4_2
Wire Wire Line
1100 9050 950 9050
Text GLabel 950 9050 2 30 BiDi ~ 0
PMOD4_3
Wire Wire Line
2500 9050 2650 9050
Text GLabel 2650 9050 0 30 BiDi ~ 0
PMOD4_4
Wire Wire Line
1100 8950 950 8950
Text GLabel 950 8950 2 30 BiDi ~ 0
GND
Wire Wire Line
2500 8950 2650 8950
Text GLabel 2650 8950 0 30 BiDi ~ 0
VCC1V8
Wire Wire Line
1100 8850 950 8850
Text GLabel 950 8850 2 30 BiDi ~ 0
PMOD4_7
Wire Wire Line
2500 8850 2650 8850
Text GLabel 2650 8850 0 30 BiDi ~ 0
PMOD4_8
Wire Wire Line
1100 8750 950 8750
Text GLabel 950 8750 2 30 BiDi ~ 0
PMOD4_9
Wire Wire Line
2500 8750 2650 8750
Text GLabel 2650 8750 0 30 BiDi ~ 0
PMOD4_10
Wire Wire Line
1100 8650 950 8650
Text GLabel 950 8650 2 30 BiDi ~ 0
GND
Wire Wire Line
2500 8650 2650 8650
Text GLabel 2650 8650 0 30 BiDi ~ 0
VCC1V8
$EndSCHEMATC
+4
View File
@@ -0,0 +1,4 @@
(fp_lib_table
(version 7)
(lib (name "board")(type "KiCad")(uri "${KIPRJMOD}/board.pretty")(options "")(descr "Official-land-pattern custom footprints"))
)
+1616
View File
File diff suppressed because it is too large Load Diff
+333
View File
@@ -0,0 +1,333 @@
EESchema Schematic File Version 4
LIBS:board-cache
EELAYER 29 0
EELAYER END
$Descr A0 46811 33110
encoding utf-8
Sheet 1 1
Title "Ti375 GNSS/IMU board - Imu"
Date "2026-08-15"
Rev "A0"
Comp "Open hardware design for JLCPCB"
Comment1 "Generated from scripts/design_data.py; do not hand-edit"
Comment2 "No LEDs, no push buttons"
Comment3 "Ti375C529C3 / MAX2771 / SCH16T-K01-1"
Comment4 "JLC08161H-3313 eight-layer stack"
$EndDescr
$Comp
L BOARD_U22 U22
U 1 1 65030001
P 1800 1800
F 0 "U22" H 1800 1700 50 0000 C CNN
F 1 "SCH16T-K01-1" H 1800 1900 50 0000 C CNN
F 2 "board:Murata_SCH16T_K01" H 1800 1600 50 0001 C CNN
F 3 "" H 1800 1800 50 0001 C CNN
F 4 "SCH16T-K01-1" H 1800 1800 50 0001 C CNN "MPN"
F 5 "Murata" H 1800 1800 50 0001 C CNN "Manufacturer"
1 1800 1800
1 0 0 -1
$EndComp
Wire Wire Line
1100 2350 950 2350
Text GLabel 950 2350 2 30 BiDi ~ 0
GND
NoConn ~ 2500 2350
Wire Wire Line
1100 2250 950 2250
Text GLabel 950 2250 2 30 BiDi ~ 0
GND
Wire Wire Line
2500 2250 2650 2250
Text GLabel 2650 2250 0 30 BiDi ~ 0
GND
Wire Wire Line
1100 2150 950 2150
Text GLabel 950 2150 2 30 BiDi ~ 0
GND
Wire Wire Line
2500 2150 2650 2150
Text GLabel 2650 2150 0 30 BiDi ~ 0
IMU_EXTRESN
Wire Wire Line
1100 2050 950 2050
Text GLabel 950 2050 2 30 BiDi ~ 0
GND
Wire Wire Line
2500 2050 2650 2050
Text GLabel 2650 2050 0 30 BiDi ~ 0
IMU_3V3
Wire Wire Line
1100 1950 950 1950
Text GLabel 950 1950 2 30 BiDi ~ 0
GND
Wire Wire Line
2500 1950 2650 1950
Text GLabel 2650 1950 0 30 BiDi ~ 0
IMU_VREGA2
Wire Wire Line
1100 1850 950 1850
Text GLabel 950 1850 2 30 BiDi ~ 0
IMU_VREGA2
Wire Wire Line
2500 1850 2650 1850
Text GLabel 2650 1850 0 30 BiDi ~ 0
GND
Wire Wire Line
1100 1750 950 1750
Text GLabel 950 1750 2 30 BiDi ~ 0
GND
Wire Wire Line
2500 1750 2650 1750
Text GLabel 2650 1750 0 30 BiDi ~ 0
IMU_VREGD
Wire Wire Line
1100 1650 950 1650
Text GLabel 950 1650 2 30 BiDi ~ 0
IMU_VREGD
Wire Wire Line
2500 1650 2650 1650
Text GLabel 2650 1650 0 30 BiDi ~ 0
GND
Wire Wire Line
1100 1550 950 1550
Text GLabel 950 1550 2 30 BiDi ~ 0
IMU_3V3
Wire Wire Line
2500 1550 2650 1550
Text GLabel 2650 1550 0 30 BiDi ~ 0
VCC3V3
Wire Wire Line
1100 1450 950 1450
Text GLabel 950 1450 2 30 BiDi ~ 0
IMU_MISO_DEV
Wire Wire Line
2500 1450 2650 1450
Text GLabel 2650 1450 0 30 BiDi ~ 0
IMU_DRY_SYNC
Wire Wire Line
1100 1350 950 1350
Text GLabel 950 1350 2 30 BiDi ~ 0
IMU_SCK_DEV
Wire Wire Line
2500 1350 2650 1350
Text GLabel 2650 1350 0 30 BiDi ~ 0
IMU_CS_DEV
Wire Wire Line
1100 1250 950 1250
Text GLabel 950 1250 2 30 BiDi ~ 0
IMU_MOSI_DEV
Wire Wire Line
2500 1250 2650 1250
Text GLabel 2650 1250 0 30 BiDi ~ 0
GND
$Comp
L BOARD_FB1 FB1
U 1 1 65030002
P 1800 3600
F 0 "FB1" H 1800 3500 50 0000 C CNN
F 1 "600R@100MHz" H 1800 3700 50 0000 C CNN
F 2 "Inductor_SMD:L_0402_1005Metric" H 1800 3400 50 0001 C CNN
F 3 "" H 1800 3600 50 0001 C CNN
F 4 "BLM15AG601SN1D" H 1800 3600 50 0001 C CNN "MPN"
F 5 "Murata" H 1800 3600 50 0001 C CNN "Manufacturer"
1 1800 3600
1 0 0 -1
$EndComp
Wire Wire Line
1100 3600 950 3600
Text GLabel 950 3600 2 30 BiDi ~ 0
VCC3V3
Wire Wire Line
2500 3600 2650 3600
Text GLabel 2650 3600 0 30 BiDi ~ 0
IMU_3V3
$Comp
L BOARD_R57 R57
U 1 1 65030003
P 1800 4400
F 0 "R57" H 1800 4300 50 0000 C CNN
F 1 "22R" H 1800 4500 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 4200 50 0001 C CNN
F 3 "" H 1800 4400 50 0001 C CNN
F 4 "RC0402FR-0722RL" H 1800 4400 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 4400 50 0001 C CNN "Manufacturer"
1 1800 4400
1 0 0 -1
$EndComp
Wire Wire Line
1100 4400 950 4400
Text GLabel 950 4400 2 30 BiDi ~ 0
IMU_SCK
Wire Wire Line
2500 4400 2650 4400
Text GLabel 2650 4400 0 30 BiDi ~ 0
IMU_SCK_DEV
$Comp
L BOARD_R58 R58
U 1 1 65030004
P 1800 5200
F 0 "R58" H 1800 5100 50 0000 C CNN
F 1 "22R" H 1800 5300 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 5000 50 0001 C CNN
F 3 "" H 1800 5200 50 0001 C CNN
F 4 "RC0402FR-0722RL" H 1800 5200 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 5200 50 0001 C CNN "Manufacturer"
1 1800 5200
1 0 0 -1
$EndComp
Wire Wire Line
1100 5200 950 5200
Text GLabel 950 5200 2 30 BiDi ~ 0
IMU_MOSI
Wire Wire Line
2500 5200 2650 5200
Text GLabel 2650 5200 0 30 BiDi ~ 0
IMU_MOSI_DEV
$Comp
L BOARD_R59 R59
U 1 1 65030005
P 1800 6000
F 0 "R59" H 1800 5900 50 0000 C CNN
F 1 "22R" H 1800 6100 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 5800 50 0001 C CNN
F 3 "" H 1800 6000 50 0001 C CNN
F 4 "RC0402FR-0722RL" H 1800 6000 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 6000 50 0001 C CNN "Manufacturer"
1 1800 6000
1 0 0 -1
$EndComp
Wire Wire Line
1100 6000 950 6000
Text GLabel 950 6000 2 30 BiDi ~ 0
IMU_CS
Wire Wire Line
2500 6000 2650 6000
Text GLabel 2650 6000 0 30 BiDi ~ 0
IMU_CS_DEV
$Comp
L BOARD_R60 R60
U 1 1 65030006
P 1800 6800
F 0 "R60" H 1800 6700 50 0000 C CNN
F 1 "22R" H 1800 6900 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 6600 50 0001 C CNN
F 3 "" H 1800 6800 50 0001 C CNN
F 4 "RC0402FR-0722RL" H 1800 6800 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 6800 50 0001 C CNN "Manufacturer"
1 1800 6800
1 0 0 -1
$EndComp
Wire Wire Line
1100 6800 950 6800
Text GLabel 950 6800 2 30 BiDi ~ 0
IMU_MISO_DEV
Wire Wire Line
2500 6800 2650 6800
Text GLabel 2650 6800 0 30 BiDi ~ 0
IMU_MISO
$Comp
L BOARD_R61 R61
U 1 1 65030007
P 1800 7600
F 0 "R61" H 1800 7500 50 0000 C CNN
F 1 "10K" H 1800 7700 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 7400 50 0001 C CNN
F 3 "" H 1800 7600 50 0001 C CNN
F 4 "RC0402FR-0710KL" H 1800 7600 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 7600 50 0001 C CNN "Manufacturer"
1 1800 7600
1 0 0 -1
$EndComp
Wire Wire Line
1100 7600 950 7600
Text GLabel 950 7600 2 30 BiDi ~ 0
IMU_EXTRESN
Wire Wire Line
2500 7600 2650 7600
Text GLabel 2650 7600 0 30 BiDi ~ 0
GND
$Comp
L BOARD_C103 C103
U 1 1 65030008
P 1800 8400
F 0 "C103" H 1800 8300 50 0000 C CNN
F 1 "100nF" H 1800 8500 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 1800 8200 50 0001 C CNN
F 3 "" H 1800 8400 50 0001 C CNN
F 4 "GRM155R71A104KA01D" H 1800 8400 50 0001 C CNN "MPN"
F 5 "Murata" H 1800 8400 50 0001 C CNN "Manufacturer"
1 1800 8400
1 0 0 -1
$EndComp
Wire Wire Line
1100 8400 950 8400
Text GLabel 950 8400 2 30 BiDi ~ 0
IMU_3V3
Wire Wire Line
2500 8400 2650 8400
Text GLabel 2650 8400 0 30 BiDi ~ 0
GND
$Comp
L BOARD_C104 C104
U 1 1 65030009
P 1800 9200
F 0 "C104" H 1800 9100 50 0000 C CNN
F 1 "1uF" H 1800 9300 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 1800 9000 50 0001 C CNN
F 3 "" H 1800 9200 50 0001 C CNN
F 4 "GRM155R60J105KE19D" H 1800 9200 50 0001 C CNN "MPN"
F 5 "Murata" H 1800 9200 50 0001 C CNN "Manufacturer"
1 1800 9200
1 0 0 -1
$EndComp
Wire Wire Line
1100 9200 950 9200
Text GLabel 950 9200 2 30 BiDi ~ 0
IMU_3V3
Wire Wire Line
2500 9200 2650 9200
Text GLabel 2650 9200 0 30 BiDi ~ 0
GND
$Comp
L BOARD_C105 C105
U 1 1 6503000A
P 1800 10000
F 0 "C105" H 1800 9900 50 0000 C CNN
F 1 "10uF" H 1800 10100 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 1800 9800 50 0001 C CNN
F 3 "" H 1800 10000 50 0001 C CNN
F 4 "GRM188R60J106ME47D" H 1800 10000 50 0001 C CNN "MPN"
F 5 "Murata" H 1800 10000 50 0001 C CNN "Manufacturer"
1 1800 10000
1 0 0 -1
$EndComp
Wire Wire Line
1100 10000 950 10000
Text GLabel 950 10000 2 30 BiDi ~ 0
IMU_VREGA2
Wire Wire Line
2500 10000 2650 10000
Text GLabel 2650 10000 0 30 BiDi ~ 0
GND
$Comp
L BOARD_C106 C106
U 1 1 6503000B
P 1800 10800
F 0 "C106" H 1800 10700 50 0000 C CNN
F 1 "1uF" H 1800 10900 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 1800 10600 50 0001 C CNN
F 3 "" H 1800 10800 50 0001 C CNN
F 4 "GRM155R60J105KE19D" H 1800 10800 50 0001 C CNN "MPN"
F 5 "Murata" H 1800 10800 50 0001 C CNN "Manufacturer"
1 1800 10800
1 0 0 -1
$EndComp
Wire Wire Line
1100 10800 950 10800
Text GLabel 950 10800 2 30 BiDi ~ 0
IMU_VREGD
Wire Wire Line
2500 10800 2650 10800
Text GLabel 2650 10800 0 30 BiDi ~ 0
GND
$EndSCHEMATC
File diff suppressed because it is too large Load Diff
+894
View File
@@ -0,0 +1,894 @@
EESchema Schematic File Version 4
LIBS:board-cache
EELAYER 29 0
EELAYER END
$Descr A0 46811 33110
encoding utf-8
Sheet 1 1
Title "Ti375 GNSS/IMU board - Rf Clock"
Date "2026-08-15"
Rev "A0"
Comp "Open hardware design for JLCPCB"
Comment1 "Generated from scripts/design_data.py; do not hand-edit"
Comment2 "No LEDs, no push buttons"
Comment3 "Ti375C529C3 / MAX2771 / SCH16T-K01-1"
Comment4 "JLC08161H-3313 eight-layer stack"
$EndDescr
$Comp
L BOARD_J2 J2
U 1 1 65020001
P 1800 1800
F 0 "J2" H 1800 1700 50 0000 C CNN
F 1 "GPS L1 SMA" H 1800 1900 50 0000 C CNN
F 2 "Connector_Coaxial:SMA_Amphenol_132289_EdgeMount" H 1800 1600 50 0001 C CNN
F 3 "" H 1800 1800 50 0001 C CNN
F 4 "132289" H 1800 1800 50 0001 C CNN "MPN"
F 5 "Amphenol RF" H 1800 1800 50 0001 C CNN "Manufacturer"
1 1800 1800
1 0 0 -1
$EndComp
Wire Wire Line
1100 1800 950 1800
Text GLabel 950 1800 2 30 BiDi ~ 0
RF_SMA
Wire Wire Line
2500 1800 2650 1800
Text GLabel 2650 1800 0 30 BiDi ~ 0
GND
$Comp
L BOARD_D1 D1
U 1 1 65020002
P 1800 2600
F 0 "D1" H 1800 2500 50 0000 C CNN
F 1 "ESD501" H 1800 2700 50 0000 C CNN
F 2 "board:Texas_DPY0002A_X1SON" H 1800 2400 50 0001 C CNN
F 3 "" H 1800 2600 50 0001 C CNN
F 4 "ESD501DPYR" H 1800 2600 50 0001 C CNN "MPN"
F 5 "Texas Instruments" H 1800 2600 50 0001 C CNN "Manufacturer"
1 1800 2600
1 0 0 -1
$EndComp
Wire Wire Line
1100 2600 950 2600
Text GLabel 950 2600 2 30 BiDi ~ 0
RF_SMA
Wire Wire Line
2500 2600 2650 2600
Text GLabel 2650 2600 0 30 BiDi ~ 0
GND
$Comp
L BOARD_C83 C83
U 1 1 65020003
P 1800 3400
F 0 "C83" H 1800 3300 50 0000 C CNN
F 1 "27pF" H 1800 3500 50 0000 C CNN
F 2 "board:Kyocera_600L_0402" H 1800 3200 50 0001 C CNN
F 3 "" H 1800 3400 50 0001 C CNN
F 4 "600L270JT200T" H 1800 3400 50 0001 C CNN "MPN"
F 5 "Murata" H 1800 3400 50 0001 C CNN "Manufacturer"
1 1800 3400
1 0 0 -1
$EndComp
Wire Wire Line
1100 3400 950 3400
Text GLabel 950 3400 2 30 BiDi ~ 0
RF_SMA
Wire Wire Line
2500 3400 2650 3400
Text GLabel 2650 3400 0 30 BiDi ~ 0
RF_PRE_SAW
$Comp
L BOARD_FL1 FL1
U 1 1 65020004
P 1800 4200
F 0 "FL1" H 1800 4100 50 0000 C CNN
F 1 "GPS L1/L1C SAW" H 1800 4300 50 0000 C CNN
F 2 "board:Kyocera_SF14_5pad" H 1800 4000 50 0001 C CNN
F 3 "" H 1800 4200 50 0001 C CNN
F 4 "SF14-1582M5UUS2" H 1800 4200 50 0001 C CNN "MPN"
F 5 "Kyocera" H 1800 4200 50 0001 C CNN "Manufacturer"
1 1800 4200
1 0 0 -1
$EndComp
Wire Wire Line
1100 4300 950 4300
Text GLabel 950 4300 2 30 BiDi ~ 0
RF_PRE_SAW
Wire Wire Line
2500 4250 2650 4250
Text GLabel 2650 4250 0 30 BiDi ~ 0
GND
Wire Wire Line
1100 4200 950 4200
Text GLabel 950 4200 2 30 BiDi ~ 0
GND
Wire Wire Line
2500 4150 2650 4150
Text GLabel 2650 4150 0 30 BiDi ~ 0
RF_POST_SAW
Wire Wire Line
1100 4100 950 4100
Text GLabel 950 4100 2 30 BiDi ~ 0
GND
$Comp
L BOARD_C84 C84
U 1 1 65020005
P 1800 5100
F 0 "C84" H 1800 5000 50 0000 C CNN
F 1 "DNP" H 1800 5200 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 1800 4900 50 0001 C CNN
F 3 "" H 1800 5100 50 0001 C CNN
F 4 "" H 1800 5100 50 0001 C CNN "MPN"
F 5 "Murata" H 1800 5100 50 0001 C CNN "Manufacturer"
1 1800 5100
1 0 0 -1
$EndComp
Wire Wire Line
1100 5100 950 5100
Text GLabel 950 5100 2 30 BiDi ~ 0
RF_POST_SAW
Wire Wire Line
2500 5100 2650 5100
Text GLabel 2650 5100 0 30 BiDi ~ 0
GND
$Comp
L BOARD_R39 R39
U 1 1 65020006
P 1800 5900
F 0 "R39" H 1800 5800 50 0000 C CNN
F 1 "0R" H 1800 6000 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 5700 50 0001 C CNN
F 3 "" H 1800 5900 50 0001 C CNN
F 4 "RC0402JR-070RL" H 1800 5900 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 5900 50 0001 C CNN "Manufacturer"
1 1800 5900
1 0 0 -1
$EndComp
Wire Wire Line
1100 5900 950 5900
Text GLabel 950 5900 2 30 BiDi ~ 0
RF_POST_SAW
Wire Wire Line
2500 5900 2650 5900
Text GLabel 2650 5900 0 30 BiDi ~ 0
MAX_MIXIN_HI
$Comp
L BOARD_C85 C85
U 1 1 65020007
P 1800 6700
F 0 "C85" H 1800 6600 50 0000 C CNN
F 1 "DNP" H 1800 6800 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 1800 6500 50 0001 C CNN
F 3 "" H 1800 6700 50 0001 C CNN
F 4 "" H 1800 6700 50 0001 C CNN "MPN"
F 5 "Murata" H 1800 6700 50 0001 C CNN "Manufacturer"
1 1800 6700
1 0 0 -1
$EndComp
Wire Wire Line
1100 6700 950 6700
Text GLabel 950 6700 2 30 BiDi ~ 0
MAX_MIXIN_HI
Wire Wire Line
2500 6700 2650 6700
Text GLabel 2650 6700 0 30 BiDi ~ 0
GND
$Comp
L BOARD_J5 J5
U 1 1 65020008
P 1800 7500
F 0 "J5" H 1800 7400 50 0000 C CNN
F 1 "ANT BIAS OFF/3V3/5V" H 1800 7600 50 0000 C CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical" H 1800 7300 50 0001 C CNN
F 3 "" H 1800 7500 50 0001 C CNN
F 4 "61300311121" H 1800 7500 50 0001 C CNN "MPN"
F 5 "Wuerth Elektronik" H 1800 7500 50 0001 C CNN "Manufacturer"
1 1800 7500
1 0 0 -1
$EndComp
Wire Wire Line
1100 7550 950 7550
Text GLabel 950 7550 2 30 BiDi ~ 0
VCC3V3_ANT
Wire Wire Line
2500 7500 2650 7500
Text GLabel 2650 7500 0 30 BiDi ~ 0
ANT_BIAS_SEL
Wire Wire Line
1100 7450 950 7450
Text GLabel 950 7450 2 30 BiDi ~ 0
SYS5
$Comp
L BOARD_U27 U27
U 1 1 65020009
P 1800 8300
F 0 "U27" H 1800 8200 50 0000 C CNN
F 1 "TPS22944" H 1800 8400 50 0000 C CNN
F 2 "Package_TO_SOT_SMD:SOT-353_SC-70-5" H 1800 8100 50 0001 C CNN
F 3 "" H 1800 8300 50 0001 C CNN
F 4 "TPS22944DCKR" H 1800 8300 50 0001 C CNN "MPN"
F 5 "Texas Instruments" H 1800 8300 50 0001 C CNN "Manufacturer"
1 1800 8300
1 0 0 -1
$EndComp
Wire Wire Line
1100 8400 950 8400
Text GLabel 950 8400 2 30 BiDi ~ 0
ANT_BIAS_SW
Wire Wire Line
2500 8350 2650 8350
Text GLabel 2650 8350 0 30 BiDi ~ 0
GND
Wire Wire Line
1100 8300 950 8300
Text GLabel 950 8300 2 30 BiDi ~ 0
ANT_BIAS_OC
Wire Wire Line
2500 8250 2650 8250
Text GLabel 2650 8250 0 30 BiDi ~ 0
ANT_BIAS_ON
Wire Wire Line
1100 8200 950 8200
Text GLabel 950 8200 2 30 BiDi ~ 0
ANT_BIAS_SEL
$Comp
L BOARD_R40 R40
U 1 1 6502000A
P 1800 9200
F 0 "R40" H 1800 9100 50 0000 C CNN
F 1 "100K" H 1800 9300 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 9000 50 0001 C CNN
F 3 "" H 1800 9200 50 0001 C CNN
F 4 "RC0402FR-07100KL" H 1800 9200 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 9200 50 0001 C CNN "Manufacturer"
1 1800 9200
1 0 0 -1
$EndComp
Wire Wire Line
1100 9200 950 9200
Text GLabel 950 9200 2 30 BiDi ~ 0
ANT_BIAS_SEL
Wire Wire Line
2500 9200 2650 9200
Text GLabel 2650 9200 0 30 BiDi ~ 0
ANT_BIAS_ON
$Comp
L BOARD_R41 R41
U 1 1 6502000B
P 1800 10000
F 0 "R41" H 1800 9900 50 0000 C CNN
F 1 "100K" H 1800 10100 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 9800 50 0001 C CNN
F 3 "" H 1800 10000 50 0001 C CNN
F 4 "RC0402FR-07100KL" H 1800 10000 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 10000 50 0001 C CNN "Manufacturer"
1 1800 10000
1 0 0 -1
$EndComp
Wire Wire Line
1100 10000 950 10000
Text GLabel 950 10000 2 30 BiDi ~ 0
ANT_BIAS_ON
Wire Wire Line
2500 10000 2650 10000
Text GLabel 2650 10000 0 30 BiDi ~ 0
GND
$Comp
L BOARD_R42 R42
U 1 1 6502000C
P 1800 10800
F 0 "R42" H 1800 10700 50 0000 C CNN
F 1 "10K" H 1800 10900 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 10600 50 0001 C CNN
F 3 "" H 1800 10800 50 0001 C CNN
F 4 "RC0402FR-0710KL" H 1800 10800 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 10800 50 0001 C CNN "Manufacturer"
1 1800 10800
1 0 0 -1
$EndComp
Wire Wire Line
1100 10800 950 10800
Text GLabel 950 10800 2 30 BiDi ~ 0
VCC3V3_AUX
Wire Wire Line
2500 10800 2650 10800
Text GLabel 2650 10800 0 30 BiDi ~ 0
ANT_BIAS_OC
$Comp
L BOARD_C86 C86
U 1 1 6502000D
P 1800 11600
F 0 "C86" H 1800 11500 50 0000 C CNN
F 1 "1uF" H 1800 11700 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 1800 11400 50 0001 C CNN
F 3 "" H 1800 11600 50 0001 C CNN
F 4 "GRM155R60J105KE19D" H 1800 11600 50 0001 C CNN "MPN"
F 5 "Murata" H 1800 11600 50 0001 C CNN "Manufacturer"
1 1800 11600
1 0 0 -1
$EndComp
Wire Wire Line
1100 11600 950 11600
Text GLabel 950 11600 2 30 BiDi ~ 0
ANT_BIAS_SEL
Wire Wire Line
2500 11600 2650 11600
Text GLabel 2650 11600 0 30 BiDi ~ 0
GND
$Comp
L BOARD_C87 C87
U 1 1 6502000E
P 1800 12400
F 0 "C87" H 1800 12300 50 0000 C CNN
F 1 "1uF" H 1800 12500 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 1800 12200 50 0001 C CNN
F 3 "" H 1800 12400 50 0001 C CNN
F 4 "GRM155R60J105KE19D" H 1800 12400 50 0001 C CNN "MPN"
F 5 "Murata" H 1800 12400 50 0001 C CNN "Manufacturer"
1 1800 12400
1 0 0 -1
$EndComp
Wire Wire Line
1100 12400 950 12400
Text GLabel 950 12400 2 30 BiDi ~ 0
ANT_BIAS_SW
Wire Wire Line
2500 12400 2650 12400
Text GLabel 2650 12400 0 30 BiDi ~ 0
GND
$Comp
L BOARD_L4 L4
U 1 1 6502000F
P 1800 13200
F 0 "L4" H 1800 13100 50 0000 C CNN
F 1 "56nH" H 1800 13300 50 0000 C CNN
F 2 "Inductor_SMD:L_0402_1005Metric" H 1800 13000 50 0001 C CNN
F 3 "" H 1800 13200 50 0001 C CNN
F 4 "0402HPH-56NXJRW" H 1800 13200 50 0001 C CNN "MPN"
F 5 "Coilcraft" H 1800 13200 50 0001 C CNN "Manufacturer"
1 1800 13200
1 0 0 -1
$EndComp
Wire Wire Line
1100 13200 950 13200
Text GLabel 950 13200 2 30 BiDi ~ 0
ANT_BIAS_SW
Wire Wire Line
2500 13200 2650 13200
Text GLabel 2650 13200 0 30 BiDi ~ 0
RF_SMA
$Comp
L BOARD_TP3 TP3
U 1 1 65020010
P 1800 14000
F 0 "TP3" H 1800 13900 50 0000 C CNN
F 1 "ANT OC" H 1800 14100 50 0000 C CNN
F 2 "TestPoint:TestPoint_Pad_D1.0mm" H 1800 13800 50 0001 C CNN
F 3 "" H 1800 14000 50 0001 C CNN
F 4 "" H 1800 14000 50 0001 C CNN "MPN"
F 5 "" H 1800 14000 50 0001 C CNN "Manufacturer"
1 1800 14000
1 0 0 -1
$EndComp
Wire Wire Line
1100 14000 950 14000
Text GLabel 950 14000 2 30 BiDi ~ 0
ANT_BIAS_OC
$Comp
L BOARD_U21 U21
U 1 1 65020011
P 1800 14800
F 0 "U21" H 1800 14700 50 0000 C CNN
F 1 "MAX2771" H 1800 14900 50 0000 C CNN
F 2 "Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.25x3.25mm" H 1800 14600 50 0001 C CNN
F 3 "" H 1800 14800 50 0001 C CNN
F 4 "MAX2771ETI+" H 1800 14800 50 0001 C CNN "MPN"
F 5 "Analog Devices" H 1800 14800 50 0001 C CNN "Manufacturer"
1 1800 14800
1 0 0 -1
$EndComp
Wire Wire Line
1100 15500 950 15500
Text GLabel 950 15500 2 30 BiDi ~ 0
MAX_CPOUT
Wire Wire Line
2500 15450 2650 15450
Text GLabel 2650 15450 0 30 BiDi ~ 0
VCC3V0_RF
Wire Wire Line
1100 15400 950 15400
Text GLabel 950 15400 2 30 BiDi ~ 0
MAX_XTAL
Wire Wire Line
2500 15350 2650 15350
Text GLabel 2650 15350 0 30 BiDi ~ 0
MAX_CLKOUT_SRC
Wire Wire Line
1100 15300 950 15300
Text GLabel 950 15300 2 30 BiDi ~ 0
MAX_ADC_CLKIN
Wire Wire Line
2500 15250 2650 15250
Text GLabel 2650 15250 0 30 BiDi ~ 0
VCC3V0_DIG
Wire Wire Line
1100 15200 950 15200
Text GLabel 950 15200 2 30 BiDi ~ 0
MAX_SDATA_DEV
Wire Wire Line
2500 15150 2650 15150
Text GLabel 2650 15150 0 30 BiDi ~ 0
MAX_SCLK_DEV
Wire Wire Line
1100 15100 950 15100
Text GLabel 950 15100 2 30 BiDi ~ 0
MAX_CSN_DEV
Wire Wire Line
2500 15050 2650 15050
Text GLabel 2650 15050 0 30 BiDi ~ 0
MAX_Q1_DEV
Wire Wire Line
1100 15000 950 15000
Text GLabel 950 15000 2 30 BiDi ~ 0
MAX_Q0_DEV
Wire Wire Line
2500 14950 2650 14950
Text GLabel 2650 14950 0 30 BiDi ~ 0
MAX_I0_DEV
Wire Wire Line
1100 14900 950 14900
Text GLabel 950 14900 2 30 BiDi ~ 0
MAX_I1_DEV
Wire Wire Line
2500 14850 2650 14850
Text GLabel 2650 14850 0 30 BiDi ~ 0
VCC3V0_DIG
NoConn ~ 1100 14800
NoConn ~ 2500 14750
Wire Wire Line
1100 14700 950 14700
Text GLabel 950 14700 2 30 BiDi ~ 0
MAX_LD_DEV
Wire Wire Line
2500 14650 2650 14650
Text GLabel 2650 14650 0 30 BiDi ~ 0
MAX_SHDN_DEV
NoConn ~ 1100 14600
NoConn ~ 2500 14550
NoConn ~ 1100 14500
Wire Wire Line
2500 14450 2650 14450
Text GLabel 2650 14450 0 30 BiDi ~ 0
VCC3V0_RF
NoConn ~ 1100 14400
NoConn ~ 2500 14350
Wire Wire Line
1100 14300 950 14300
Text GLabel 950 14300 2 30 BiDi ~ 0
MAX_MIXIN_HI
NoConn ~ 2500 14250
Wire Wire Line
1100 14200 950 14200
Text GLabel 950 14200 2 30 BiDi ~ 0
VCC3V0_RF
Wire Wire Line
2500 14150 2650 14150
Text GLabel 2650 14150 0 30 BiDi ~ 0
VCC3V0_RF
Wire Wire Line
1100 14100 950 14100
Text GLabel 950 14100 2 30 BiDi ~ 0
GND
$Comp
L BOARD_C88 C88
U 1 1 65020012
P 1800 16900
F 0 "C88" H 1800 16800 50 0000 C CNN
F 1 "15pF" H 1800 17000 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 1800 16700 50 0001 C CNN
F 3 "" H 1800 16900 50 0001 C CNN
F 4 "GRM1555C1H150JA01D" H 1800 16900 50 0001 C CNN "MPN"
F 5 "Murata" H 1800 16900 50 0001 C CNN "Manufacturer"
1 1800 16900
1 0 0 -1
$EndComp
Wire Wire Line
1100 16900 950 16900
Text GLabel 950 16900 2 30 BiDi ~ 0
MAX_CPOUT
Wire Wire Line
2500 16900 2650 16900
Text GLabel 2650 16900 0 30 BiDi ~ 0
GND
$Comp
L BOARD_R43 R43
U 1 1 65020013
P 1800 17700
F 0 "R43" H 1800 17600 50 0000 C CNN
F 1 "15K" H 1800 17800 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 17500 50 0001 C CNN
F 3 "" H 1800 17700 50 0001 C CNN
F 4 "RC0402FR-0715KL" H 1800 17700 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 17700 50 0001 C CNN "Manufacturer"
1 1800 17700
1 0 0 -1
$EndComp
Wire Wire Line
1100 17700 950 17700
Text GLabel 950 17700 2 30 BiDi ~ 0
MAX_CPOUT
Wire Wire Line
2500 17700 2650 17700
Text GLabel 2650 17700 0 30 BiDi ~ 0
MAX_LOOP_RC
$Comp
L BOARD_C89 C89
U 1 1 65020014
P 1800 18500
F 0 "C89" H 1800 18400 50 0000 C CNN
F 1 "750pF" H 1800 18600 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 1800 18300 50 0001 C CNN
F 3 "" H 1800 18500 50 0001 C CNN
F 4 "GRM1555C1H751JA01D" H 1800 18500 50 0001 C CNN "MPN"
F 5 "Murata" H 1800 18500 50 0001 C CNN "Manufacturer"
1 1800 18500
1 0 0 -1
$EndComp
Wire Wire Line
1100 18500 950 18500
Text GLabel 950 18500 2 30 BiDi ~ 0
MAX_LOOP_RC
Wire Wire Line
2500 18500 2650 18500
Text GLabel 2650 18500 0 30 BiDi ~ 0
GND
$Comp
L BOARD_C90 C90
U 1 1 65020015
P 1800 19300
F 0 "C90" H 1800 19200 50 0000 C CNN
F 1 "10nF" H 1800 19400 50 0000 C CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 1800 19100 50 0001 C CNN
F 3 "" H 1800 19300 50 0001 C CNN
F 4 "GRM155R71H103KA88D" H 1800 19300 50 0001 C CNN "MPN"
F 5 "Murata" H 1800 19300 50 0001 C CNN "Manufacturer"
1 1800 19300
1 0 0 -1
$EndComp
Wire Wire Line
1100 19300 950 19300
Text GLabel 950 19300 2 30 BiDi ~ 0
TCXO16_OUT
Wire Wire Line
2500 19300 2650 19300
Text GLabel 2650 19300 0 30 BiDi ~ 0
MAX_XTAL
$Comp
L BOARD_R44 R44
U 1 1 65020016
P 1800 20100
F 0 "R44" H 1800 20000 50 0000 C CNN
F 1 "33R" H 1800 20200 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 19900 50 0001 C CNN
F 3 "" H 1800 20100 50 0001 C CNN
F 4 "RC0402FR-0733RL" H 1800 20100 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 20100 50 0001 C CNN "Manufacturer"
1 1800 20100
1 0 0 -1
$EndComp
Wire Wire Line
1100 20100 950 20100
Text GLabel 950 20100 2 30 BiDi ~ 0
OSC40_OUT
Wire Wire Line
2500 20100 2650 20100
Text GLabel 2650 20100 0 30 BiDi ~ 0
MAX_ADC_CLKIN
$Comp
L BOARD_R45 R45
U 1 1 65020017
P 1800 20900
F 0 "R45" H 1800 20800 50 0000 C CNN
F 1 "22R" H 1800 21000 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 20700 50 0001 C CNN
F 3 "" H 1800 20900 50 0001 C CNN
F 4 "RC0402FR-0722RL" H 1800 20900 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 20900 50 0001 C CNN "Manufacturer"
1 1800 20900
1 0 0 -1
$EndComp
Wire Wire Line
1100 20900 950 20900
Text GLabel 950 20900 2 30 BiDi ~ 0
MAX_CLKOUT_SRC
Wire Wire Line
2500 20900 2650 20900
Text GLabel 2650 20900 0 30 BiDi ~ 0
MAX_CLKOUT
$Comp
L BOARD_R46 R46
U 1 1 65020018
P 1800 21700
F 0 "R46" H 1800 21600 50 0000 C CNN
F 1 "22R" H 1800 21800 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 21500 50 0001 C CNN
F 3 "" H 1800 21700 50 0001 C CNN
F 4 "RC0402FR-0722RL" H 1800 21700 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 21700 50 0001 C CNN "Manufacturer"
1 1800 21700
1 0 0 -1
$EndComp
Wire Wire Line
1100 21700 950 21700
Text GLabel 950 21700 2 30 BiDi ~ 0
MAX_I0_DEV
Wire Wire Line
2500 21700 2650 21700
Text GLabel 2650 21700 0 30 BiDi ~ 0
MAX_I0
$Comp
L BOARD_R47 R47
U 1 1 65020019
P 1800 22500
F 0 "R47" H 1800 22400 50 0000 C CNN
F 1 "22R" H 1800 22600 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 22300 50 0001 C CNN
F 3 "" H 1800 22500 50 0001 C CNN
F 4 "RC0402FR-0722RL" H 1800 22500 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 22500 50 0001 C CNN "Manufacturer"
1 1800 22500
1 0 0 -1
$EndComp
Wire Wire Line
1100 22500 950 22500
Text GLabel 950 22500 2 30 BiDi ~ 0
MAX_I1_DEV
Wire Wire Line
2500 22500 2650 22500
Text GLabel 2650 22500 0 30 BiDi ~ 0
MAX_I1
$Comp
L BOARD_R48 R48
U 1 1 6502001A
P 1800 23300
F 0 "R48" H 1800 23200 50 0000 C CNN
F 1 "22R" H 1800 23400 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 23100 50 0001 C CNN
F 3 "" H 1800 23300 50 0001 C CNN
F 4 "RC0402FR-0722RL" H 1800 23300 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 23300 50 0001 C CNN "Manufacturer"
1 1800 23300
1 0 0 -1
$EndComp
Wire Wire Line
1100 23300 950 23300
Text GLabel 950 23300 2 30 BiDi ~ 0
MAX_Q0_DEV
Wire Wire Line
2500 23300 2650 23300
Text GLabel 2650 23300 0 30 BiDi ~ 0
MAX_Q0
$Comp
L BOARD_R49 R49
U 1 1 6502001B
P 1800 24100
F 0 "R49" H 1800 24000 50 0000 C CNN
F 1 "22R" H 1800 24200 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 23900 50 0001 C CNN
F 3 "" H 1800 24100 50 0001 C CNN
F 4 "RC0402FR-0722RL" H 1800 24100 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 24100 50 0001 C CNN "Manufacturer"
1 1800 24100
1 0 0 -1
$EndComp
Wire Wire Line
1100 24100 950 24100
Text GLabel 950 24100 2 30 BiDi ~ 0
MAX_Q1_DEV
Wire Wire Line
2500 24100 2650 24100
Text GLabel 2650 24100 0 30 BiDi ~ 0
MAX_Q1
$Comp
L BOARD_R50 R50
U 1 1 6502001C
P 1800 24900
F 0 "R50" H 1800 24800 50 0000 C CNN
F 1 "22R" H 1800 25000 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 24700 50 0001 C CNN
F 3 "" H 1800 24900 50 0001 C CNN
F 4 "RC0402FR-0722RL" H 1800 24900 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 24900 50 0001 C CNN "Manufacturer"
1 1800 24900
1 0 0 -1
$EndComp
Wire Wire Line
1100 24900 950 24900
Text GLabel 950 24900 2 30 BiDi ~ 0
MAX_LD_DEV
Wire Wire Line
2500 24900 2650 24900
Text GLabel 2650 24900 0 30 BiDi ~ 0
MAX_LD
$Comp
L BOARD_R51 R51
U 1 1 6502001D
P 1800 25700
F 0 "R51" H 1800 25600 50 0000 C CNN
F 1 "22R" H 1800 25800 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 25500 50 0001 C CNN
F 3 "" H 1800 25700 50 0001 C CNN
F 4 "RC0402FR-0722RL" H 1800 25700 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 25700 50 0001 C CNN "Manufacturer"
1 1800 25700
1 0 0 -1
$EndComp
Wire Wire Line
1100 25700 950 25700
Text GLabel 950 25700 2 30 BiDi ~ 0
MAX_SCLK
Wire Wire Line
2500 25700 2650 25700
Text GLabel 2650 25700 0 30 BiDi ~ 0
MAX_SCLK_DEV
$Comp
L BOARD_R52 R52
U 1 1 6502001E
P 1800 26500
F 0 "R52" H 1800 26400 50 0000 C CNN
F 1 "22R" H 1800 26600 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 26300 50 0001 C CNN
F 3 "" H 1800 26500 50 0001 C CNN
F 4 "RC0402FR-0722RL" H 1800 26500 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 26500 50 0001 C CNN "Manufacturer"
1 1800 26500
1 0 0 -1
$EndComp
Wire Wire Line
1100 26500 950 26500
Text GLabel 950 26500 2 30 BiDi ~ 0
MAX_CSN
Wire Wire Line
2500 26500 2650 26500
Text GLabel 2650 26500 0 30 BiDi ~ 0
MAX_CSN_DEV
$Comp
L BOARD_R53 R53
U 1 1 6502001F
P 1800 27300
F 0 "R53" H 1800 27200 50 0000 C CNN
F 1 "22R" H 1800 27400 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 27100 50 0001 C CNN
F 3 "" H 1800 27300 50 0001 C CNN
F 4 "RC0402FR-0722RL" H 1800 27300 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 27300 50 0001 C CNN "Manufacturer"
1 1800 27300
1 0 0 -1
$EndComp
Wire Wire Line
1100 27300 950 27300
Text GLabel 950 27300 2 30 BiDi ~ 0
MAX_SDATA
Wire Wire Line
2500 27300 2650 27300
Text GLabel 2650 27300 0 30 BiDi ~ 0
MAX_SDATA_DEV
$Comp
L BOARD_R54 R54
U 1 1 65020020
P 1800 28100
F 0 "R54" H 1800 28000 50 0000 C CNN
F 1 "22R" H 1800 28200 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 27900 50 0001 C CNN
F 3 "" H 1800 28100 50 0001 C CNN
F 4 "RC0402FR-0722RL" H 1800 28100 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 28100 50 0001 C CNN "Manufacturer"
1 1800 28100
1 0 0 -1
$EndComp
Wire Wire Line
1100 28100 950 28100
Text GLabel 950 28100 2 30 BiDi ~ 0
MAX_SHDN
Wire Wire Line
2500 28100 2650 28100
Text GLabel 2650 28100 0 30 BiDi ~ 0
MAX_SHDN_DEV
$Comp
L BOARD_R55 R55
U 1 1 65020021
P 1800 28900
F 0 "R55" H 1800 28800 50 0000 C CNN
F 1 "100K" H 1800 29000 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 28700 50 0001 C CNN
F 3 "" H 1800 28900 50 0001 C CNN
F 4 "RC0402FR-07100KL" H 1800 28900 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 28900 50 0001 C CNN "Manufacturer"
1 1800 28900
1 0 0 -1
$EndComp
Wire Wire Line
1100 28900 950 28900
Text GLabel 950 28900 2 30 BiDi ~ 0
MAX_SHDN_DEV
Wire Wire Line
2500 28900 2650 28900
Text GLabel 2650 28900 0 30 BiDi ~ 0
GND
$Comp
L BOARD_U23 U23
U 1 1 65020022
P 1800 29700
F 0 "U23" H 1800 29600 50 0000 C CNN
F 1 "16.368 MHz TCXO" H 1800 29800 50 0000 C CNN
F 2 "board:Epson_TG2016SMN" H 1800 29500 50 0001 C CNN
F 3 "" H 1800 29700 50 0001 C CNN
F 4 "X1G005441030125" H 1800 29700 50 0001 C CNN "MPN"
F 5 "Epson" H 1800 29700 50 0001 C CNN "Manufacturer"
1 1800 29700
1 0 0 -1
$EndComp
NoConn ~ 1100 29750
Wire Wire Line
2500 29750 2650 29750
Text GLabel 2650 29750 0 30 BiDi ~ 0
GND
Wire Wire Line
1100 29650 950 29650
Text GLabel 950 29650 2 30 BiDi ~ 0
TCXO16_OUT
Wire Wire Line
2500 29650 2650 29650
Text GLabel 2650 29650 0 30 BiDi ~ 0
VCC3V0_CLK
$Comp
L BOARD_U24 U24
U 1 1 65020023
P 1800 30500
F 0 "U24" H 1800 30400 50 0000 C CNN
F 1 "40.000 MHz XO" H 1800 30600 50 0000 C CNN
F 2 "Oscillator:Oscillator_SMD_SeikoEpson_SG210-4Pin_2.5x2.0mm" H 1800 30300 50 0001 C CNN
F 3 "" H 1800 30500 50 0001 C CNN
F 4 "X1G004171041100" H 1800 30500 50 0001 C CNN "MPN"
F 5 "Epson" H 1800 30500 50 0001 C CNN "Manufacturer"
1 1800 30500
1 0 0 -1
$EndComp
Wire Wire Line
1100 30550 950 30550
Text GLabel 950 30550 2 30 BiDi ~ 0
VCC3V0_CLK
Wire Wire Line
2500 30550 2650 30550
Text GLabel 2650 30550 0 30 BiDi ~ 0
GND
Wire Wire Line
1100 30450 950 30450
Text GLabel 950 30450 2 30 BiDi ~ 0
OSC40_OUT
Wire Wire Line
2500 30450 2650 30450
Text GLabel 2650 30450 0 30 BiDi ~ 0
VCC3V0_CLK
$Comp
L BOARD_R56 R56
U 1 1 65020024
P 1800 31300
F 0 "R56" H 1800 31200 50 0000 C CNN
F 1 "33R" H 1800 31400 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 31100 50 0001 C CNN
F 3 "" H 1800 31300 50 0001 C CNN
F 4 "RC0402FR-0733RL" H 1800 31300 50 0001 C CNN "MPN"
F 5 "Yageo" H 1800 31300 50 0001 C CNN "Manufacturer"
1 1800 31300
1 0 0 -1
$EndComp
Wire Wire Line
1100 31300 950 31300
Text GLabel 950 31300 2 30 BiDi ~ 0
OSC40_OUT
Wire Wire Line
2500 31300 2650 31300
Text GLabel 2650 31300 0 30 BiDi ~ 0
CLK_40M_FPGA
$EndSCHEMATC
+4
View File
@@ -0,0 +1,4 @@
(sym_lib_table
(version 7)
(lib (name "board")(type "KiCad")(uri "${KIPRJMOD}/board.kicad_sym")(options "")(descr "Generated board symbols"))
)
File diff suppressed because it is too large Load Diff