Initial Ti375 GNSS IMU board design and documentation

2026-08-15 18:09:17 +03:00
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+*.csv text eol=lf
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+*.json text eol=lf
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+# Local tools and Python environments
+.tools/
+.venv/
+venv/
+__pycache__/
+*.py[cod]
+
+# KiCad local/editor state
+*.lck
+*.kicad_prl
+*-backups/
+*.bak
+
+# Local manufacturer documents; links and policy are in references/README.md
+references/official/
+
+# Stale/intermediate routed board variants
+hardware/board_prerouted.*
+hardware/board_plane_stitched.*
+hardware/board_power_routed.*
+hardware/board_routed.*
+
+# Routing/build workspace. Keep only the current review deliverables.
+outputs/*
+!outputs/README.md
+!outputs/bom.csv
+!outputs/jlcpcb_bom.csv
+!outputs/erc_final_reset.rpt
+!outputs/drc_final_placement.rpt
+!outputs/board_final_reset_top.png
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+# Ti375 GNSS / IMU FPGA Kartı
+
+Efinix Ti375C529 FPGA, MAX2771 GNSS alıcısı, Murata SCH16T-K01 IMU ve FT4232H
+USB debug arayüzünü tek kartta birleştiren 8 katmanlı KiCad 10 tasarımıdır.
+
+> Durum: Şema ve placement günceldir; kart henüz route edilmemiştir. Üretime
+> gönderilmeden önce routing, zone fill, final DRC ve üretim dosyası kontrolü
+> tamamlanmalıdır.
+
+![Güncel kart görünümü](outputs/board_final_reset_top.png)
+
+## Kartın özeti
+
+| Blok | İçerik |
+|---|---|
+| FPGA | Efinix Ti375C529, 0.8 mm pitch C529 BGA |
+| GNSS | MAX2771, GPS L1/L1C aktif anten girişi, 50 ohm CPWG RF hattı |
+| IMU | Murata SCH16T-K01, SafeSPI bağlantısı |
+| Debug | FT4232H üzerinden hard JTAG, RISC-V JTAG ve iki UART |
+| Genişleme | 4 adet Digilent 2x6 PMOD: 2 x 3.3 V, 2 x 1.8 V |
+| Konfigürasyon | 1.8 V QSPI flash, CDONE ve CRESET test noktaları |
+| Besleme | USB-C veya korumalı harici 5 V; sıralı 0.95/1.8/3.3/3.0 V rayları |
+| Mekanik | 155.1 x 90.0 mm, 8 katman, dört montaj deliği |
+
+## Yapılan temel tasarım kararları
+
+- Ti375 üzerindeki bütün kullanılabilir pinler konnektöre çıkarılmadı. Yalnızca
+  özel fonksiyonlardan arta kalan 32 GPIO dört PMOD üzerinde kullanıldı.
+- Büyük genel amaçlı header, jumper grubu ve ARM 10-pin hard-JTAG konnektörü
+  kaldırıldı. Gerekli bring-up sinyalleri 15 yerel test noktasına dağıtıldı.
+- FT4232H interface 0/A RISC-V JTAG'a, interface 1/B FPGA hard JTAG'a ayrıldı.
+  FPGA'ya giden debug çıkışları güç-domain izolasyonundan geçer.
+- Hard JTAG TCK, TMS, TDI ve TDO hatlarında FPGA tarafında 10 kohm pull-up
+  bulunur.
+- Harici reset için JST-SH konnektör, kart üstü buton, RC filtre ve ESD koruması
+  eklendi.
+- FTDI reset, harici reset ve power-fault istekleri CRESET_N üzerinde ayrı
+  açık-drenç sürücülerle birleşir. Aktif-düşük mantıkta bu yapı reset
+  isteklerinin OR'lanmasıdır; çıkış çatışması oluşturmaz.
+- Core, 1.8 V, 3.3 V, 3.0 V ve LM3880 sequence sonucu bağımsız olarak izlenir.
+  `ALL_FPGA_POWER_OK` geçerli olmadan CRESET_N bırakılmaz ve FPGA'ya giden FTDI
+  sürücüleri etkinleşmez.
+- RF ve USB hatları autorouter sonucuna bırakılmaz; son aşamada deterministik,
+  denetlenebilir geometriyle oluşturulur.
+
+## Güç ve reset akışı
+
+```text
+USB-C / EXT 5 V
+       |
+      SYS5
+       |
+   0.95 V core ---- CORE_PG
+                       |
+                    LM3880
+                       +---- 1.8 V ---- PG_1V8
+                       +---- 3.3 V ---- PG_3V3
+                       +---- FLAG3
+                                      |
+3.0 V DIG ---- TPS3808 (20 ms) -------+---- ALL_FPGA_POWER_OK
+                                                   |
+                              +--------------------+---- CRESET_N release
+                              +------------------------- FTDI buffer enable
+
+EXT_RESET_N ---- filtre/ESD ---- open drain --+
+FTDI BDBUS4 -------------------- open drain --+---- FPGA_CRESET_N
+power-valid -------------------- open drain --+
+```
+
+Kullanıcı veya FTDI reseti yalnızca CRESET_N'i etkiler; power-good durumunu
+bozmaz. Bu nedenle raylar sağlıklıyken FPGA reset altında tutulsa bile JTAG
+erişimi korunur.
+
+## Hızlı başlangıç
+
+KiCad 10 ve KiCad'in `pcbnew` modülünü içeren sistem Python'u gereklidir.
+
+```bash
+python3 -m pip install -r requirements.txt
+python3 scripts/generate_footprints.py
+python3 scripts/generate_kicad.py
+python3 scripts/generate_design_tables.py
+/usr/bin/python3 scripts/generate_pcb.py
+```
+
+Kontrol:
+
+```bash
+kicad-cli sch erc --severity-all \
+  -o outputs/erc_final_reset.rpt hardware/board.kicad_sch
+kicad-cli pcb drc --severity-all \
+  -o outputs/drc_final_placement.rpt hardware/board.kicad_pcb
+```
+
+Güncel placement kontrolünde ERC 0 ihlaldir. DRC'deki 12 `isolated_copper`
+uyarısı ve 499 açık bağlantı, kartın henüz route edilmemiş olmasından
+kaynaklanır; üretim öncesi kabul edilebilir final sonuç değildir.
+
+## Kaynakların önceliği
+
+1. `scripts/design_data.py`: komponentler, pinler ve bağlantılar için tek kaynak.
+2. `scripts/generate_pcb.py`: placement, stackup, zone ve fiziksel PCB kuralları.
+3. `scripts/generate_design_tables.py`: Ti375 pin politikası ve constraint tabloları.
+4. `hardware/board.kicad_sch` ve `hardware/board.kicad_pcb`: üretilmiş güncel KiCad dosyaları.
+5. `outputs/`: BOM, kontrol raporları ve inceleme görselleri.
+
+Elle yapılan değişiklikler tekrar üretimde kaybolabileceği için temel bağlantı
+ve placement kararları önce ilgili Python kaynağına işlenmelidir.
+
+## Ayrıntılı dokümanlar
+
+- [Donanım mimarisi ve pin kullanımı](hardware/README.md)
+- [Ana komponent seçimi ve güç/akım kapasiteleri](docs/COMPONENT_SELECTION.md)
+- [MAX2771, SCH16T, QSPI, FTDI ve test noktası bağlantıları](docs/INTERFACES.md)
+- [Ti375 ball, bank, gerilim ve PMOD pin seçimi](docs/FPGA_PINOUT.md)
+- [Ayrıntılı güç ağacı, sıralama ve reset davranışı](docs/POWER_TREE.md)
+- [Üretim, kontrol ve routing akışı](scripts/README.md)
+- [Pin tabloları ve türetilmiş veriler](docs/README.md)
+- [Güncel çıktılar ve raporların anlamı](outputs/README.md)
+- [Referans doküman politikası](references/README.md)
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+# Ana komponent seçimi ve kapasite sınırları
+
+Bu tablolardaki akım değerleri komponent datasheet kapasitesini veya tasarımda
+ayarlanan limiti gösterir. Kartın tamamının aynı anda bu değerleri verebildiği
+anlamına gelmez. Gerçek sürekli güç; 5 V kaynağı, power-path limiti, PCB bakırı,
+indüktör kaybı, ortam sıcaklığı ve termal ölçümle sınırlandırılır.
+
+## İşlem, RF, sensör ve debug komponentleri
+
+| Ref | Parça | Besleme / kapasite | Seçilme nedeni ve karttaki görevi |
+|---|---|---|---|
+| U1 | Efinix Ti375C529C3 | 0.95 V core; 1.8 V AUX/HSIO/config; 3.0/3.3 V HVIO | C529 paket, standart-power C3 core seçeneği. GNSS örnekleme, SafeSPI, QSPI, JTAG ve PMOD mantığını taşır. FPGA akımı HDL kullanımına bağlıdır; sabit bir tüketim değeri kabul edilmez, Efinity power estimator ile hesaplanmalıdır. |
+| U21 | MAX2771ETI+ | 2.7–3.3 V; datasheet varsayılan GNSS modunda yaklaşık 26–27 mA tipik | Tek çip GNSS RF/PLL/IF/ADC. Kartta 3.0 V analog ve dijital LDO'lardan beslenir; iki dahili LNA kapalı, SAW çıkışı doğrudan `MIXIN_HI` girişine gider. |
+| U22 | SCH16T-K01-1 | V3P3 3.0–3.6 V; VDDIO 1.7–3.6 V; 41 mA nominal, 47 mA maksimum | 6 eksen yüksek performanslı IMU. Tam parça varyantı K01-1; 3.3 V SafeSPI ve DRY/SYNC arayüzü kullanılır. |
+| U26 | IS25WP512M-JLLE | 1.8 V, 512 Mbit | Ti375 active-serial konfigürasyon belleği; x1/x2/x4 I/O pinleri doğrudan dedicated config ball'larına gider. |
+| U2 | FT4232H-56Q | 3.3 V I/O, dahili 1.8 V core regülatörü; USB 2.0 High-Speed | Tek USB üzerinden iki JTAG, iki UART ve bir debug GPIO sağlar. FPGA kapalıyken back-power olmaması için çıkışlar U29/U30 ile izole edilir. |
+| U3 | 93LC56BT-I/OT | 3.3 V, x16 organizasyon | FT4232H USB descriptor ve kanal modlarını kalıcı tutar. |
+| U5 | TUSB320LAI | 3.3 V AUX | USB-C UFP/sink rolü, CC1/CC2 üzerindeki entegre Rd ve Type-C akım ilanı algılama. USB'den ana ray yalnızca 3 A ilanı algılandığında etkinleşir. |
+| U6 | TPD2EUSB30A | USB2 düşük kapasitans ESD koruması | D+/D− hattını konektöre yakın korur; yüksek hızlı diferansiyel hattın yükünü düşük tutar. |
+| U23 | Epson TG2016SMN | 3.0 V; 16.368 MHz, ±0.5 ppm | MAX2771 PLL referansı. 10 nF ile MAX2771 XTAL girişine AC bağlanır. |
+| U24 | Epson SG-210STF | 3.0 V; 40.000 MHz, ±25 ppm | MAX2771 ADC sampling clock ve FPGA sistem/capture clockunun ortak kaynağı. İki ayrı 33 ohm source-series kol kullanılır. |
+| U25 | ECS-2520MV | 3.3 V; 12.000 MHz | FT4232H ana saat kaynağı. |
+| FL1 | SF14-1582M5UUS2 | 1565.19–1585.65 MHz; 1.2 dB tipik insertion loss | GPS L1/L1C ön seçim SAW filtresi. |
+| D1 | ESD501DPYR | Yaklaşık 0.3 pF, 12 V RF ESD elemanı | SMA girişini RF hattını fazla yüklemeden korur. |
+| L4 | 0402HPH-56NXJRW | 56 nH; 330 mA; SRF 2.1 GHz; Q yaklaşık 64 | 3.3/5 V aktif anten beslemesini SMA merkez iletkenine veren bias-tee choke. |
+
+## Güç giriş ve regülatör komponentleri
+
+| Ref | Parça | Datasheet / ayarlanan kapasite | Tasarımdaki kullanım |
+|---|---|---|---|
+| U7 | TPS259470A | 2.7–23 V eFuse, cihaz ailesi 5.5 A; RILM ile yaklaşık 2.69 A tipik | USB VBUS için UV≈4.0 V, OV≈5.8 V, current/inrush/reverse-current koruması. USB yolu 3 A Type-C sınırının altında tutulur. |
+| U8 | TPS259470A | 2.7–23 V eFuse; RILM ile yaklaşık 4.04 A tipik | Harici regüle 5 V girişi için aynı korumalar. |
+| U9 | TPS2121 | 2.8–22 V; 4.5 A ayarlanabilir limit; 56 mΩ tipik RON | USB ve harici 5 V arasında reverse-blocking power mux. Geçerli ve yakın gerilimlerde harici giriş önceliklidir. |
+| U12 | TPS7A2033 | 300 mA LDO | Supervisor, Type-C ve FTDI için her zaman açık `VCC3V3_AUX`. |
+| U13 | TPS6287B15 | 2.7–6 V giriş; 15 A sınıfı | Ti375 `VCC0V95` core/VCCA/VDD_SOC rayı. 100 nH, 30 A saturation sınıfı XEL4030 ve differential remote sense kullanır. |
+| U14 | TPS62867 | 2.4–5.5 V giriş; 6 A sınıfı | `VCC1V8` FPGA AUX/config/HSIO rayı. 240 nH, 6.6 A sınıfı indüktör. |
+| U15 | TPS62867 | 2.4–5.5 V giriş; 6 A sınıfı | `VCC3V3` FPGA HVIO/IMU/PMOD rayı. 240 nH, 6.6 A sınıfı indüktör. |
+| U16 | LM3880MF-1AA | 2.7–5.5 V; 1→2→3 ve ters kapanış sırası; yaklaşık 10 ms/kademe seçimi | Core PG geldikten sonra 1.8 V, 3.3 V ve final sequence flag üretir. Çıkışlar open-drain'dir. |
+| U17 | TPS7A2030 | 300 mA LDO | `VCC3V0_RF`: MAX2771 RF/PLL/IF/VCO analog beslemeleri. |
+| U18 | TPS7A2030 | 300 mA LDO | `VCC3V0_DIG`: MAX2771 dijital/ADC ve Ti375 3.0 V bankı. |
+| U19 | TPS7A2030 | 300 mA LDO | `VCC3V0_CLK`: 16.368 MHz TCXO ve 40 MHz XO. |
+| U20 | TPS7A2033 | 300 mA LDO | Aktif anten için temiz 3.3 V seçeneği. |
+| U27 | TPS22944 | Sabit 100 mA current limit | J5 ile seçilen 3.3 V veya 5 V anten biasını sınırlar; `ANT_BIAS_OC` fault çıkışı vardır. |
+| U28 | TPS3808G30 | VDD 1.7–6.5 V; 3.0 V nominal için 2.79 V threshold; CT açıkken 20 ms | Son oluşan 3.0 V FPGA bankını izler ve reset bırakma gecikmesini sağlar. |
+
+## Mantık ve power-domain elemanları
+
+| Ref | Parça | Besleme | Görev |
+|---|---|---|---|
+| U10 | SN74LVC2G02 | 3.3 V AUX | TUSB320'nin 3 A ilanını decode eder ve mux statusunu tersler. |
+| U11 | SN74LVC1G32 | 3.3 V AUX | Geçerli USB 3 A veya seçilmiş harici 5 V koşulundan `MAIN_EN` üretir. |
+| U29 | SN74LVC244A | FPGA 3.3 V | FTDI'den FPGA'ya JTAG/UART çıkış bufferı; Ioff ve ortak aktif-düşük OE. |
+| U30 | SN74LVC1G125 | FPGA 3.3 V | Channel-D debug GPIO için tri-state Ioff buffer. |
+| U31 | SN74LVC1G07 | 3.3 V AUX | FTDI reset isteğini CRESET_N'e açık-drenç aktarır. |
+| U32 | SN74LVC1G07 | 3.3 V AUX | All-power-valid sonucunu CRESET_N'e açık-drenç aktarır. |
+| U33 | SN74LVC1G07 | 1.8 V | Harici/manual reseti 1.8 V CRESET domainine açık-drenç aktarır. |
+| U34 | SN74LVC08A | 3.3 V AUX | Core/1.8/3.3/3.0/sequence valid sinyallerinin dört kapılı AND ağacı. |
+| Q1 | MMBT3904 | Ayrık transistor | `ALL_FPGA_POWER_OK` geçerliyken aktif-düşük FTDI buffer OE üretir. |
+
+## Güç kapasitesi nasıl okunmalı?
+
+- USB girişinde kullanılabilir sürekli akım U7 ayarı ve gerçek Type-C kaynak
+  ilanıyla sınırlıdır; konektörden rastgele 3 A çekildiği varsayılmaz.
+- Harici girişte U8 yaklaşık 4.04 A, U9 ise 4.5 A ayarlıdır; dolayısıyla nominal
+  üst sınır eFuse tarafıdır.
+- 15 A ve 6 A converter değerleri silikon sınıfıdır. Aynı anda maksimum core,
+  1.8 V ve 3.3 V gücü talep etmek 5 V giriş bütçesini aşabilir.
+- PMOD besleme pinleri ayrı current-limit içermez ve ilgili FPGA rayını paylaşır.
+  Takılan modüllerin toplam akımı güç/termal bütçeye dahil edilmelidir.
+- LDO'larda 300 mA elektriksel sınıra yaklaşmadan önce `(VIN−VOUT) × IOUT`
+  paket kaybı ve bakır alanı kontrol edilmelidir.
@@ -0,0 +1,123 @@
+# Ti375 FPGA pin seçimi
+
+Kesin ve makine tarafından doğrulanan kaynak `ti375_pinout.csv` dosyasıdır.
+Bu özet HDL tarafında kullanılacak sinyal adlarını, C529 ball'larını ve bank
+gerilimlerini okunabilir biçimde gösterir.
+
+## Sabit fonksiyonlar
+
+| Sinyal | Ball | Bank | Gerilim | Yön | Bağlantı |
+|---|---|---|---|---|---|
+| `HARD_TCK` | G10 | BR3/BR4 | 3.3 V | input | FT4232H BDBUS0 |
+| `HARD_TMS` | G12 | BR3/BR4 | 3.3 V | input | FT4232H BDBUS3 |
+| `HARD_TDI` | G9 | BR3/BR4 | 3.3 V | input | FT4232H BDBUS1 |
+| `HARD_TDO` | G13 | BR3/BR4 | 3.3 V | output | FT4232H BDBUS2 |
+| `FPGA_CRESET_N` | F9 | 4A/4B | 1.8 V | input | Power/FTDI/external reset fan-in |
+| `FPGA_CDONE` | F8 | 4A/4B | 1.8 V | output | TP14 ve 10k pull-up |
+| `QSPI_CS_N` | A7 | 4A/4B | 1.8 V | output | Flash CS_N |
+| `QSPI_IO3` | B7 | 4A/4B | 1.8 V | bidirectional | Flash IO3/HOLD_N |
+| `QSPI_IO2` | G5 | 4A/4B | 1.8 V | bidirectional | Flash IO2/WP_N |
+| `QSPI_SCLK` | G6 | 4A/4B | 1.8 V | output | Flash CCK |
+| `QSPI_IO0` | H4 | 4A/4B | 1.8 V | bidirectional | Flash IO0 |
+| `QSPI_IO1` | H5 | 4A/4B | 1.8 V | bidirectional | Flash IO1 |
+| `FPGA_TEST_N` | J2 | 4C | 1.8 V | input | 10k pull-up |
+| `FPGA_CSI` | J5 | 4A/4B | 1.8 V | input | 10k pull-up |
+
+## MAX2771
+
+| Sinyal | Ball | Bank | Gerilim | Yön |
+|---|---|---|---|---|
+| `MAX_CLKOUT` | B11 | BR0 | 3.0 V | input |
+| `MAX_I0` | D10 | BR0 | 3.0 V | input |
+| `MAX_I1` | D11 | BR0 | 3.0 V | input |
+| `MAX_Q0` | E10 | BR0 | 3.0 V | input |
+| `MAX_Q1` | E11 | BR0 | 3.0 V | input |
+| `MAX_LD` | F11 | BR0 | 3.0 V | input |
+| `MAX_SCLK` | F16 | TR0 | 3.0 V | output |
+| `MAX_CSN` | F17 | TR0 | 3.0 V | output |
+| `MAX_SDATA` | G16 | TR0 | 3.0 V | bidirectional |
+| `MAX_SHDN` | G17 | TR0 | 3.0 V | output |
+
+## SCH16T-K01
+
+| Sinyal | Ball | Bank | Gerilim | Yön |
+|---|---|---|---|---|
+| `IMU_SCK` | A8 | BR3/BR4 | 3.3 V | output |
+| `IMU_MOSI` | A9 | BR3/BR4 | 3.3 V | output |
+| `IMU_MISO` | B9 | BR3/BR4 | 3.3 V | input |
+| `IMU_CS` | B10 | BR3/BR4 | 3.3 V | output |
+| `IMU_DRY_SYNC` | A11 | TR1 | 3.3 V | bidirectional |
+| `IMU_EXTRESN` | C10 | BR3/BR4 | 3.3 V | output |
+
+## Saat ve USB debug
+
+| Sinyal | Ball | Gerilim | Yön | İşlev |
+|---|---|---|---|---|
+| `CLK_40M_FPGA` | U17 | 3.3 V | input | Clock-capable sistem/ADC saati |
+| `RISCV_TCK` | F12 | 3.3 V | input | FTDI interface A |
+| `RISCV_TDI` | V19 | 3.3 V | input | FTDI interface A |
+| `RISCV_TMS` | P18 | 3.3 V | input | FTDI interface A |
+| `RISCV_TDO` | T18 | 3.3 V | output | FTDI interface A |
+| `UART0_RX` | P17 | 3.3 V | input | FTDI channel C TX |
+| `UART0_TX` | R17 | 3.3 V | output | FTDI channel C RX |
+| `UART1_RX` | R18 | 3.3 V | input | FTDI channel D TX |
+| `UART1_TX` | T19 | 3.3 V | output | FTDI channel D RX |
+| `FTDI_DBG_GPIO` | U19 | 3.3 V | bidirectional | FTDI channel D debug |
+
+## 3.3 V PMOD pinleri
+
+| PMOD | Pin | FPGA ball | Bank |
+|---|---:|---|---|
+| JPMOD1 | 1 | U6 | BL2/BL3 |
+| JPMOD1 | 2 | V4 | BL2/BL3 |
+| JPMOD1 | 3 | A13 | TR1 |
+| JPMOD1 | 4 | C9 | BR3/BR4 |
+| JPMOD1 | 7 | C12 | TR1 |
+| JPMOD1 | 8 | C13 | TR1 |
+| JPMOD1 | 9 | C14 | TR1 |
+| JPMOD1 | 10 | D12 | TR1 |
+| JPMOD2 | 1 | V20 | TL1/TL5 |
+| JPMOD2 | 2 | D13 | TR2 |
+| JPMOD2 | 3 | E13 | TR2 |
+| JPMOD2 | 4 | E14 | TR2 |
+| JPMOD2 | 7 | E16 | TR2 |
+| JPMOD2 | 8 | F13 | TR2 |
+| JPMOD2 | 9 | E15 | TR2 |
+| JPMOD2 | 10 | F14 | TR2 |
+
+## 1.8 V PMOD pinleri
+
+1.8 V konnektörler Ti375 2E HSIO bankındaki düz diferansiyel çiftleri kullanır.
+Bu pinlerde config, PLL input/feedback veya dedicated clock görevi seçilmemiştir.
+Konnektör tek uçlu GPIO olarak kullanılabilir; kullanıcı HDL'i I/O standardını
+1.8 V seçmelidir.
+
+| PMOD | Pin | FPGA ball | HSIO çifti |
+|---|---:|---|---|
+| JPMOD3 | 1 | C20 | 51 P |
+| JPMOD3 | 2 | B20 | 51 N |
+| JPMOD3 | 3 | C17 | 52 P |
+| JPMOD3 | 4 | B17 | 52 N |
+| JPMOD3 | 7 | A16 | 53 P |
+| JPMOD3 | 8 | A17 | 53 N |
+| JPMOD3 | 9 | C19 | 54 P |
+| JPMOD3 | 10 | B19 | 54 N |
+| JPMOD4 | 1 | B14 | 55 P |
+| JPMOD4 | 2 | A14 | 55 N |
+| JPMOD4 | 3 | J18 | 56 P |
+| JPMOD4 | 4 | H18 | 56 N |
+| JPMOD4 | 7 | A18 | 57 P |
+| JPMOD4 | 8 | A19 | 57 N |
+| JPMOD4 | 9 | D16 | 58 P |
+| JPMOD4 | 10 | D17 | 58 N |
+
+Her Digilent 2x6 konnektörde pin 5/11 GND, pin 6/12 ilgili beslemedir.
+Konnektörler 5 V toleranslı değildir.
+
+## Neden diğer GPIO'lar dışarı çıkarılmadı?
+
+C529 paketindeki ball sayısı kullanıcı GPIO sayısı değildir. Paket; çok sayıda
+GND, core/AUX/VCCIO beslemesi, reference resistor, konfigürasyon, JTAG ve özel
+işlev ball'ı içerir. Tasarım yalnızca 32 PMOD GPIO'yu dışarı çıkarır. Geri kalan
+fabric GPIO'ların kullanıldı/boş durumu `unused_gpio_inventory.csv` dosyasında
+tek tek bulunur.
@@ -0,0 +1,175 @@
+# Arayüzler ve net bağlantıları
+
+Bu dokümanda ok yönü veri akışını gösterir. Parantez içindeki değer seri
+sonlandırma veya bias elemanıdır.
+
+## MAX2771 RF zinciri
+
+```text
+J2 SMA merkez
+  -> RF_SMA
+  -> D1 ESD501 (şönt ESD)
+  -> C83 27 pF DC block
+  -> RF_PRE_SAW
+  -> FL1 SF14-1582M5UUS2 GPS L1/L1C SAW
+  -> RF_POST_SAW
+  -> R39 0 ohm tuning link
+  -> MAX_MIXIN_HI
+  -> U21 pin 25 MIXIN_HI
+```
+
+`C84` (`RF_POST_SAW`-GND) ve `C85` (`MAX_MIXIN_HI`-GND) tuning şönt
+footprintleridir ve varsayılan olarak DNP'dir. Böylece VNA ölçümünden sonra
+pi-match kurulabilir. MAX2771'in LNAIN_HI/LNAIN_LO ve LNA çıkışları bağlı
+değildir; register 0 her iki LNA'yı kapatır ve yüksek-band mixer girişi seçilir.
+
+Aktif anten bias yolu:
+
+```text
+J5 pin 1 = temiz 3.3 V
+J5 pin 2 = ANT_BIAS_SEL
+J5 pin 3 = SYS5
+
+şönt 1-2 -> 3.3 V bias
+şönt 2-3 -> 5 V bias
+şönt yok -> OFF
+
+ANT_BIAS_SEL -> U27 TPS22944, 100 mA limit
+             -> ANT_BIAS_SW -> L4 56 nH -> RF_SMA -> anten
+```
+
+`TP3 ANT OC`, U27'nin aktif-düşük over-current göstergesidir. Bias devresi
+RF hattına L4 üzerinden girer; RF sinyali güç rayına taşınmamalıdır.
+
+## MAX2771 saat, SPI ve ADC arayüzü
+
+Saat ağacı:
+
+```text
+U23 16.368 MHz TCXO -> C90 10 nF -> U21 pin 3 XTAL
+
+U24 40.000 MHz XO --+-> R44 33R -> U21 pin 5 ADC_CLKIN
+                    +-> R56 33R -> U1 ball U17 CLK_40M_FPGA
+
+U21 pin 4 CLKOUT -> R45 22R -> U1 ball B11 MAX_CLKOUT
+```
+
+`MAX_CLKOUT`, ADC örnekleme saatinin FPGA'ya source-synchronous kopyasıdır.
+FPGA veri yakalama mantığı I/Q bitlerini bu saatle örneklemelidir.
+
+Üç telli kontrol arayüzü:
+
+| İşlev | FPGA | Seri eleman | MAX2771 |
+|---|---|---|---|
+| SCLK | U1 F16 `MAX_SCLK`, output, 3.0 V | R51 22R | U21 pin 8 `SCLK` |
+| CS_N | U1 F17 `MAX_CSN`, output, 3.0 V | R52 22R | U21 pin 9 `CSN` |
+| SDATA | U1 G16 `MAX_SDATA`, bidirectional, 3.0 V | R53 22R | U21 pin 7 `SDATA` |
+| Shutdown | U1 G17 `MAX_SHDN`, output, 3.0 V | R54 22R | U21 pin 18 `SHDN` |
+
+SDATA ayrı MOSI/MISO değildir; MAX2771'in tek bidirectional üç telli veri
+hattıdır. `R55=100 kohm`, MAX2771 tarafındaki SHDN pinini FPGA konfigüre olana
+kadar düşük tutar.
+
+ADC/status çıkışları:
+
+| MAX2771 pini | Seri eleman | FPGA ball/net | Yön |
+|---|---|---|---|
+| pin 10 Q1 | R49 22R | E11 `MAX_Q1` | MAX2771 -> FPGA |
+| pin 11 Q0 | R48 22R | E10 `MAX_Q0` | MAX2771 -> FPGA |
+| pin 12 I0 | R46 22R | D10 `MAX_I0` | MAX2771 -> FPGA |
+| pin 13 I1 | R47 22R | D11 `MAX_I1` | MAX2771 -> FPGA |
+| pin 17 LD | R50 22R | F11 `MAX_LD` | MAX2771 -> FPGA |
+| pin 4 CLKOUT | R45 22R | B11 `MAX_CLKOUT` | MAX2771 -> FPGA |
+
+Tüm bu pinler Ti375 BR0 bankındadır ve `VCC3V0_DIG=3.0 V` kullanır. SCLK,
+CSN, SDATA ve SHDN ise aynı 3.0 V standardındaki TR0 bankındadır.
+
+Başlangıç register görüntüsünün önemli seçimleri:
+
+| Register | Değer | Karar |
+|---|---|---|
+| 0x0 | `0xBEA71619` | MIXIN_HI, iki LNA kapalı, 23.4 MHz 5. derece LPF |
+| 0x3 | `0x698C0008` | Integer-N GPS L1 PLL |
+| 0x4 | `0x00C08080` | NDIV=1540, RDIV=16; 1575.42 MHz |
+| 0x7 | `0x110061B2` | Harici 40 MHz ADC sampling clock |
+| 0xA | `0x010061B4` | ADC sampling clocku CLKOUT'a yönlendir |
+
+Tam görüntü `max2771_registers.csv` dosyasındadır.
+
+## SCH16T-K01 SafeSPI arayüzü
+
+| İşlev | FPGA ball/net | Seri eleman | SCH16T pini | Yön |
+|---|---|---|---|---|
+| SCK | A8 `IMU_SCK` | R57 22R, FPGA yanında | pin 21 SCK | FPGA -> IMU |
+| MOSI | A9 `IMU_MOSI` | R58 22R, FPGA yanında | pin 23 MOSI | FPGA -> IMU |
+| CS_N | B10 `IMU_CS` | R59 22R, FPGA yanında | pin 22 CS | FPGA -> IMU |
+| MISO | B9 `IMU_MISO` | R60 22R, IMU yanında | pin 19 MISO | IMU -> FPGA |
+| Data-ready / sync | A11 `IMU_DRY_SYNC` | doğrudan | pin 20 DRY_SYNC | çift yönlü |
+| Harici reset | C10 `IMU_EXTRESN` | R61 10k pulldown | pin 6 EXTRESN | FPGA -> IMU |
+
+SafeSPI clock mode 0 kullanılır. SCH16T V3P3 girişleri `VCC3V3` üzerinden FB1
+600 ohm@100 MHz ferritle `IMU_3V3` rayına ayrılır. VDDIO doğrudan 3.3 V'tur.
+Murata'nın dahili regülatör pinlerinde C105 10 uF (`VREGA2`) ve C106 1 uF
+(`VREGD`) bulunur. `IMU_EXTRESN` pulldown nedeniyle FPGA resetten çıkıp pini
+aktif olarak yükseltmeden sensör çalışmaya başlamaz.
+
+## FPGA konfigürasyon flashı
+
+| IS25WP512M pini | Net | Ti375 ball / dedicated işlev |
+|---|---|---|
+| 1 CS_N | `QSPI_CS_N` | A7 / SSL_N |
+| 2 IO1 | `QSPI_IO1` | H5 / CDI1 |
+| 3 IO2 | `QSPI_IO2` | G5 / CDI2 |
+| 5 IO0 | `QSPI_IO0` | H4 / CDI0 |
+| 6 SCLK | `QSPI_SCLK` | G6 / CCK_PLLIN0 |
+| 7 IO3 | `QSPI_IO3` | B7 / CDI3 |
+| 8 VCC | `VCC1V8` | 1.8 V config domain |
+
+CS_N, IO2/WP_N ve IO3/HOLD_N 10 kohm ile 1.8 V'a çekilir. Ti375 `TEST_N`,
+`CSI` ve open-drain `CDONE` pinlerinde de Efinix'in istediği 10 kohm 1.8 V
+pull-up'lar vardır.
+
+## FT4232H arayüzleri
+
+| USB interface | FTDI pinleri | FPGA işlevi | FPGA ball'ları |
+|---|---|---|---|
+| A / interface 0 | ADBUS0 TCK, 1 TDI, 2 TDO, 3 TMS | RISC-V JTAG | F12, V19, T18, P18 |
+| B / interface 1 | BDBUS0 TCK, 1 TDI, 2 TDO, 3 TMS | FPGA hard JTAG | G10, G9, G13, G12 |
+| B | BDBUS4 | Aktif-düşük FPGA reset isteği | CRESET_N open-drain fan-in |
+| C / interface 2 | CDBUS0 TXD, CDBUS1 RXD | UART0 | P17 RX, R17 TX |
+| D / interface 3 | DDBUS0 TXD, DDBUS1 RXD | UART1 | R18 RX, T19 TX |
+| D | DDBUS2 | Debug GPIO | U19 |
+
+FTDI'den FPGA'ya giden TCK/TDI/TMS, UART RX ve debug çıkışları U29/U30
+bufferlarından ve ardından 33 ohm seri dirençlerden geçer. FPGA'dan FTDI'ye
+giden TDO/UART TX yönleri 33 ohm seri dirençlidir. JTAG hatlarının FPGA
+tarafında 10 kohm idle pull-up vardır.
+
+## USB-C güç ve veri
+
+- J1 CC1/CC2 -> U5 TUSB320LAI; PORT=GND ile UFP/sink.
+- J1 D+/D− -> U6 TPD2EUSB30A -> R63/R64 27 ohm -> U2 FT4232H.
+- J1 VBUS -> U7 TPS259470A -> `USB5_PROT` -> U9 TPS2121 -> `SYS5`.
+- Harici J3 5 V -> U8 TPS259470A -> `EXT5_PROT` -> U9 TPS2121 -> `SYS5`.
+- U10/U11, USB 3 A ilanı veya seçilmiş harici kaynak yoksa ana FPGA güç
+  converterlarını kapalı tutar.
+
+## Test noktaları
+
+| TP | Net | Amaç |
+|---|---|---|
+| TP1 | `U7_FLT` | USB eFuse fault |
+| TP2 | `U8_FLT` | Harici giriş eFuse fault |
+| TP3 | `ANT_BIAS_OC` | Aktif anten over-current |
+| TP4 | `VBUS_RAW` | USB VBUS |
+| TP5 | `EXT5_RAW` | Harici 5 V giriş |
+| TP6 | `SYS5` | Seçilmiş sistem 5 V |
+| TP7 | `VCC3V3_AUX` | Her zaman açık yardımcı 3.3 V |
+| TP8 | `VCC0V95` | FPGA core 0.95 V |
+| TP9 | `VCC1V8` | FPGA AUX/config 1.8 V |
+| TP10 | `VCC3V3` | FPGA/IMU/PMOD 3.3 V |
+| TP11 | `VCC3V0_RF` | MAX2771 analog 3.0 V |
+| TP12 | `VCC3V0_DIG` | MAX2771/FPGA bank 3.0 V |
+| TP13 | `FPGA_CRESET_N` | FPGA reset durumu |
+| TP14 | `FPGA_CDONE` | Konfigürasyon tamamlandı |
+| TP15 | `GND` | Ölçüm referansı |
@@ -0,0 +1,93 @@
+# Güç ağacı, sıralama ve reset
+
+## Giriş yolu
+
+```text
+USB-C VBUS -> U7 TPS259470A (2.69 A typ) -> USB5_PROT --+
+                                                          +-> U9 TPS2121 -> SYS5
+EXT_5V ----> U8 TPS259470A (4.04 A typ) -> EXT5_PROT --+
+```
+
+Her iki eFuse yaklaşık 4.0 V UV ve 5.8 V OV eşiğine, kontrollü output slew'a,
+fault test noktasına ve true reverse-current blocking'e sahiptir. U9 4.5 A
+limitli power mux'tur; yakın geçerli girişlerde harici 5 V yolu önceliklidir.
+
+USB yolunda TUSB320 CC ilanı U10 tarafından decode edilir. `MAIN_EN`, yalnızca
+USB kaynağı 3 A ilan ettiğinde veya harici giriş gerçekten U9 tarafından
+seçildiğinde yükselir. `VCC3V3_AUX` ise U12 üzerinden SYS5 var olduğu sürece
+supervisor/debug mantığını besler.
+
+## Ray üretimi
+
+| Sıra | Ray | Regülatör | Nominal kapasite | Yükler |
+|---:|---|---|---:|---|
+| 0 | `VCC3V3_AUX` | U12 TPS7A2033 | 300 mA | TUSB320, FT4232H I/O/regülatör, EEPROM, supervisor ve reset mantığı |
+| 1 | `VCC0V95` | U13 TPS6287B15 | 15 A sınıfı | Ti375 VCC/VCCA/VDD_SOC |
+| 2 | `VCC1V8` | U14 TPS62867 | 6 A sınıfı | Ti375 VCCAUX/config/HSIO, QSPI, iki 1.8 V PMOD |
+| 3 | `VCC3V3` | U15 TPS62867 | 6 A sınıfı | Ti375 HVIO, SCH16T, FTDI izolasyon bufferları, iki 3.3 V PMOD |
+| 4 | `VCC3V0_RF` | U17 TPS7A2030 | 300 mA | MAX2771 RF/PLL/IF/VCO |
+| 4 | `VCC3V0_DIG` | U18 TPS7A2030 | 300 mA | MAX2771 digital/ADC, Ti375 BR0/TR0 VCCIO |
+| 4 | `VCC3V0_CLK` | U19 TPS7A2030 | 300 mA | 16.368 MHz ve 40 MHz osilatörler |
+| bağımsız | `VCC3V3_ANT` | U20 TPS7A2033 | 300 mA | J5 3.3 V aktif anten seçeneği; U27 çıkışı 100 mA ile sınırlar |
+
+Bu tablo regulator sınıfını gösterir. Toplam çıkış gücü `SYS5` giriş gücünü,
+eFuse/mux limitini ve termal sınırı aşamaz.
+
+## FPGA açılış sırası
+
+1. `MAIN_EN`, U13 core buck'ı etkinleştirir.
+2. 0.95 V regülasyona girince U13 `CORE_PG` yükselir.
+3. `CORE_PG`, U16 LM3880'i başlatır.
+4. `SEQ_FLAG1` U14'ü açar; `VCC1V8` oluşur ve U14 `PG_1V8` verir.
+5. `SEQ_FLAG2` U15'i açar; `VCC3V3` oluşur ve U15 `PG_3V3` verir.
+6. 3.3 V LDO'ları açarak üç 3.0 V rayını oluşturur.
+7. U28 `VCC3V0_DIG > 2.79 V` gördükten sonra CT açık seçimiyle yaklaşık
+   20 ms bekler ve `FPGA_POWER_OK_N` bırakılır.
+8. U34 aşağıdaki mantığı üretir:
+
+```text
+ALL_FPGA_POWER_OK = CORE_PG
+                  AND PG_1V8
+                  AND PG_3V3
+                  AND FPGA_POWER_OK_N
+                  AND SEQ_FLAG3
+```
+
+9. Sonuç doğru olunca U32 CRESET_N'i bırakır ve Q1 U29/U30 buffer OE'yi açar.
+
+## Reset kaynakları
+
+| Kaynak | Koşul | CRESET yolu |
+|---|---|---|
+| Power valid | `ALL_FPGA_POWER_OK=0` | U32 açık-drenç çıkış low |
+| FTDI | BDBUS4 low | U31 açık-drenç çıkış low |
+| Kart butonu | SW1 basılı | U33 açık-drenç çıkış low |
+| Harici | J4 pin 1 GND'ye çekilir | 1k/4.7nF filtre, U33 açık-drenç output low |
+
+CRESET_N üzerinde tek pull-up R35=10 kohm ile `VCC1V8`'adır. Hiçbir reset
+sürücüsü high sürmez; dolayısıyla farklı power domain çıkışları çatışmaz.
+Harici reset pini dry-contact/open-drain girişidir, harici bir gerilim kaynağı
+değildir.
+
+## Kapanış davranışı
+
+Bir izlenen ray bozulduğunda ilgili PG düşer, U34 sonucu hemen düşük olur,
+CRESET_N çekilir ve FTDI'nin FPGA'ya doğru sürücüleri high-Z yapılır. Bu yapı
+yalnızca boot sırası için değil brown-out/back-power koruması için de kullanılır.
+LM3880 power-down sırasında FLAG3→FLAG2→FLAG1 ters sırasını uygular.
+
+## Ölçüm sırası
+
+İlk enerjilemede akım limitli laboratuvar kaynağı kullanılmalı ve şu sıra
+osiloskopla doğrulanmalıdır:
+
+1. TP6 `SYS5` ve TP7 `VCC3V3_AUX`.
+2. TP8 `VCC0V95`.
+3. TP9 `VCC1V8`.
+4. TP10 `VCC3V3`.
+5. TP12 `VCC3V0_DIG`.
+6. TP13 `FPGA_CRESET_N` ve TP14 `FPGA_CDONE`.
+
+TP13, son rail valid olduktan yaklaşık 20 ms sonra yükselmelidir. Boot
+tamamlandığında TP14 yükselmelidir. Gerçek inrush ve steady-state akımları
+ölçülmeden PMOD veya aktif anten yükü bağlanmamalıdır.
@@ -0,0 +1,40 @@
+# Türetilmiş tasarım verileri
+
+Bu klasördeki CSV/ISF dosyaları elle düzenlenecek ana tasarım kaynağı değildir;
+`scripts/design_data.py` ve `scripts/generate_design_tables.py` üzerinden tekrar
+üretilir.
+
+Okunabilir tasarım dokümanları:
+
+- `COMPONENT_SELECTION.md`: ana IC seçimi, besleme ve kapasite sınırları.
+- `INTERFACES.md`: RF, MAX2771, SafeSPI, QSPI, FTDI/USB ve test noktaları.
+- `FPGA_PINOUT.md`: FPGA ball/bank/gerilim ve dört PMOD eşlemesi.
+- `POWER_TREE.md`: giriş power-path, rail sıralaması, supervisor ve reset.
+
+| Dosya | Açıklama |
+|---|---|
+| `ti375_c529_package.csv` | Efinity 2025.2 Ti375C529 paket veritabanından çıkarılmış 529 ball kaydı |
+| `ti375_c529_package.meta.json` | Paket verisinin kaynak/sürüm metadatası |
+| `ti375_pinout.csv` | Kartta kullanılan sinyal, ball, bank, VCCIO, I/O standardı ve konnektör eşlemesi |
+| `unused_gpio_inventory.csv` | Kullanılan ve fiziksel olarak boş bırakılan fabric GPIO envanteri |
+| `ti375_pin_constraints.isf` | HDL/Efinity tarafı için pin ve I/O standardı constraintleri |
+| `max2771_registers.csv` | Kartın MAX2771 başlangıç register görüntüsü |
+
+Yeniden üretmek için:
+
+```bash
+python3 scripts/generate_design_tables.py
+```
+
+Script aşağıdaki koşulları doğrular:
+
+- Paket kaynağında tam 529 benzersiz ball bulunması.
+- Dedicated TCK/TMS/TDI/TDO, CRESET_N, CDONE ve JTAG_VCCIO_SEL adları.
+- Seçilen bankın istenen 3.3 V, 3.0 V veya 1.8 V I/O standardını desteklemesi.
+- PMOD tahsislerinde konfigürasyon/PLL/clock özel fonksiyonlarının yanlışlıkla
+  kullanılmaması.
+- MAX2771 ve SCH16T için ayrılmış pinlerle PMOD çakışması olmaması.
+
+Hard JTAG yalnızca kart üzerindeki FT4232H interface 1 üzerinden erişilir;
+harici ARM/JTAG headerı yoktur. `FPGA_CRESET_N`, açık-drenç power/FTDI/harici
+reset fan-in'i olarak belgelenmiştir.
@@ -0,0 +1,12 @@
+address,value_hex,default_hex,changed,purpose
+0x0,0xBEA71619,0xBEA41603,yes,"MIXIN_HI, both LNAs disabled, 23.4 MHz 5th-order LPF, 36 MHz mixer pole"
+0x1,0x20550288,0x20550288,no,Preserve MAX2771 documented reset/default value
+0x2,0x0EAFA1DC,0x0EAFA1DC,no,Preserve MAX2771 documented reset/default value
+0x3,0x698C0008,0x698C0008,no,Integer-N L1 PLL
+0x4,0x00C08080,0x00C00080,yes,"NDIV=1540, RDIV=16: 16.368 MHz / 16 * 1540 = 1575.42 MHz"
+0x5,0x08000070,0x08000070,no,Preserve MAX2771 documented reset/default value
+0x6,0x08000000,0x08000000,no,Preserve MAX2771 documented reset/default value
+0x7,0x110061B2,0x010061B2,yes,External 40 MHz ADC sampling clock on ADC_CLKIN
+0x8,0x01E0F401,0x01E0F401,no,Preserve MAX2771 documented reset/default value
+0x9,0x00C00002,0x00C00002,no,Preserve MAX2771 documented reset/default value
+0xA,0x010061B4,0x010061B0,yes,Route ADC sampling clock to CLKOUT for source-synchronous FPGA capture
@@ -0,0 +1,530 @@
+ball,official_pad_name,die_bank,package_bank,bank_class,allowed_vccio_v,direction,function,periphery_instances,instance_pin,special_capability,fabric_gpio
+A1,GND,,,HARD/POWER,,power,Ground,,,,no
+A2,GPIOB_P_30_CDI9_PLLIN0,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_30,P,PLL_INPUT;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+A3,GPIOB_N_32,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_32,N,DIFFERENTIAL_MEMBER,yes
+A4,GPIOB_P_32,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_32,P,DIFFERENTIAL_MEMBER,yes
+A5,GND,,,HARD/POWER,,power,Ground,,,,no
+A6,GPIOB_N_35,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_35,N,DIFFERENTIAL_MEMBER,yes
+A7,GPIOB_N_38_SSL_N,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_38,N,DIFFERENTIAL_MEMBER,yes
+A8,GPIOR_170,BR3,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_170,,,yes
+A9,GPIOR_171,BR3,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_171,,,yes
+A10,GND,,,HARD/POWER,,power,Ground,,,,no
+A11,GPIOR_93_PLLIN1,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_93,,PLL_INPUT,yes
+A12,GPIOR_95_CLK12,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_95,,CLOCK_CAPABLE,yes
+A13,GPIOR_94,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_94,,,yes
+A14,GPIOT_N_55,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_55,N,DIFFERENTIAL_MEMBER,yes
+A15,GND,,,HARD/POWER,,power,Ground,,,,no
+A16,GPIOT_P_53,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_53,P,DIFFERENTIAL_MEMBER,yes
+A17,GPIOT_N_53,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_53,N,DIFFERENTIAL_MEMBER,yes
+A18,GPIOT_P_57,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_57,P,DIFFERENTIAL_MEMBER,yes
+A19,GPIOT_N_57,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_57,N,DIFFERENTIAL_MEMBER,yes
+A20,GND,,,HARD/POWER,,power,Ground,,,,no
+A21,GPIOT_N_33_CLK16_N,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_33,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+A22,GPIOT_N_26,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_26,N,DIFFERENTIAL_MEMBER,yes
+A23,GND,,,HARD/POWER,,power,Ground,,,,no
+AA1,GND,,,HARD/POWER,,power,Ground,,,,no
+AA2,DDR0_DQ[6],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[6],,no
+AA3,VDDQX_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AA4,DDR0_DQS[0],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQS[0],,no
+AA5,GND,,,HARD/POWER,,power,Ground,,,,no
+AA6,DDR0_DQ[8],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[8],,no
+AA7,DDR0_DQS[1],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQS[1],,no
+AA8,DDR0_DQS_N[1],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQS_N[1],,no
+AA9,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AA10,GND,,,HARD/POWER,,power,Ground,,,,no
+AA11,DDR0_CKE[0],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CKE[0],,no
+AA12,NC,,,HARD/POWER,,,,,,,no
+AA13,DDR0_A[2],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,A[2],,no
+AA14,DDR0_A[3],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,A[3],,no
+AA15,GND,,,HARD/POWER,,power,Ground,,,,no
+AA16,DDR0_DQ[23],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[23],,no
+AA17,DDR0_DQS_N[2],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQS_N[2],,no
+AA18,VDDQX_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AA19,DDR0_DQ[28],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[28],,no
+AA20,GND,,,HARD/POWER,,power,Ground,,,,no
+AA21,DDR0_DQS[3],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQS[3],,no
+AA22,DDR0_DQ[25],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[25],,no
+AA23,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AB1,DDR0_DQ[7],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[7],,no
+AB2,DDR0_DQ[4],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[4],,no
+AB3,GND,,,HARD/POWER,,power,Ground,,,,no
+AB4,DDR0_DQS_N[0],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQS_N[0],,no
+AB5,DDR0_DQ[14],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[14],,no
+AB6,VDDQX_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AB7,DDR0_DM[1],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DM[1],,no
+AB8,GND,,,HARD/POWER,,power,Ground,,,,no
+AB9,DDR0_CS_N[2],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CS_N[2],,no
+AB10,DDR0_CS_N[1],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CS_N[1],,no
+AB11,DDR0_CK_N,DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CK_N,DIFFERENTIAL_MEMBER,no
+AB12,DDR0_A[0],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,A[0],,no
+AB13,GND,,,HARD/POWER,,power,Ground,,,,no
+AB14,NC,,,HARD/POWER,,,,,,,no
+AB15,DDR0_DM[2],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DM[2],,no
+AB16,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AB17,DDR0_DQS[2],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQS[2],,no
+AB18,GND,,,HARD/POWER,,power,Ground,,,,no
+AB19,DDR0_DQ[19],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[19],,no
+AB20,DDR0_DM[3],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DM[3],,no
+AB21,DDR0_DQS_N[3],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQS_N[3],,no
+AB22,GND,,,HARD/POWER,,power,Ground,,,,no
+AB23,DDR0_DQ[26],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[26],,no
+AC1,GND,,,HARD/POWER,,power,Ground,,,,no
+AC2,DDR0_DQ[5],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[5],,no
+AC3,DDR0_DM[0],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DM[0],,no
+AC4,VDDQX_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AC5,DDR0_DQ[15],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[15],,no
+AC6,GND,,,HARD/POWER,,power,Ground,,,,no
+AC7,DDR0_DQ[12],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[12],,no
+AC8,DDR0_DQ[13],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[13],,no
+AC9,GND,,,HARD/POWER,,power,Ground,,,,no
+AC10,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AC11,DDR0_CK,DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CK,,no
+AC12,GND,,,HARD/POWER,,power,Ground,,,,no
+AC13,DDR0_A[1],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,A[1],,no
+AC14,NC,,,HARD/POWER,,,,,,,no
+AC15,DDR0_A[4],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,A[4],,no
+AC16,GND,,,HARD/POWER,,power,Ground,,,,no
+AC17,DDR0_DQ[16],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[16],,no
+AC18,VDDQX_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AC19,DDR0_DQ[18],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[18],,no
+AC20,GND,,,HARD/POWER,,power,Ground,,,,no
+AC21,VDDQX_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+AC22,DDR0_DQ[27],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[27],,no
+AC23,GND,,,HARD/POWER,,power,Ground,,,,no
+B1,GPIOB_P_21,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_21,P,DIFFERENTIAL_MEMBER,yes
+B2,GPIOB_N_30_CDI8,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_30,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+B3,GND,,,HARD/POWER,,power,Ground,,,,no
+B4,GPIOB_N_31,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_31,N,DIFFERENTIAL_MEMBER,yes
+B5,GPIOB_N_34,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_34,N,DIFFERENTIAL_MEMBER,yes
+B6,GPIOB_P_35,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_35,P,DIFFERENTIAL_MEMBER,yes
+B7,GPIOB_P_38_CDI3,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_38,P,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+B8,GND,,,HARD/POWER,,power,Ground,,,,no
+B9,GPIOR_168,BR3,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_168,,,yes
+B10,GPIOR_169,BR3,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_169,,,yes
+B11,GPIOR_143_CLK9,BR0,BR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_143,,CLOCK_CAPABLE,yes
+B12,GPIOR_96_CLK13,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_96,,CLOCK_CAPABLE,yes
+B13,VCCIO33_TR1,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,power,VCCIO Power,,,,no
+B14,GPIOT_P_55,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_55,P,DIFFERENTIAL_MEMBER,yes
+B15,GPIOT_P_62_PLLIN0,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_62,P,PLL_INPUT;DIFFERENTIAL_MEMBER,yes
+B16,GPIOT_N_62,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_62,N,DIFFERENTIAL_MEMBER,yes
+B17,GPIOT_N_52,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_52,N,DIFFERENTIAL_MEMBER,yes
+B18,VCCIO2E,2E,2E,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+B19,GPIOT_N_54,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_54,N,DIFFERENTIAL_MEMBER,yes
+B20,GPIOT_N_51,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_51,N,DIFFERENTIAL_MEMBER,yes
+B21,GPIOT_P_33_CLK16_P,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_33,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+B22,GPIOT_N_27,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_27,N,DIFFERENTIAL_MEMBER,yes
+B23,GPIOT_P_26,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_26,P,DIFFERENTIAL_MEMBER,yes
+C1,GND,,,HARD/POWER,,power,Ground,,,,no
+C2,GPIOB_N_21,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_21,N,DIFFERENTIAL_MEMBER,yes
+C3,GPIOB_P_27,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_27,P,DIFFERENTIAL_MEMBER,yes
+C4,GPIOB_P_31,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_31,P,DIFFERENTIAL_MEMBER,yes
+C5,GPIOB_P_34,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_34,P,DIFFERENTIAL_MEMBER,yes
+C6,VCCIO4A_4B,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+C7,GPIOB_N_41,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_41,N,DIFFERENTIAL_MEMBER,yes
+C8,JTAG_VCCIO_SEL,4A,4A_4B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+C9,GPIOR_166,BR3,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_166,,,yes
+C10,GPIOR_167,BR3,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_167,,,yes
+C11,VCCIO33_BR0,BR0,BR0,HVIO,1.8;2.5;3.0;3.3,power,VCCIO Power,,,,no
+C12,GPIOR_99,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_99,,,yes
+C13,GPIOR_98,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_98,,,yes
+C14,GPIOR_97,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_97,,,yes
+C15,GPIOT_N_59,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_59,N,DIFFERENTIAL_MEMBER,yes
+C16,VCCIO2E,2E,2E,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+C17,GPIOT_P_52,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_52,P,DIFFERENTIAL_MEMBER,yes
+C18,GPIOT_N_60,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_60,N,DIFFERENTIAL_MEMBER,yes
+C19,GPIOT_P_54,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_54,P,DIFFERENTIAL_MEMBER,yes
+C20,GPIOT_P_51,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_51,P,DIFFERENTIAL_MEMBER,yes
+C21,GND,,,HARD/POWER,,power,Ground,,,,no
+C22,GPIOT_P_27,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_27,P,DIFFERENTIAL_MEMBER,yes
+C23,GND,,,HARD/POWER,,power,Ground,,,,no
+D1,GPIOB_P_20_CLK7_P,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_20,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+D2,GPIOB_N_20_CLK7_N,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_20,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+D3,GPIOB_N_27,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_27,N,DIFFERENTIAL_MEMBER,yes
+D4,VCCIO4A_4B,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+D5,GPIOB_N_37_CDI4,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_37,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+D6,GPIOB_P_37_CDI5,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_37,P,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+D7,GPIOB_P_41,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_41,P,DIFFERENTIAL_MEMBER,yes
+D8,GPIOB_N_44_CLK11_N,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_44,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+D9,VCCIO33_BR3_BR4,BR4,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,power,VCCIO Power,,,,no
+D10,GPIOR_144,BR0,BR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_144,,,yes
+D11,GPIOR_142_CLK8,BR0,BR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_142,,CLOCK_CAPABLE,yes
+D12,GPIOR_100,TR1,TR1,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_100,,,yes
+D13,GPIOR_102,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_102,,,yes
+D14,GND,,,HARD/POWER,,power,Ground,,,,no
+D15,GPIOT_P_59_PLLIN0,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_59,P,PLL_INPUT;DIFFERENTIAL_MEMBER,yes
+D16,GPIOT_P_58,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_58,P,DIFFERENTIAL_MEMBER,yes
+D17,GPIOT_N_58,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_58,N,DIFFERENTIAL_MEMBER,yes
+D18,GPIOT_P_60_EXTFB,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_60,P,PLL_EXTFB;DIFFERENTIAL_MEMBER,yes
+D19,GND,,,HARD/POWER,,power,Ground,,,,no
+D20,GPIOT_N_36_CLK19_N,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_36,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+D21,GPIOT_N_29,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_29,N,DIFFERENTIAL_MEMBER,yes
+D22,GPIOT_P_25,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_25,P,DIFFERENTIAL_MEMBER,yes
+D23,GPIOT_N_25,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_25,N,DIFFERENTIAL_MEMBER,yes
+E1,GPIOB_P_18_CLK5_P,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_18,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+E2,VCCIO4C,4C,4C,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+E3,GPIOB_P_24_CDI15,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_24,P,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+E4,GPIOB_N_36_CDI6,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_36,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+E5,GPIOB_P_36_CDI7,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_36,P,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+E6,GPIOB_N_42,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_42,N,DIFFERENTIAL_MEMBER,yes
+E7,GND,,,HARD/POWER,,power,Ground,,,,no
+E8,GPIOB_P_44_CLK11_P,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_44,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+E9,GPIOR_165_PLLIN1,BR3,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_165,,PLL_INPUT,yes
+E10,GPIOR_145_PLLIN1,BR0,BR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_145,,PLL_INPUT,yes
+E11,GPIOR_140_PLLIN1,BR0,BR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_140,,PLL_INPUT,yes
+E12,GND,,,HARD/POWER,,power,Ground,,,,no
+E13,GPIOR_103,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_103,,,yes
+E14,GPIOR_104,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_104,,,yes
+E15,GPIOR_107,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_107,,,yes
+E16,GPIOR_105,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_105,,,yes
+E17,GND,,,HARD/POWER,,power,Ground,,,,no
+E18,GPIOT_N_61,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_61,N,DIFFERENTIAL_MEMBER,yes
+E19,GPIOT_N_64_CLK15_N,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_64,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+E20,GPIOT_P_36_CLK19_P,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_36,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+E21,GPIOT_P_29,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_29,P,DIFFERENTIAL_MEMBER,yes
+E22,VCCIO2C,2C,2C,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+E23,GPIOT_N_23,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_23,N,DIFFERENTIAL_MEMBER,yes
+F1,GPIOB_N_18_CLK5_N,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_18,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+F2,GPIOB_P_17_CLK4_P,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_17,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+F3,GPIOB_N_24_CDI14,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_24,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+F4,GPIOB_N_33,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_33,N,DIFFERENTIAL_MEMBER,yes
+F5,VCCIO4A_4B,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+F6,GPIOB_P_42,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_42,P,DIFFERENTIAL_MEMBER,yes
+F7,VQPS,BR,BR,HARD/POWER,,power,,,,,no
+F8,CDONE,4A,4A_4B,HSIO,1.2;1.35;1.5;1.8,output,Configuration,,,,no
+F9,CRESET_N,4A,4A_4B,HSIO,1.2;1.35;1.5;1.8,input,Configuration,,,DIFFERENTIAL_MEMBER,no
+F10,GND,,,HARD/POWER,,power,Ground,,,,no
+F11,GPIOR_141,BR0,BR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_141,,,yes
+F12,GPIOR_101_PLLIN1,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_101,,PLL_INPUT,yes
+F13,GPIOR_106,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_106,,,yes
+F14,GPIOR_108,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_108,,,yes
+F15,VCCIO33_TR2,TR2,TR2,HVIO,1.8;2.5;3.0;3.3,power,VCCIO Power,,,,no
+F16,GPIOR_90,TR0,TR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_90,,,yes
+F17,GPIOR_91,TR0,TR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_91,,,yes
+F18,GPIOT_P_61_EXTFB,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_61,P,PLL_EXTFB;DIFFERENTIAL_MEMBER,yes
+F19,GPIOT_P_64_CLK15_P,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_64,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+F20,VCCIO2C,2C,2C,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+F21,GPIOT_P_35_CLK18_P,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_35,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+F22,GPIOT_N_35_CLK18_N,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_35,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+F23,GPIOT_P_23_PLLIN0,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_23,P,PLL_INPUT;DIFFERENTIAL_MEMBER,yes
+G1,GPIOB_P_23_CBSEL1,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_23,P,CONFIG_BOOT_SELECT;DIFFERENTIAL_MEMBER,yes
+G2,GPIOB_N_17_CLK4_N,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_17,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+G3,GND,,,HARD/POWER,,power,Ground,,,,no
+G4,GPIOB_P_33,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_33,P,DIFFERENTIAL_MEMBER,yes
+G5,GPIOB_N_39_CDI2,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_39,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+G6,GPIOB_P_39_CCK_PLLIN0,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_39,P,PLL_INPUT;DIFFERENTIAL_MEMBER,yes
+G7,VCCA_BR,BR,BR,HARD/POWER,,power,,,,,no
+G8,GND,,,HARD/POWER,,power,Ground,,,,no
+G9,TDI,BR4,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,input,Configuration,JTAG_USER1;JTAG_USER2;JTAG_USER3;JTAG_USER4,,,no
+G10,TCK,BR4,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,input,Configuration,JTAG_USER1;JTAG_USER2;JTAG_USER3;JTAG_USER4,,,no
+G11,VCCAUX,,,HARD/POWER,,power,,,,,no
+G12,TMS,BR4,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,input,Configuration,JTAG_USER1;JTAG_USER2;JTAG_USER3;JTAG_USER4,,,no
+G13,TDO,BR4,BR3_BR4,HVIO,1.8;2.5;3.0;3.3,output,Configuration,JTAG_USER1;JTAG_USER2;JTAG_USER3;JTAG_USER4,,,no
+G14,VCCAUX,,,HARD/POWER,,power,,,,,no
+G15,GPIOR_88_PLLIN1,TR0,TR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_88,,PLL_INPUT,yes
+G16,GPIOR_89,TR0,TR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_89,,,yes
+G17,GPIOR_92,TR0,TR0,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOR_92,,,yes
+G18,VCCIO2E,2E,2E,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+G19,GPIOT_N_63_CLK14_N,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_63,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+G20,GPIOT_N_34_CLK17_N,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_34,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+G21,GPIOT_P_28,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_28,P,DIFFERENTIAL_MEMBER,yes
+G22,GPIOT_N_28,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_28,N,DIFFERENTIAL_MEMBER,yes
+G23,GND,,,HARD/POWER,,power,Ground,,,,no
+H1,GND,,,HARD/POWER,,power,Ground,,,,no
+H2,GPIOB_N_23_CBSEL0,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_23,N,CONFIG_BOOT_SELECT;DIFFERENTIAL_MEMBER,yes
+H3,GPIOB_P_28,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_28,P,DIFFERENTIAL_MEMBER,yes
+H4,GPIOB_N_40_CDI0,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_40,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+H5,GPIOB_P_40_CDI1_EXTFB,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_40,P,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+H6,VCCIO4A_4B,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+H7,VCCAUX,,,HARD/POWER,,power,,,,,no
+H8,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+H9,GND,,,HARD/POWER,,power,Ground,,,,no
+H10,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+H11,GND,,,HARD/POWER,,power,Ground,,,,no
+H12,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+H13,GND,,,HARD/POWER,,power,Ground,,,,no
+H14,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+H15,GND,,,HARD/POWER,,power,Ground,,,,no
+H16,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+H17,VCCIO33_TR0,TR0,TR0,HVIO,1.8;2.5;3.0;3.3,power,VCCIO Power,,,,no
+H18,GPIOT_N_56,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_56,N,DIFFERENTIAL_MEMBER,yes
+H19,GPIOT_P_63_CLK14_P,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_63,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+H20,GPIOT_P_34_CLK17_P,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_34,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+H21,VCCIO2C,2C,2C,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+H22,GPIOT_P_24_EXTFB,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_24,P,PLL_EXTFB;DIFFERENTIAL_MEMBER,yes
+H23,GPIOT_N_24,2C,2C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_24,N,DIFFERENTIAL_MEMBER,yes
+J1,GPIOB_P_19_NSTATUS_CLK6_P,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_19,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+J2,GPIOB_N_19_TEST_N_CLK6_N,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_19,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+J3,GPIOB_N_28,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_28,N,DIFFERENTIAL_MEMBER,yes
+J4,VCCIO4C,4C,4C,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+J5,GPIOB_N_43_CSI_CLK10_N,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_43,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+J6,GPIOB_P_43_CSO_CLK10_P,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_43,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+J7,REF_RES_4A,4A,4A_4B,HSIO,1.2;1.35;1.5;1.8,input,,,,,no
+J8,GND,,,HARD/POWER,,power,Ground,,,,no
+J9,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+J10,GND,,,HARD/POWER,,power,Ground,,,,no
+J11,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+J12,GND,,,HARD/POWER,,power,Ground,,,,no
+J13,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+J14,GND,,,HARD/POWER,,power,Ground,,,,no
+J15,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+J16,GND,,,HARD/POWER,,power,Ground,,,,no
+J17,REF_RES_2E,2E,2E,HSIO,1.2;1.35;1.5;1.8,input,,,,,no
+J18,GPIOT_P_56,2E,2E,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_56,P,DIFFERENTIAL_MEMBER,yes
+J19,GND,,,HARD/POWER,,power,Ground,,,,no
+J20,GPIOT_P_17,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_17,P,DIFFERENTIAL_MEMBER,yes
+J21,GPIOT_P_16,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_16,P,DIFFERENTIAL_MEMBER,yes
+J22,GPIOT_P_10_CLK27_P,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_10,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+J23,GPIOT_N_10_CLK27_N,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_10,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+K1,GPIOB_P_14_CDI19_CLK1_P,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_14,P,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+K2,GND,,,HARD/POWER,,power,Ground,,,,no
+K3,GPIOB_P_29_CDI11_EXTFB,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_29,P,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+K4,GPIOB_N_29_CDI10,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_29,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+K5,GPIOB_P_26_EXTSPICLK,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_26,P,CLOCK_CAPABLE;EXT_SPI;DIFFERENTIAL_MEMBER,yes
+K6,GPIOB_P_25_CDI13,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_25,P,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+K7,REF_RES_4B,4B,4A_4B,HSIO,1.2;1.35;1.5;1.8,input,,,,,no
+K8,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+K9,GND,,,HARD/POWER,,power,Ground,,,,no
+K10,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+K11,GND,,,HARD/POWER,,power,Ground,,,,no
+K12,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+K13,GND,,,HARD/POWER,,power,Ground,,,,no
+K14,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+K15,GND,,,HARD/POWER,,power,Ground,,,,no
+K16,VCCA_TR,TR,TR,HARD/POWER,,power,,,,,no
+K17,GND,,,HARD/POWER,,power,Ground,,,,no
+K18,GPIOT_P_49_EXTFB,2D,2D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_49,P,PLL_EXTFB;DIFFERENTIAL_MEMBER,yes
+K19,GPIOT_N_49,2D,2D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_49,N,DIFFERENTIAL_MEMBER,yes
+K20,GPIOT_N_17,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_17,N,DIFFERENTIAL_MEMBER,yes
+K21,GPIOT_N_16,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_16,N,DIFFERENTIAL_MEMBER,yes
+K22,VCCIO2B,2B,2B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+K23,GPIOT_P_21,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_21,P,DIFFERENTIAL_MEMBER,yes
+L1,GPIOB_N_14_CDI18_CLK1_N,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_14,N,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+L2,GPIOB_P_15_CDI17_CLK2_P,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_15,P,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+L3,GPIOB_P_11,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_11,P,DIFFERENTIAL_MEMBER,yes
+L4,GPIOB_N_26_SSU_N,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_26,N,DIFFERENTIAL_MEMBER,yes
+L5,VCCIO4C,4C,4C,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+L6,GPIOB_N_25_CDI12,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_25,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+L7,VCCAUX,,,HARD/POWER,,power,,,,,no
+L8,GND,,,HARD/POWER,,power,Ground,,,,no
+L9,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+L10,GND,,,HARD/POWER,,power,Ground,,,,no
+L11,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+L12,GND,,,HARD/POWER,,power,Ground,,,,no
+L13,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+L14,GND,,,HARD/POWER,,power,Ground,,,,no
+L15,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+L16,VCCAUX,,,HARD/POWER,,power,,,,,no
+L17,GPIOT_P_50_PLLIN0,2D,2D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_50,P,PLL_INPUT;DIFFERENTIAL_MEMBER,yes
+L18,GPIOT_N_50,2D,2D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_50,N,DIFFERENTIAL_MEMBER,yes
+L19,GPIOT_P_20,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_20,P,DIFFERENTIAL_MEMBER,yes
+L20,VCCIO2B,2B,2B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+L21,GPIOT_P_11_CLK30_P,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_11,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+L22,GPIOT_N_11_CLK30_N,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_11,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+L23,GPIOT_N_21,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_21,N,DIFFERENTIAL_MEMBER,yes
+M1,GPIOB_P_09,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_09,P,DIFFERENTIAL_MEMBER,yes
+M2,GPIOB_N_15_CDI16_CLK2_N,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_15,N,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+M3,VCCIO4D,4D,4D,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+M4,GPIOB_N_11,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_11,N,DIFFERENTIAL_MEMBER,yes
+M5,GPIOB_P_22,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_22,P,DIFFERENTIAL_MEMBER,yes
+M6,GPIOB_N_22,4C,4C,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_22,N,DIFFERENTIAL_MEMBER,yes
+M7,REF_RES_4D,4D,4D,HSIO,1.2;1.35;1.5;1.8,input,,,,,no
+M8,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+M9,GND,,,HARD/POWER,,power,Ground,,,,no
+M10,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+M11,GND,,,HARD/POWER,,power,Ground,,,,no
+M12,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+M13,GND,,,HARD/POWER,,power,Ground,,,,no
+M14,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+M15,GND,,,HARD/POWER,,power,Ground,,,,no
+M16,GPIOT_P_43,2D,2D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_43,P,DIFFERENTIAL_MEMBER,yes
+M17,GPIOT_N_43,2D,2D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_43,N,DIFFERENTIAL_MEMBER,yes
+M18,VCCIO2D,2D,2D,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+M19,GPIOT_N_20,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_20,N,DIFFERENTIAL_MEMBER,yes
+M20,GPIOT_P_13_PLLIN0,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_13,P,PLL_INPUT;DIFFERENTIAL_MEMBER,yes
+M21,GPIOT_P_22,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_22,P,DIFFERENTIAL_MEMBER,yes
+M22,GPIOT_N_22,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_22,N,DIFFERENTIAL_MEMBER,yes
+M23,GND,,,HARD/POWER,,power,Ground,,,,no
+N1,GND,,,HARD/POWER,,power,Ground,,,,no
+N2,GPIOB_N_09,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_09,N,DIFFERENTIAL_MEMBER,yes
+N3,GPIOB_P_13_CDI21_CLK0_P,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_13,P,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+N4,GPIOB_N_12,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_12,N,DIFFERENTIAL_MEMBER,yes
+N5,GPIOB_P_12,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_12,P,DIFFERENTIAL_MEMBER,yes
+N6,GND,,,HARD/POWER,,power,Ground,,,,no
+N7,GPIOB_P_08_CDI22_EXTFB,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_08,P,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+N8,GND,,,HARD/POWER,,power,Ground,,,,no
+N9,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+N10,GND,,,HARD/POWER,,power,Ground,,,,no
+N11,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+N12,GND,,,HARD/POWER,,power,Ground,,,,no
+N13,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+N14,GND,,,HARD/POWER,,power,Ground,,,,no
+N15,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+N16,GND,,,HARD/POWER,,power,Ground,,,,no
+N17,GPIOT_P_40_CLK23_P,2D,2D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_40,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+N18,GPIOT_N_40_CLK23_N,2D,2D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_40,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+N19,GPIOT_P_14_EXTFB,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_14,P,PLL_EXTFB;DIFFERENTIAL_MEMBER,yes
+N20,GPIOT_N_13,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_13,N,DIFFERENTIAL_MEMBER,yes
+N21,VCCIO2B,2B,2B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+N22,GPIOT_P_15,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_15,P,DIFFERENTIAL_MEMBER,yes
+N23,GPIOT_N_15,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_15,N,DIFFERENTIAL_MEMBER,yes
+P1,GPIOB_N_16_CLK3_N,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_16,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+P2,GPIOB_P_16_CLK3_P,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_16,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+P3,GPIOB_N_13_CDI20_CLK0_N,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_13,N,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+P4,VCCIO4D,4D,4D,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+P5,GPIOB_P_06_CDI26_EXTFB,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_06,P,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+P6,GPIOB_P_05_CDI28_PLLIN0,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_05,P,PLL_INPUT;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+P7,GPIOB_N_08,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_08,N,DIFFERENTIAL_MEMBER,yes
+P8,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+P9,GND,,,HARD/POWER,,power,Ground,,,,no
+P10,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+P11,GND,,,HARD/POWER,,power,Ground,,,,no
+P12,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+P13,GND,,,HARD/POWER,,power,Ground,,,,no
+P14,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+P15,GND,,,HARD/POWER,,power,Ground,,,,no
+P16,VCCAUX,,,HARD/POWER,,power,,,,,no
+P17,GPIOL_84,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_84,,,yes
+P18,GPIOL_80_CLK29,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_80,,CLOCK_CAPABLE,yes
+P19,GND,,,HARD/POWER,,power,Ground,,,,no
+P20,GPIOT_N_14,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_14,N,DIFFERENTIAL_MEMBER,yes
+P21,GPIOT_P_18,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_18,P,DIFFERENTIAL_MEMBER,yes
+P22,GPIOT_N_18,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_18,N,DIFFERENTIAL_MEMBER,yes
+P23,GPIOT_P_09_CLK26_P,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_09,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+R1,GPIOB_P_04_CDI30_EXTFB,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_04,P,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+R2,VCCIO4D,4D,4D,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+R3,GPIOB_N_07_CDI23,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_07,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+R4,GPIOB_P_07_CDI24_PLLIN0,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_07,P,PLL_INPUT;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+R5,GPIOB_N_06_CDI25,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_06,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+R6,GPIOB_N_05_CDI27,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_05,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+R7,VCCAUX,,,HARD/POWER,,power,,,,,no
+R8,GND,,,HARD/POWER,,power,Ground,,,,no
+R9,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+R10,GND,,,HARD/POWER,,power,Ground,,,,no
+R11,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+R12,GND,,,HARD/POWER,,power,Ground,,,,no
+R13,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+R14,GND,,,HARD/POWER,,power,Ground,,,,no
+R15,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+R16,GND,,,HARD/POWER,,power,Ground,,,,no
+R17,GPIOL_85_PLLIN1,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_85,,PLL_INPUT,yes
+R18,GPIOL_87_PLLIN1,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_87,,PLL_INPUT,yes
+R19,GPIOT_P_19,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_19,P,DIFFERENTIAL_MEMBER,yes
+R20,GPIOT_N_19,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_19,N,DIFFERENTIAL_MEMBER,yes
+R21,GPIOT_P_12_CLK31_P,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_12,P,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+R22,VCCIO2B,2B,2B,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+R23,GPIOT_N_09_CLK26_N,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_09,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+T1,GPIOB_N_04_CDI29,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_04,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+T2,GPIOB_N_10,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_10,N,DIFFERENTIAL_MEMBER,yes
+T3,GPIOB_P_10,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_10,P,DIFFERENTIAL_MEMBER,yes
+T4,GPIOL_27_CLK25,BL3,BL2_BL3,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_27,,CLOCK_CAPABLE,yes
+T5,GND,,,HARD/POWER,,power,Ground,,,,no
+T6,VDD_SOC,SOC,SOC,HARD/POWER,,power,,,,,no
+T7,GND,,,HARD/POWER,,power,Ground,,,,no
+T8,VCCA_BL2,BL,BL,HARD/POWER,,power,,,,,no
+T9,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+T10,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+T11,GND,,,HARD/POWER,,power,Ground,,,,no
+T12,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+T13,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+T14,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+T15,GND,,,HARD/POWER,,power,Ground,,,,no
+T16,VCC,,,HARD/POWER,,power,1.1 V VCC Power,,,,no
+T17,VCCIO33_TL1_TL5,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,power,VCCIO Power,,,,no
+T18,GPIOL_83,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_83,,,yes
+T19,GPIOL_86,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_86,,,yes
+T20,VCCIO2A,2A,2A,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+T21,GPIOT_N_12_CLK31_N,2B,2B,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_12,N,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,yes
+T22,GPIOT_P_08_PLLIN0,2A,2A,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_08,P,PLL_INPUT;DIFFERENTIAL_MEMBER,yes
+T23,GPIOT_N_08,2A,2A,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_08,N,DIFFERENTIAL_MEMBER,yes
+U1,GPIOB_N_03_CDI31,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_03,N,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,yes
+U2,GPIOB_P_03_PLLIN0,4D,4D,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOB_PN_03,P,PLL_INPUT;DIFFERENTIAL_MEMBER,yes
+U3,VCCIO4D,4D,4D,HSIO,1.2;1.35;1.5;1.8,power,VCCIO Power,,,,no
+U4,GPIOL_25_PLLIN1,BL2,BL2_BL3,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_25,,PLL_INPUT,yes
+U5,GPIOL_34_PLLIN1,BL3,BL2_BL3,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_34,,PLL_INPUT,yes
+U6,GPIOL_24,BL2,BL2_BL3,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_24,,,yes
+U7,VDD_SOC,SOC,SOC,HARD/POWER,,power,,,,,no
+U8,VCCA_BL0_BL1,BL,BL,HARD/POWER,,power,,,,,no
+U9,GND,,,HARD/POWER,,power,Ground,,,,no
+U10,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+U11,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+U12,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+U13,GND,,,HARD/POWER,,power,Ground,,,,no
+U14,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+U15,VCCA_TL2,TL,TL,HARD/POWER,,power,,,,,no
+U16,VCCA_TL0_TL1,TL,TL,HARD/POWER,,power,,,,,no
+U17,GPIOL_79_CLK28,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_79,,CLOCK_CAPABLE,yes
+U18,GND,,,HARD/POWER,,power,Ground,,,,no
+U19,GPIOL_52_PLLIN1,TL1,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_52,,PLL_INPUT,yes
+U20,REF_RES_2A,2A,2A,HSIO,1.2;1.35;1.5;1.8,input,,,,,no
+U21,GPIOT_P_05,2A,2A,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_05,P,DIFFERENTIAL_MEMBER,yes
+U22,GPIOT_N_05,2A,2A,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_05,N,DIFFERENTIAL_MEMBER,yes
+U23,GND,,,HARD/POWER,,power,Ground,,,,no
+V1,GND,,,HARD/POWER,,power,Ground,,,,no
+V2,GPIOL_26_CLK24,BL3,BL2_BL3,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_26,,CLOCK_CAPABLE,yes
+V3,GPIOL_32_PLLIN1,BL3,BL2_BL3,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_32,,PLL_INPUT,yes
+V4,GPIOL_23,BL2,BL2_BL3,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_23,,,yes
+V5,VCCIO33_BL2_BL3,BL3,BL2_BL3,HVIO,1.8;2.5;3.0;3.3,power,VCCIO Power,,,,no
+V6,VDD_SOC,SOC,SOC,HARD/POWER,,power,,,,,no
+V7,GND,,,HARD/POWER,,power,Ground,,,,no
+V8,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+V9,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+V10,VDDQ_CK_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+V11,GND,,,HARD/POWER,,power,Ground,,,,no
+V12,VDDPLL_MCB_TOP_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+V13,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+V14,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+V15,GND,,,HARD/POWER,,power,Ground,,,,no
+V16,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+V17,VDD_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+V18,VCCIO33_TL1_TL5,TL5,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,power,VCCIO Power,,,,no
+V19,GPIOL_46,TL1,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_46,,,yes
+V20,GPIOL_45,TL1,TL1_TL5,HVIO,1.8;2.5;3.0;3.3,configurable,,GPIOL_45,,,yes
+V21,GND,,,HARD/POWER,,power,Ground,,,,no
+V22,GPIOT_P_07_EXTFB,2A,2A,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_07,P,PLL_EXTFB;DIFFERENTIAL_MEMBER,yes
+V23,GPIOT_N_07,2A,2A,HSIO,1.2;1.35;1.5;1.8,configurable,,GPIOT_PN_07,N,DIFFERENTIAL_MEMBER,yes
+W1,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W2,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W3,VDDQX_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W4,GND,,,HARD/POWER,,power,Ground,,,,no
+W5,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W6,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W7,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W8,DDR0_DQ[11],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[11],,no
+W9,GND,,,HARD/POWER,,power,Ground,,,,no
+W10,DDR0_CKE[1],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CKE[1],,no
+W11,DDR0_CAL,DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CAL,,no
+W12,NC,,,HARD/POWER,,,,,,,no
+W13,NC,,,HARD/POWER,,,,,,,no
+W14,GND,,,HARD/POWER,,power,Ground,,,,no
+W15,DDR0_DQ[21],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[21],,no
+W16,DDR0_DQ[20],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[20],,no
+W17,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W18,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W19,GND,,,HARD/POWER,,power,Ground,,,,no
+W20,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W21,VDDQX_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W22,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+W23,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+Y1,DDR0_DQ[0],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[0],,no
+Y2,GND,,,HARD/POWER,,power,Ground,,,,no
+Y3,DDR0_DQ[1],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[1],,no
+Y4,DDR0_DQ[2],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[2],,no
+Y5,DDR0_DQ[3],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[3],,no
+Y6,DDR0_DQ[10],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[10],,no
+Y7,GND,,,HARD/POWER,,power,Ground,,,,no
+Y8,DDR0_DQ[9],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[9],,no
+Y9,DDR0_CS_N[3],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CS_N[3],,no
+Y10,DDR0_CS_N[0],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,CS_N[0],,no
+Y11,DDR0_RST_N,DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,RST_N,DIFFERENTIAL_MEMBER,no
+Y12,GND,,,HARD/POWER,,power,Ground,,,,no
+Y13,NC,,,HARD/POWER,,,,,,,no
+Y14,DDR0_A[5],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,A[5],,no
+Y15,VDDQ_PHY_DDR0,DDR0,DDR0,HARD/POWER,,power,,,,,no
+Y16,DDR0_DQ[22],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[22],,no
+Y17,GND,,,HARD/POWER,,power,Ground,,,,no
+Y18,DDR0_DQ[17],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[17],,no
+Y19,DDR0_DQ[30],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[30],,no
+Y20,DDR0_DQ[29],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[29],,no
+Y21,DDR0_DQ[31],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[31],,no
+Y22,GND,,,HARD/POWER,,power,Ground,,,,no
+Y23,DDR0_DQ[24],DDR0,DDR0,HARD/POWER,,configurable,,DDR_0,DQ[24],,no
@@ -0,0 +1,27 @@
+{
+  "device": "Ti375C529",
+  "fabric_gpio_count": 227,
+  "mapped_device": "opx_466x964_b56_d28_bc529",
+  "package": "529-ball FBGA",
+  "package_banks": [
+    "2A",
+    "2B",
+    "2C",
+    "2D",
+    "2E",
+    "4A_4B",
+    "4C",
+    "4D",
+    "BL2_BL3",
+    "BR0",
+    "BR3_BR4",
+    "TL1_TL5",
+    "TR0",
+    "TR1",
+    "TR2"
+  ],
+  "package_status": "final",
+  "row_count": 529,
+  "source_database": "/tools/efinix/efinity/2025.2/pt/db/resource/Ti375C529.db",
+  "source_sha256": "ef752ff9cb71fed702254a9ee4dc74050fc33ab01f03b2a327a8e034864cfbe6"
+}
@@ -0,0 +1,74 @@
+# Efinity interface constraints generated from the official Ti375C529 database.
+# Verify port names against the final RTL top level before importing.
+set_pin_assignment -pin_name U17 -port_name CLK_40M_FPGA
+set_pin_assignment -pin_name F8 -port_name FPGA_CDONE
+set_pin_assignment -pin_name F9 -port_name FPGA_CRESET_N
+set_pin_assignment -pin_name J5 -port_name FPGA_CSI
+set_pin_assignment -pin_name J2 -port_name FPGA_TEST_N
+set_pin_assignment -pin_name U19 -port_name FTDI_DBG_GPIO
+set_pin_assignment -pin_name G10 -port_name HARD_TCK
+set_pin_assignment -pin_name G9 -port_name HARD_TDI
+set_pin_assignment -pin_name G13 -port_name HARD_TDO
+set_pin_assignment -pin_name G12 -port_name HARD_TMS
+set_pin_assignment -pin_name B10 -port_name IMU_CS
+set_pin_assignment -pin_name A11 -port_name IMU_DRY_SYNC
+set_pin_assignment -pin_name C10 -port_name IMU_EXTRESN
+set_pin_assignment -pin_name B9 -port_name IMU_MISO
+set_pin_assignment -pin_name A9 -port_name IMU_MOSI
+set_pin_assignment -pin_name A8 -port_name IMU_SCK
+set_pin_assignment -pin_name B11 -port_name MAX_CLKOUT
+set_pin_assignment -pin_name F17 -port_name MAX_CSN
+set_pin_assignment -pin_name D10 -port_name MAX_I0
+set_pin_assignment -pin_name D11 -port_name MAX_I1
+set_pin_assignment -pin_name F11 -port_name MAX_LD
+set_pin_assignment -pin_name E10 -port_name MAX_Q0
+set_pin_assignment -pin_name E11 -port_name MAX_Q1
+set_pin_assignment -pin_name F16 -port_name MAX_SCLK
+set_pin_assignment -pin_name G16 -port_name MAX_SDATA
+set_pin_assignment -pin_name G17 -port_name MAX_SHDN
+set_pin_assignment -pin_name U6 -port_name PMOD1_1
+set_pin_assignment -pin_name D12 -port_name PMOD1_10
+set_pin_assignment -pin_name V4 -port_name PMOD1_2
+set_pin_assignment -pin_name A13 -port_name PMOD1_3
+set_pin_assignment -pin_name C9 -port_name PMOD1_4
+set_pin_assignment -pin_name C12 -port_name PMOD1_7
+set_pin_assignment -pin_name C13 -port_name PMOD1_8
+set_pin_assignment -pin_name C14 -port_name PMOD1_9
+set_pin_assignment -pin_name V20 -port_name PMOD2_1
+set_pin_assignment -pin_name F14 -port_name PMOD2_10
+set_pin_assignment -pin_name D13 -port_name PMOD2_2
+set_pin_assignment -pin_name E13 -port_name PMOD2_3
+set_pin_assignment -pin_name E14 -port_name PMOD2_4
+set_pin_assignment -pin_name E16 -port_name PMOD2_7
+set_pin_assignment -pin_name F13 -port_name PMOD2_8
+set_pin_assignment -pin_name E15 -port_name PMOD2_9
+set_pin_assignment -pin_name C20 -port_name PMOD3_1
+set_pin_assignment -pin_name B19 -port_name PMOD3_10
+set_pin_assignment -pin_name B20 -port_name PMOD3_2
+set_pin_assignment -pin_name C17 -port_name PMOD3_3
+set_pin_assignment -pin_name B17 -port_name PMOD3_4
+set_pin_assignment -pin_name A16 -port_name PMOD3_7
+set_pin_assignment -pin_name A17 -port_name PMOD3_8
+set_pin_assignment -pin_name C19 -port_name PMOD3_9
+set_pin_assignment -pin_name B14 -port_name PMOD4_1
+set_pin_assignment -pin_name D17 -port_name PMOD4_10
+set_pin_assignment -pin_name A14 -port_name PMOD4_2
+set_pin_assignment -pin_name J18 -port_name PMOD4_3
+set_pin_assignment -pin_name H18 -port_name PMOD4_4
+set_pin_assignment -pin_name A18 -port_name PMOD4_7
+set_pin_assignment -pin_name A19 -port_name PMOD4_8
+set_pin_assignment -pin_name D16 -port_name PMOD4_9
+set_pin_assignment -pin_name A7 -port_name QSPI_CS_N
+set_pin_assignment -pin_name H4 -port_name QSPI_IO0
+set_pin_assignment -pin_name H5 -port_name QSPI_IO1
+set_pin_assignment -pin_name G5 -port_name QSPI_IO2
+set_pin_assignment -pin_name B7 -port_name QSPI_IO3
+set_pin_assignment -pin_name G6 -port_name QSPI_SCLK
+set_pin_assignment -pin_name F12 -port_name RISCV_TCK
+set_pin_assignment -pin_name V19 -port_name RISCV_TDI
+set_pin_assignment -pin_name T18 -port_name RISCV_TDO
+set_pin_assignment -pin_name P18 -port_name RISCV_TMS
+set_pin_assignment -pin_name P17 -port_name UART0_RX
+set_pin_assignment -pin_name R17 -port_name UART0_TX
+set_pin_assignment -pin_name R18 -port_name UART1_RX
+set_pin_assignment -pin_name T19 -port_name UART1_TX
@@ -0,0 +1,73 @@
+signal,ball,official_pin_name,die_bank,package_bank,vccio,io_standard,direction,clock_capability,special_function,subsystem,connector,connector_pin,note
+IMU_DRY_SYNC,A11,GPIOR_93_PLLIN1,TR1,TR1,3.3 V,3.3 V LVCMOS,bidirectional,no,PLL_INPUT,sch16t,on-board,,Murata multiplexed Data Ready output / SYNC input
+PMOD1_3,A13,GPIOR_94,TR1,TR1,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr1,JPMOD1,3,PMOD 1 pin 3
+PMOD4_2,A14,GPIOT_N_55,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD4,2,PMOD 4 pin 2; HSIO pair 55 N
+PMOD3_7,A16,GPIOT_P_53,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD3,7,PMOD 3 pin 7; HSIO pair 53 P
+PMOD3_8,A17,GPIOT_N_53,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD3,8,PMOD 3 pin 8; HSIO pair 53 N
+PMOD4_7,A18,GPIOT_P_57,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD4,7,PMOD 4 pin 7; HSIO pair 57 P
+PMOD4_8,A19,GPIOT_N_57,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD4,8,PMOD 4 pin 8; HSIO pair 57 N
+QSPI_CS_N,A7,GPIOB_N_38_SSL_N,4B,4A_4B,1.8 V,1.8 V LVCMOS,output,no,DIFFERENTIAL_MEMBER,configuration,on-board,,SPI-active SSL_N
+IMU_SCK,A8,GPIOR_170,BR3,BR3_BR4,3.3 V,3.3 V LVCMOS,output,no,,sch16t,on-board,,SafeSPI mode-0 clock
+IMU_MOSI,A9,GPIOR_171,BR3,BR3_BR4,3.3 V,3.3 V LVCMOS,output,no,,sch16t,on-board,,SafeSPI controller-to-sensor data
+IMU_CS,B10,GPIOR_169,BR3,BR3_BR4,3.3 V,3.3 V LVCMOS,output,no,,sch16t,on-board,,SafeSPI active-low chip select
+MAX_CLKOUT,B11,GPIOR_143_CLK9,BR0,BR0,3.0 V,3.0 V LVCMOS,input,yes,CLOCK_CAPABLE,max2771,on-board,,Source-synchronous ADC capture clock on dedicated clock-capable input
+PMOD4_1,B14,GPIOT_P_55,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD4,1,PMOD 4 pin 1; HSIO pair 55 P
+PMOD3_4,B17,GPIOT_N_52,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD3,4,PMOD 3 pin 4; HSIO pair 52 N
+PMOD3_10,B19,GPIOT_N_54,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD3,10,PMOD 3 pin 10; HSIO pair 54 N
+PMOD3_2,B20,GPIOT_N_51,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD3,2,PMOD 3 pin 2; HSIO pair 51 N
+QSPI_IO3,B7,GPIOB_P_38_CDI3,4B,4A_4B,1.8 V,1.8 V LVCMOS,bidirectional,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,configuration,on-board,,SPI-active CDI3
+IMU_MISO,B9,GPIOR_168,BR3,BR3_BR4,3.3 V,3.3 V LVCMOS,input,no,,sch16t,on-board,,SafeSPI sensor-to-controller data
+IMU_EXTRESN,C10,GPIOR_167,BR3,BR3_BR4,3.3 V,3.3 V LVCMOS,output,no,,sch16t,on-board,,External active-low reset
+PMOD1_7,C12,GPIOR_99,TR1,TR1,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr1,JPMOD1,7,PMOD 1 pin 7
+PMOD1_8,C13,GPIOR_98,TR1,TR1,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr1,JPMOD1,8,PMOD 1 pin 8
+PMOD1_9,C14,GPIOR_97,TR1,TR1,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr1,JPMOD1,9,PMOD 1 pin 9
+PMOD3_3,C17,GPIOT_P_52,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD3,3,PMOD 3 pin 3; HSIO pair 52 P
+PMOD3_9,C19,GPIOT_P_54,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD3,9,PMOD 3 pin 9; HSIO pair 54 P
+PMOD3_1,C20,GPIOT_P_51,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD3,1,PMOD 3 pin 1; HSIO pair 51 P
+PMOD1_4,C9,GPIOR_166,BR3,BR3_BR4,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_3v3,JPMOD1,4,PMOD 1 pin 4; plain HVIO GPIO
+MAX_I0,D10,GPIOR_144,BR0,BR0,3.0 V,3.0 V LVCMOS,input,no,,max2771,on-board,,ADC I bit 0
+MAX_I1,D11,GPIOR_142_CLK8,BR0,BR0,3.0 V,3.0 V LVCMOS,input,yes,CLOCK_CAPABLE,max2771,on-board,,ADC I bit 1; clock-capable pad retained in same BR0 bank
+PMOD1_10,D12,GPIOR_100,TR1,TR1,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr1,JPMOD1,10,PMOD 1 pin 10
+PMOD2_2,D13,GPIOR_102,TR2,TR2,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr2,JPMOD2,2,PMOD 2 pin 2
+PMOD4_9,D16,GPIOT_P_58,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD4,9,PMOD 4 pin 9; HSIO pair 58 P
+PMOD4_10,D17,GPIOT_N_58,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD4,10,PMOD 4 pin 10; HSIO pair 58 N
+MAX_Q0,E10,GPIOR_145_PLLIN1,BR0,BR0,3.0 V,3.0 V LVCMOS,input,no,PLL_INPUT,max2771,on-board,,ADC Q bit 0; PLL-capable pad in same BR0 bank
+MAX_Q1,E11,GPIOR_140_PLLIN1,BR0,BR0,3.0 V,3.0 V LVCMOS,input,no,PLL_INPUT,max2771,on-board,,ADC Q bit 1; PLL-capable pad in same BR0 bank
+PMOD2_3,E13,GPIOR_103,TR2,TR2,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr2,JPMOD2,3,PMOD 2 pin 3
+PMOD2_4,E14,GPIOR_104,TR2,TR2,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr2,JPMOD2,4,PMOD 2 pin 4
+PMOD2_9,E15,GPIOR_107,TR2,TR2,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr2,JPMOD2,9,PMOD 2 pin 9
+PMOD2_7,E16,GPIOR_105,TR2,TR2,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr2,JPMOD2,7,PMOD 2 pin 7
+MAX_LD,F11,GPIOR_141,BR0,BR0,3.0 V,3.0 V LVCMOS,input,no,,max2771,on-board,,PLL lock status
+RISCV_TCK,F12,GPIOR_101_PLLIN1,TR2,TR2,3.3 V,3.3 V LVCMOS,input,no,PLL_INPUT,secondary_jtag,on-board,,Fabric RISC-V JTAG clock moved off the plain-GPIO PMOD allocation
+PMOD2_8,F13,GPIOR_106,TR2,TR2,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr2,JPMOD2,8,PMOD 2 pin 8
+PMOD2_10,F14,GPIOR_108,TR2,TR2,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_tr2,JPMOD2,10,PMOD 2 pin 10
+MAX_SCLK,F16,GPIOR_90,TR0,TR0,3.0 V,3.0 V LVCMOS,output,no,,max2771,on-board,,Three-wire serial clock
+MAX_CSN,F17,GPIOR_91,TR0,TR0,3.0 V,3.0 V LVCMOS,output,no,,max2771,on-board,,Three-wire active-low chip select
+FPGA_CDONE,F8,CDONE,4A,4A_4B,1.8 V,1.8 V LVCMOS,output,no,,configuration,on-board,,Configuration status test point
+FPGA_CRESET_N,F9,CRESET_N,4A,4A_4B,1.8 V,1.8 V LVCMOS,input,no,DIFFERENTIAL_MEMBER,configuration,on-board,,"Open-drain fan-in of all-rail-valid, FTDI, and filtered external/manual reset requests"
+HARD_TCK,G10,TCK,BR4,BR3_BR4,3.3 V,3.3 V LVCMOS,input,no,,hard_jtag,on-board,,Dedicated hard TAP TCK; FT4232H interface 1 BDBUS0 through power-domain isolation
+HARD_TMS,G12,TMS,BR4,BR3_BR4,3.3 V,3.3 V LVCMOS,input,no,,hard_jtag,on-board,,Dedicated hard TAP TMS; FT4232H interface 1 BDBUS3 through power-domain isolation
+HARD_TDO,G13,TDO,BR4,BR3_BR4,3.3 V,3.3 V LVCMOS,output,no,,hard_jtag,on-board,,Dedicated hard TAP TDO; FT4232H interface 1 BDBUS2 through power-domain isolation
+MAX_SDATA,G16,GPIOR_89,TR0,TR0,3.0 V,3.0 V LVCMOS,bidirectional,no,,max2771,on-board,,Single bidirectional three-wire serial data; not split MOSI/MISO
+MAX_SHDN,G17,GPIOR_92,TR0,TR0,3.0 V,3.0 V LVCMOS,output,no,,max2771,on-board,,MAX2771 hardware shutdown control
+QSPI_IO2,G5,GPIOB_N_39_CDI2,4B,4A_4B,1.8 V,1.8 V LVCMOS,bidirectional,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,configuration,on-board,,SPI-active CDI2
+QSPI_SCLK,G6,GPIOB_P_39_CCK_PLLIN0,4B,4A_4B,1.8 V,1.8 V LVCMOS,output,no,PLL_INPUT;DIFFERENTIAL_MEMBER,configuration,on-board,,SPI-active CCK; official CCK_PLLIN0 pin
+HARD_TDI,G9,TDI,BR4,BR3_BR4,3.3 V,3.3 V LVCMOS,input,no,,hard_jtag,on-board,,Dedicated hard TAP TDI; FT4232H interface 1 BDBUS1 through power-domain isolation
+PMOD4_4,H18,GPIOT_N_56,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD4,4,PMOD 4 pin 4; HSIO pair 56 N
+QSPI_IO0,H4,GPIOB_N_40_CDI0,4B,4A_4B,1.8 V,1.8 V LVCMOS,bidirectional,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,configuration,on-board,,SPI-active CDI0
+QSPI_IO1,H5,GPIOB_P_40_CDI1_EXTFB,4B,4A_4B,1.8 V,1.8 V LVCMOS,bidirectional,no,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,configuration,on-board,,SPI-active CDI1
+PMOD4_3,J18,GPIOT_P_56,2E,2E,1.8 V,1.8 V LVCMOS,bidirectional,no,DIFFERENTIAL_MEMBER,pmod_2e,JPMOD4,3,PMOD 4 pin 3; HSIO pair 56 P
+FPGA_TEST_N,J2,GPIOB_N_19_TEST_N_CLK6_N,4C,4C,1.8 V,1.8 V LVCMOS,input,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,configuration,on-board,,Mandatory external weak pull-up disables test mode during configuration
+FPGA_CSI,J5,GPIOB_N_43_CSI_CLK10_N,4B,4A_4B,1.8 V,1.8 V LVCMOS,input,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,configuration,on-board,,Mandatory external weak pull-up selects this FPGA throughout configuration
+UART0_RX,P17,GPIOL_84,TL5,TL1_TL5,3.3 V,3.3 V LVCMOS,input,no,,ft4232,on-board,,FT4232H channel C TXD to FPGA RX
+RISCV_TMS,P18,GPIOL_80_CLK29,TL5,TL1_TL5,3.3 V,3.3 V LVCMOS,input,yes,CLOCK_CAPABLE,secondary_jtag,on-board,,Clock-capable fabric pin; official development-kit assignment
+UART0_TX,R17,GPIOL_85_PLLIN1,TL5,TL1_TL5,3.3 V,3.3 V LVCMOS,output,no,PLL_INPUT,ft4232,on-board,,FPGA TX to FT4232H channel C RXD
+UART1_RX,R18,GPIOL_87_PLLIN1,TL5,TL1_TL5,3.3 V,3.3 V LVCMOS,input,no,PLL_INPUT,ft4232,on-board,,FT4232H channel D TXD to FPGA RX
+RISCV_TDO,T18,GPIOL_83,TL5,TL1_TL5,3.3 V,3.3 V LVCMOS,output,no,,secondary_jtag,on-board,,Official development-kit hardened RISC-V JTAG assignment
+UART1_TX,T19,GPIOL_86,TL5,TL1_TL5,3.3 V,3.3 V LVCMOS,output,no,,ft4232,on-board,,FPGA TX to FT4232H channel D RXD
+CLK_40M_FPGA,U17,GPIOL_79_CLK28,TL5,TL1_TL5,3.3 V,3.3 V LVCMOS,input,yes,CLOCK_CAPABLE,clock,on-board,,40 MHz oscillator branch on clock-capable pin
+FTDI_DBG_GPIO,U19,GPIOL_52_PLLIN1,TL1,TL1_TL5,3.3 V,3.3 V LVCMOS,bidirectional,no,PLL_INPUT,ft4232,on-board,,Channel D debug GPIO/test point; PLL-capable
+PMOD1_1,U6,GPIOL_24,BL2,BL2_BL3,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_3v3,JPMOD1,1,PMOD 1 pin 1; plain HVIO GPIO
+RISCV_TDI,V19,GPIOL_46,TL1,TL1_TL5,3.3 V,3.3 V LVCMOS,input,no,,secondary_jtag,on-board,,Official development-kit hardened RISC-V JTAG assignment
+PMOD2_1,V20,GPIOL_45,TL1,TL1_TL5,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_3v3,JPMOD2,1,PMOD 2 pin 1; plain HVIO GPIO
+PMOD1_2,V4,GPIOL_23,BL2,BL2_BL3,3.3 V,3.3 V LVCMOS,bidirectional,no,,pmod_3v3,JPMOD1,2,PMOD 1 pin 2; plain HVIO GPIO
@@ -0,0 +1,228 @@
+ball,official_pin_name,package_bank,bank_class,selected_vccio,io_standard,clock_capability,special_function,status,signal,connector,connector_pin,note
+A11,GPIOR_93_PLLIN1,TR1,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,used,IMU_DRY_SYNC,on-board,,Murata multiplexed Data Ready output / SYNC input
+A12,GPIOR_95_CLK12,TR1,HVIO,3.3 V,3.3 V LVCMOS,yes,CLOCK_CAPABLE,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+A13,GPIOR_94,TR1,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD1_3,JPMOD1,3,PMOD 1 pin 3
+A14,GPIOT_N_55,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD4_2,JPMOD4,2,PMOD 4 pin 2; HSIO pair 55 N
+A16,GPIOT_P_53,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD3_7,JPMOD3,7,PMOD 3 pin 7; HSIO pair 53 P
+A17,GPIOT_N_53,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD3_8,JPMOD3,8,PMOD 3 pin 8; HSIO pair 53 N
+A18,GPIOT_P_57,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD4_7,JPMOD4,7,PMOD 4 pin 7; HSIO pair 57 P
+A19,GPIOT_N_57,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD4_8,JPMOD4,8,PMOD 4 pin 8; HSIO pair 57 N
+A2,GPIOB_P_30_CDI9_PLLIN0,4C,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+A21,GPIOT_N_33_CLK16_N,2C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+A22,GPIOT_N_26,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+A3,GPIOB_N_32,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+A4,GPIOB_P_32,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+A6,GPIOB_N_35,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+A7,GPIOB_N_38_SSL_N,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,QSPI_CS_N,on-board,,SPI-active SSL_N
+A8,GPIOR_170,BR3_BR4,HVIO,3.3 V,3.3 V LVCMOS,no,,used,IMU_SCK,on-board,,SafeSPI mode-0 clock
+A9,GPIOR_171,BR3_BR4,HVIO,3.3 V,3.3 V LVCMOS,no,,used,IMU_MOSI,on-board,,SafeSPI controller-to-sensor data
+B1,GPIOB_P_21,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B10,GPIOR_169,BR3_BR4,HVIO,3.3 V,3.3 V LVCMOS,no,,used,IMU_CS,on-board,,SafeSPI active-low chip select
+B11,GPIOR_143_CLK9,BR0,HVIO,3.0 V,3.0 V LVCMOS,yes,CLOCK_CAPABLE,used,MAX_CLKOUT,on-board,,Source-synchronous ADC capture clock on dedicated clock-capable input
+B12,GPIOR_96_CLK13,TR1,HVIO,3.3 V,3.3 V LVCMOS,yes,CLOCK_CAPABLE,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B14,GPIOT_P_55,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD4_1,JPMOD4,1,PMOD 4 pin 1; HSIO pair 55 P
+B15,GPIOT_P_62_PLLIN0,2E,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B16,GPIOT_N_62,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B17,GPIOT_N_52,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD3_4,JPMOD3,4,PMOD 3 pin 4; HSIO pair 52 N
+B19,GPIOT_N_54,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD3_10,JPMOD3,10,PMOD 3 pin 10; HSIO pair 54 N
+B2,GPIOB_N_30_CDI8,4C,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B20,GPIOT_N_51,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD3_2,JPMOD3,2,PMOD 3 pin 2; HSIO pair 51 N
+B21,GPIOT_P_33_CLK16_P,2C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B22,GPIOT_N_27,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B23,GPIOT_P_26,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B4,GPIOB_N_31,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B5,GPIOB_N_34,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B6,GPIOB_P_35,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+B7,GPIOB_P_38_CDI3,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,used,QSPI_IO3,on-board,,SPI-active CDI3
+B9,GPIOR_168,BR3_BR4,HVIO,3.3 V,3.3 V LVCMOS,no,,used,IMU_MISO,on-board,,SafeSPI sensor-to-controller data
+C10,GPIOR_167,BR3_BR4,HVIO,3.3 V,3.3 V LVCMOS,no,,used,IMU_EXTRESN,on-board,,External active-low reset
+C12,GPIOR_99,TR1,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD1_7,JPMOD1,7,PMOD 1 pin 7
+C13,GPIOR_98,TR1,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD1_8,JPMOD1,8,PMOD 1 pin 8
+C14,GPIOR_97,TR1,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD1_9,JPMOD1,9,PMOD 1 pin 9
+C15,GPIOT_N_59,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+C17,GPIOT_P_52,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD3_3,JPMOD3,3,PMOD 3 pin 3; HSIO pair 52 P
+C18,GPIOT_N_60,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+C19,GPIOT_P_54,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD3_9,JPMOD3,9,PMOD 3 pin 9; HSIO pair 54 P
+C2,GPIOB_N_21,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+C20,GPIOT_P_51,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD3_1,JPMOD3,1,PMOD 3 pin 1; HSIO pair 51 P
+C22,GPIOT_P_27,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+C3,GPIOB_P_27,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+C4,GPIOB_P_31,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+C5,GPIOB_P_34,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+C7,GPIOB_N_41,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+C9,GPIOR_166,BR3_BR4,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD1_4,JPMOD1,4,PMOD 1 pin 4; plain HVIO GPIO
+D1,GPIOB_P_20_CLK7_P,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D10,GPIOR_144,BR0,HVIO,3.0 V,3.0 V LVCMOS,no,,used,MAX_I0,on-board,,ADC I bit 0
+D11,GPIOR_142_CLK8,BR0,HVIO,3.0 V,3.0 V LVCMOS,yes,CLOCK_CAPABLE,used,MAX_I1,on-board,,ADC I bit 1; clock-capable pad retained in same BR0 bank
+D12,GPIOR_100,TR1,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD1_10,JPMOD1,10,PMOD 1 pin 10
+D13,GPIOR_102,TR2,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD2_2,JPMOD2,2,PMOD 2 pin 2
+D15,GPIOT_P_59_PLLIN0,2E,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D16,GPIOT_P_58,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD4_9,JPMOD4,9,PMOD 4 pin 9; HSIO pair 58 P
+D17,GPIOT_N_58,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD4_10,JPMOD4,10,PMOD 4 pin 10; HSIO pair 58 N
+D18,GPIOT_P_60_EXTFB,2E,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D2,GPIOB_N_20_CLK7_N,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D20,GPIOT_N_36_CLK19_N,2C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D21,GPIOT_N_29,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D22,GPIOT_P_25,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D23,GPIOT_N_25,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D3,GPIOB_N_27,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D5,GPIOB_N_37_CDI4,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D6,GPIOB_P_37_CDI5,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D7,GPIOB_P_41,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+D8,GPIOB_N_44_CLK11_N,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E1,GPIOB_P_18_CLK5_P,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E10,GPIOR_145_PLLIN1,BR0,HVIO,3.0 V,3.0 V LVCMOS,no,PLL_INPUT,used,MAX_Q0,on-board,,ADC Q bit 0; PLL-capable pad in same BR0 bank
+E11,GPIOR_140_PLLIN1,BR0,HVIO,3.0 V,3.0 V LVCMOS,no,PLL_INPUT,used,MAX_Q1,on-board,,ADC Q bit 1; PLL-capable pad in same BR0 bank
+E13,GPIOR_103,TR2,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD2_3,JPMOD2,3,PMOD 2 pin 3
+E14,GPIOR_104,TR2,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD2_4,JPMOD2,4,PMOD 2 pin 4
+E15,GPIOR_107,TR2,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD2_9,JPMOD2,9,PMOD 2 pin 9
+E16,GPIOR_105,TR2,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD2_7,JPMOD2,7,PMOD 2 pin 7
+E18,GPIOT_N_61,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E19,GPIOT_N_64_CLK15_N,2E,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E20,GPIOT_P_36_CLK19_P,2C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E21,GPIOT_P_29,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E23,GPIOT_N_23,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E3,GPIOB_P_24_CDI15,4C,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E4,GPIOB_N_36_CDI6,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E5,GPIOB_P_36_CDI7,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E6,GPIOB_N_42,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E8,GPIOB_P_44_CLK11_P,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+E9,GPIOR_165_PLLIN1,BR3_BR4,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F1,GPIOB_N_18_CLK5_N,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F11,GPIOR_141,BR0,HVIO,3.0 V,3.0 V LVCMOS,no,,used,MAX_LD,on-board,,PLL lock status
+F12,GPIOR_101_PLLIN1,TR2,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,used,RISCV_TCK,on-board,,Fabric RISC-V JTAG clock moved off the plain-GPIO PMOD allocation
+F13,GPIOR_106,TR2,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD2_8,JPMOD2,8,PMOD 2 pin 8
+F14,GPIOR_108,TR2,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD2_10,JPMOD2,10,PMOD 2 pin 10
+F16,GPIOR_90,TR0,HVIO,3.0 V,3.0 V LVCMOS,no,,used,MAX_SCLK,on-board,,Three-wire serial clock
+F17,GPIOR_91,TR0,HVIO,3.0 V,3.0 V LVCMOS,no,,used,MAX_CSN,on-board,,Three-wire active-low chip select
+F18,GPIOT_P_61_EXTFB,2E,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F19,GPIOT_P_64_CLK15_P,2E,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F2,GPIOB_P_17_CLK4_P,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F21,GPIOT_P_35_CLK18_P,2C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F22,GPIOT_N_35_CLK18_N,2C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F23,GPIOT_P_23_PLLIN0,2C,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F3,GPIOB_N_24_CDI14,4C,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F4,GPIOB_N_33,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+F6,GPIOB_P_42,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G1,GPIOB_P_23_CBSEL1,4C,HSIO,1.8 V,1.8 V LVCMOS,no,CONFIG_BOOT_SELECT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G15,GPIOR_88_PLLIN1,TR0,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G16,GPIOR_89,TR0,HVIO,3.0 V,3.0 V LVCMOS,no,,used,MAX_SDATA,on-board,,Single bidirectional three-wire serial data; not split MOSI/MISO
+G17,GPIOR_92,TR0,HVIO,3.0 V,3.0 V LVCMOS,no,,used,MAX_SHDN,on-board,,MAX2771 hardware shutdown control
+G19,GPIOT_N_63_CLK14_N,2E,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G2,GPIOB_N_17_CLK4_N,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G20,GPIOT_N_34_CLK17_N,2C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G21,GPIOT_P_28,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G22,GPIOT_N_28,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G4,GPIOB_P_33,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+G5,GPIOB_N_39_CDI2,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,used,QSPI_IO2,on-board,,SPI-active CDI2
+G6,GPIOB_P_39_CCK_PLLIN0,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;DIFFERENTIAL_MEMBER,used,QSPI_SCLK,on-board,,SPI-active CCK; official CCK_PLLIN0 pin
+H18,GPIOT_N_56,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD4_4,JPMOD4,4,PMOD 4 pin 4; HSIO pair 56 N
+H19,GPIOT_P_63_CLK14_P,2E,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+H2,GPIOB_N_23_CBSEL0,4C,HSIO,1.8 V,1.8 V LVCMOS,no,CONFIG_BOOT_SELECT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+H20,GPIOT_P_34_CLK17_P,2C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+H22,GPIOT_P_24_EXTFB,2C,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+H23,GPIOT_N_24,2C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+H3,GPIOB_P_28,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+H4,GPIOB_N_40_CDI0,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,used,QSPI_IO0,on-board,,SPI-active CDI0
+H5,GPIOB_P_40_CDI1_EXTFB,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,used,QSPI_IO1,on-board,,SPI-active CDI1
+J1,GPIOB_P_19_NSTATUS_CLK6_P,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+J18,GPIOT_P_56,2E,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,used,PMOD4_3,JPMOD4,3,PMOD 4 pin 3; HSIO pair 56 P
+J2,GPIOB_N_19_TEST_N_CLK6_N,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,used,FPGA_TEST_N,on-board,,Mandatory external weak pull-up disables test mode during configuration
+J20,GPIOT_P_17,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+J21,GPIOT_P_16,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+J22,GPIOT_P_10_CLK27_P,2B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+J23,GPIOT_N_10_CLK27_N,2B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+J3,GPIOB_N_28,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+J5,GPIOB_N_43_CSI_CLK10_N,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,used,FPGA_CSI,on-board,,Mandatory external weak pull-up selects this FPGA throughout configuration
+J6,GPIOB_P_43_CSO_CLK10_P,4A_4B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K1,GPIOB_P_14_CDI19_CLK1_P,4D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K18,GPIOT_P_49_EXTFB,2D,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K19,GPIOT_N_49,2D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K20,GPIOT_N_17,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K21,GPIOT_N_16,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K23,GPIOT_P_21,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K3,GPIOB_P_29_CDI11_EXTFB,4C,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K4,GPIOB_N_29_CDI10,4C,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K5,GPIOB_P_26_EXTSPICLK,4C,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;EXT_SPI;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+K6,GPIOB_P_25_CDI13,4C,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L1,GPIOB_N_14_CDI18_CLK1_N,4D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L17,GPIOT_P_50_PLLIN0,2D,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L18,GPIOT_N_50,2D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L19,GPIOT_P_20,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L2,GPIOB_P_15_CDI17_CLK2_P,4D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L21,GPIOT_P_11_CLK30_P,2B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L22,GPIOT_N_11_CLK30_N,2B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L23,GPIOT_N_21,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L3,GPIOB_P_11,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L4,GPIOB_N_26_SSU_N,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+L6,GPIOB_N_25_CDI12,4C,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M1,GPIOB_P_09,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M16,GPIOT_P_43,2D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M17,GPIOT_N_43,2D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M19,GPIOT_N_20,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M2,GPIOB_N_15_CDI16_CLK2_N,4D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M20,GPIOT_P_13_PLLIN0,2B,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M21,GPIOT_P_22,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M22,GPIOT_N_22,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M4,GPIOB_N_11,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M5,GPIOB_P_22,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+M6,GPIOB_N_22,4C,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N17,GPIOT_P_40_CLK23_P,2D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N18,GPIOT_N_40_CLK23_N,2D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N19,GPIOT_P_14_EXTFB,2B,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N2,GPIOB_N_09,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N20,GPIOT_N_13,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N22,GPIOT_P_15,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N23,GPIOT_N_15,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N3,GPIOB_P_13_CDI21_CLK0_P,4D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N4,GPIOB_N_12,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N5,GPIOB_P_12,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+N7,GPIOB_P_08_CDI22_EXTFB,4D,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P1,GPIOB_N_16_CLK3_N,4D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P17,GPIOL_84,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,no,,used,UART0_RX,on-board,,FT4232H channel C TXD to FPGA RX
+P18,GPIOL_80_CLK29,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,yes,CLOCK_CAPABLE,used,RISCV_TMS,on-board,,Clock-capable fabric pin; official development-kit assignment
+P2,GPIOB_P_16_CLK3_P,4D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P20,GPIOT_N_14,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P21,GPIOT_P_18,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P22,GPIOT_N_18,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P23,GPIOT_P_09_CLK26_P,2B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P3,GPIOB_N_13_CDI20_CLK0_N,4D,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P5,GPIOB_P_06_CDI26_EXTFB,4D,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P6,GPIOB_P_05_CDI28_PLLIN0,4D,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+P7,GPIOB_N_08,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R1,GPIOB_P_04_CDI30_EXTFB,4D,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R17,GPIOL_85_PLLIN1,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,used,UART0_TX,on-board,,FPGA TX to FT4232H channel C RXD
+R18,GPIOL_87_PLLIN1,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,used,UART1_RX,on-board,,FT4232H channel D TXD to FPGA RX
+R19,GPIOT_P_19,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R20,GPIOT_N_19,2B,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R21,GPIOT_P_12_CLK31_P,2B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R23,GPIOT_N_09_CLK26_N,2B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R3,GPIOB_N_07_CDI23,4D,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R4,GPIOB_P_07_CDI24_PLLIN0,4D,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R5,GPIOB_N_06_CDI25,4D,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+R6,GPIOB_N_05_CDI27,4D,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+T1,GPIOB_N_04_CDI29,4D,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+T18,GPIOL_83,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,no,,used,RISCV_TDO,on-board,,Official development-kit hardened RISC-V JTAG assignment
+T19,GPIOL_86,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,no,,used,UART1_TX,on-board,,FPGA TX to FT4232H channel D RXD
+T2,GPIOB_N_10,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+T21,GPIOT_N_12_CLK31_N,2B,HSIO,1.8 V,1.8 V LVCMOS,yes,CLOCK_CAPABLE;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+T22,GPIOT_P_08_PLLIN0,2A,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+T23,GPIOT_N_08,2A,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+T3,GPIOB_P_10,4D,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+T4,GPIOL_27_CLK25,BL2_BL3,HVIO,3.3 V,3.3 V LVCMOS,yes,CLOCK_CAPABLE,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+U1,GPIOB_N_03_CDI31,4D,HSIO,1.8 V,1.8 V LVCMOS,no,CORE_DATA_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+U17,GPIOL_79_CLK28,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,yes,CLOCK_CAPABLE,used,CLK_40M_FPGA,on-board,,40 MHz oscillator branch on clock-capable pin
+U19,GPIOL_52_PLLIN1,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,used,FTDI_DBG_GPIO,on-board,,Channel D debug GPIO/test point; PLL-capable
+U2,GPIOB_P_03_PLLIN0,4D,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_INPUT;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+U21,GPIOT_P_05,2A,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+U22,GPIOT_N_05,2A,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+U4,GPIOL_25_PLLIN1,BL2_BL3,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+U5,GPIOL_34_PLLIN1,BL2_BL3,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+U6,GPIOL_24,BL2_BL3,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD1_1,JPMOD1,1,PMOD 1 pin 1; plain HVIO GPIO
+V19,GPIOL_46,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,no,,used,RISCV_TDI,on-board,,Official development-kit hardened RISC-V JTAG assignment
+V2,GPIOL_26_CLK24,BL2_BL3,HVIO,3.3 V,3.3 V LVCMOS,yes,CLOCK_CAPABLE,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+V20,GPIOL_45,TL1_TL5,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD2_1,JPMOD2,1,PMOD 2 pin 1; plain HVIO GPIO
+V22,GPIOT_P_07_EXTFB,2A,HSIO,1.8 V,1.8 V LVCMOS,no,PLL_EXTFB;DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+V23,GPIOT_N_07,2A,HSIO,1.8 V,1.8 V LVCMOS,no,DIFFERENTIAL_MEMBER,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+V3,GPIOL_32_PLLIN1,BL2_BL3,HVIO,3.3 V,3.3 V LVCMOS,no,PLL_INPUT,unused,,,,Unused fabric GPIO; left unconnected at the BGA
+V4,GPIOL_23,BL2_BL3,HVIO,3.3 V,3.3 V LVCMOS,no,,used,PMOD1_2,JPMOD1,2,PMOD 1 pin 2; plain HVIO GPIO
@@ -0,0 +1,97 @@
+# Donanım mimarisi
+
+## Ana dosyalar
+
+- `board.kicad_sch`: güncel hiyerarşik KiCad 10 şeması.
+- `board.kicad_pcb`: güncel, placed fakat unrouted PCB.
+- `board.kicad_pro`: net-class, diff-pair ve proje ayarları.
+- `board.kicad_dru`: üreticiye ve kontrollü empedansa özgü DRC kuralları.
+- `board.kicad_sym` ve `board.pretty/`: projeye özel sembol ve footprintler.
+
+`board_prerouted`, `board_plane_stitched` ve eski `board_power_routed` dosyaları
+ara çalışma ürünleridir. Güncel reset/netlist revizyonundan önce oluşturulmuş
+routing dosyaları yeni tasarım için kaynak kabul edilmez.
+
+## Güç mimarisi
+
+1. USB-C VBUS veya harici 5 V koruma ve power-path devresinden sonra `SYS5`
+   rayını oluşturur.
+2. TPS6287B15, FPGA core/VCCA/VDD_SOC için 0.95 V üretir.
+3. `CORE_PG`, LM3880 sıralayıcıyı başlatır.
+4. LM3880 önce TPS62867 1.8 V rayını, ardından TPS62867 3.3 V rayını etkinleştirir.
+5. 3.3 V üzerinden MAX2771 ve ilgili FPGA bankları için ayrı düşük gürültülü
+   3.0 V LDO'lar beslenir.
+6. TPS3808, `VCC3V0_DIG` rayını izler ve geçerli olduktan sonra 20 ms gecikmeyle
+   power-good verir.
+7. Core PG, 1.8 V PG, 3.3 V PG, TPS3808 sonucu ve LM3880 FLAG3,
+   `ALL_FPGA_POWER_OK` mantığında birlikte doğrulanır.
+
+FPGA besleme rayları:
+
+| Ray | Görev |
+|---|---|
+| `VCC0V95` | FPGA core, VCCA ve SoC çekirdeği |
+| `VCC1V8` | VCCAUX, konfigürasyon/flash ve 1.8 V HSIO bankları |
+| `VCC3V3` | 3.3 V FPGA I/O bankları ve çevre birimleri |
+| `VCC3V0_DIG` | MAX2771 dijital ve ilgili 3.0 V FPGA bankı |
+| `VCC3V0_RF` | MAX2771 analog RF beslemesi |
+| `VCC3V0_CLK` | Düşük gürültülü saat beslemesi |
+| `VCC3V3_AUX` | Her zaman açık supervisor ve USB debug mantığı |
+
+## Reset mimarisi
+
+`FPGA_CRESET_N`, 1.8 V'a pull-up edilen aktif-düşük konfigürasyon resetidir.
+Aşağıdaki üç bağımsız SN74LVC1G07 açık-drenç yolu bu hattı yalnızca aşağı
+çekebilir:
+
+- FT4232H interface 1 `BDBUS4` yazılım reset isteği.
+- `ALL_FPGA_POWER_OK` geçersiz olduğunda power-fault reseti.
+- Filtrelenmiş kart üstü buton veya `J4 EXT RESET_N` harici reset isteği.
+
+`J4` harici kaynağı aktif-düşük open-drain/contact-closure kullanımına göre
+tasarlanmıştır. Harici pine gerilim uygulanmamalı; pin GND'ye çekilmelidir.
+
+## JTAG ve USB debug
+
+| FT4232H arayüzü | Görev | Sinyaller |
+|---|---|---|
+| Interface 0 / A | RISC-V JTAG | ADBUS0..3 |
+| Interface 1 / B | FPGA hard JTAG | BDBUS0..3 |
+| Interface 1 / BDBUS4 | FPGA reset | Aktif-düşük reset isteği |
+| Interface 2 / C | UART0 | TX/RX |
+| Interface 3 / D | UART1 ve debug GPIO | TX/RX/DBG |
+
+FTDI her zaman açık yardımcı raydan beslenir. FPGA'ya doğru sürülen sinyaller
+FPGA 3.3 V rayından beslenen Ioff özellikli bufferlardan geçer. Bu bufferların
+enable girişi yalnızca `ALL_FPGA_POWER_OK` geçerliyken açılır; kapalı FPGA I/O
+pinlerinin debug arayüzü üzerinden back-power edilmesi engellenir.
+
+Hard JTAG TCK/TMS/TDI/TDO ve RISC-V JTAG sinyallerinde 10 kohm idle pull-up,
+seri hatlarda 33 ohm kaynak sönümleme dirençleri bulunur. Ayrı ARM/JTAG headerı
+yoktur.
+
+## PMOD ve FPGA pin politikası
+
+- `JPMOD1`, `JPMOD2`: Digilent 2x6, 3.3 V.
+- `JPMOD3`, `JPMOD4`: Digilent 2x6, 1.8 V.
+- Her PMOD'da 8 GPIO, 2 GND ve 2 besleme pini vardır.
+- Konfigürasyon, PLL feedback, özel clock ve kartta kullanılan MAX2771/IMU
+  pinleri PMOD tahsisine dahil edilmez.
+- Kesin ball/net eşlemesi `../docs/ti375_pinout.csv` dosyasındadır.
+
+## RF ve yüksek hızlı routing kuralları
+
+- RF katı üst katmanda, JLC08161H-3313 stackup için 0.164 mm genişlik ve
+  0.200 mm coplanar GND aralığıyla 50 ohm CPWG olarak tasarlanır.
+- SMA, ESD, bias-tee, SAW ve MAX2771 MIXIN_HI arasındaki RF güzergâhında dijital
+  route veya via kullanılmaz.
+- USB2 diferansiyel çift 0.135 mm hat ve 0.150 mm coupled gap kuralındadır.
+- RF ve USB geometrisi `scripts/finalize_routing.py` tarafından deterministik
+  olarak kurulur; Freerouter çıktısındaki kritik hatlar kullanılmaz.
+- L2 ve L7 kesintisiz GND referans katmanlarıdır. L4 bölünmüş DC güç katmanıdır.
+
+## Üretime çıkış şartı
+
+Bu revizyonda placement kontrolleri geçmiştir fakat `board.kicad_pcb` üzerinde
+track yoktur. Üretim öncesinde routing akışı tamamlanmalı; zone'lar doldurulmalı;
+ERC, DRC, schematic parity, Gerber ve drill incelemesi tekrar yapılmalıdır.
@@ -0,0 +1,48 @@
+(version 1)
+
+# The edge-launch SMA copper must reach the routed board edge by construction.
+(rule "J2 edge-launch lands"
+    (condition "A.Reference == 'J2' || B.Reference == 'J2'")
+    (constraint edge_clearance (min -0.01mm)))
+
+# The manufacturer USB-C locating holes are 0.194 mm from grounded shell
+# lands.  This exception is internal to the qualified connector footprint.
+(rule "USB-C locating-hole clearance"
+    (condition "A.Reference == 'J1' && B.Reference == 'J1'")
+    (constraint hole_clearance (min 0.19mm)))
+
+# RZV0024A is an ultra-dense high-current package.  Its adjusted corner lands
+# and thermal zones meet the selected JLCPCB 0.10-mm copper rule.
+(rule "TPS6287B RZV internal clearance"
+    (condition "A.Reference == 'U13' && B.Reference == 'U13'")
+    (constraint clearance (min 0.10mm)))
+
+# A 0.45-mm dogbone via at the centre of four 0.8-mm-pitch BGA lands has
+# 0.1407-mm geometric clearance.  This local rule is still well above the
+# selected fabricator's 0.10-mm copper minimum; clocks retain 0.15 mm outside
+# the U1 escape field.
+(rule "Ti375 0.8-mm BGA dogbone clearance"
+    (condition "A.Reference == 'U1' || B.Reference == 'U1'")
+    (constraint clearance (min 0.14mm)))
+
+# JLC08161H-3313 L1/L2 geometry.  Net-class widths are routing defaults only;
+# these rules make the controlled-impedance geometries actual DRC limits.
+(rule "GNSS 50-ohm CPWG geometry"
+    (condition "A.NetClass == 'RF50_CPWG'")
+    (constraint track_width (min 0.164mm) (opt 0.164mm) (max 0.164mm)))
+
+(rule "GNSS RF stays on top layer"
+    (condition "A.NetClass == 'RF50_CPWG' && A.Type == 'Track' && A.Layer != 'F.Cu'")
+    (constraint disallow track))
+
+(rule "USB2 90-ohm differential geometry"
+    (condition "A.NetClass == 'USB90_DIFF'")
+    (constraint track_width (min 0.135mm) (opt 0.135mm) (max 0.135mm)))
+
+(rule "USB2 coupled gap"
+    (condition "A.NetClass == 'USB90_DIFF' && AB.isCoupledDiffPair()")
+    (constraint diff_pair_gap (min 0.15mm) (opt 0.15mm) (max 0.15mm)))
+
+(rule "Clock trunk width outside Ti375 escape"
+    (condition "A.NetClass == 'CLOCK' && A.Type == 'Track' && !A.insideCourtyard('U1')")
+    (constraint track_width (min 0.15mm)))
@@ -0,0 +1,576 @@
+{
+  "board": {
+    "3dviewports": [],
+    "design_settings": {
+      "defaults": {
+        "apply_defaults_to_fp_barcodes": false,
+        "apply_defaults_to_fp_dimensions": false,
+        "apply_defaults_to_fp_fields": false,
+        "apply_defaults_to_fp_shapes": false,
+        "apply_defaults_to_fp_text": false,
+        "board_outline_line_width": 0.05,
+        "copper_line_width": 0.2,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.05,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": true,
+          "text_position": 0,
+          "units_format": 0
+        },
+        "fab_line_width": 0.1,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.1,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.8,
+          "height": 1.27,
+          "width": 1.27
+        },
+        "silk_line_width": 0.1,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.1,
+        "silk_text_upright": false,
+        "zones": {
+          "border_display_style": 2,
+          "border_hatch_pitch": 0.5,
+          "corner_radius": 0.0,
+          "corner_smoothing": 0,
+          "fill_mode": 0,
+          "hatch_gap": 1.5,
+          "hatch_orientation": 0.0,
+          "hatch_smoothing_level": 0,
+          "hatch_smoothing_value": 0.1,
+          "hatch_thickness": 1.0,
+          "min_clearance": 0.5,
+          "min_island_area": 10.0,
+          "min_thickness": 0.25,
+          "pad_connection": 1,
+          "remove_islands": 0,
+          "thermal_relief_gap": 0.5,
+          "thermal_relief_spoke_width": 0.5
+        }
+      },
+      "diff_pair_dimensions": [],
+      "drc_exclusions": [],
+      "meta": {
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "connection_width": "warning",
+        "copper_edge_clearance": "error",
+        "copper_sliver": "warning",
+        "courtyards_overlap": "error",
+        "creepage": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint": "error",
+        "footprint_filters_mismatch": "ignore",
+        "footprint_symbol_field_mismatch": "warning",
+        "footprint_symbol_mismatch": "warning",
+        "footprint_type_mismatch": "ignore",
+        "hole_clearance": "error",
+        "hole_to_hole": "warning",
+        "holes_co_located": "warning",
+        "invalid_outline": "error",
+        "isolated_copper": "warning",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "lib_footprint_issues": "warning",
+        "lib_footprint_mismatch": "warning",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "mirrored_text_on_front_layer": "warning",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "missing_tuning_profile": "warning",
+        "net_conflict": "warning",
+        "nonmirrored_text_on_back_layer": "warning",
+        "npth_inside_courtyard": "error",
+        "padstack": "warning",
+        "pth_inside_courtyard": "error",
+        "shorting_items": "error",
+        "silk_edge_clearance": "warning",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "solder_mask_bridge": "error",
+        "starved_thermal": "error",
+        "text_height": "warning",
+        "text_on_edge_cuts": "error",
+        "text_thickness": "warning",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_angle": "error",
+        "track_dangling": "warning",
+        "track_not_centered_on_via": "ignore",
+        "track_on_post_machined_layer": "error",
+        "track_segment_length": "error",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "tuning_profile_track_geometries": "ignore",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zones_intersect": "error"
+      },
+      "rules": {
+        "max_error": 0.005,
+        "min_clearance": 0.1,
+        "min_connection": 0.0,
+        "min_copper_edge_clearance": 0.25,
+        "min_groove_width": 0.0,
+        "min_hole_clearance": 0.19,
+        "min_hole_to_hole": 0.25,
+        "min_microvia_diameter": 0.2,
+        "min_microvia_drill": 0.1,
+        "min_resolved_spokes": 2,
+        "min_silk_clearance": 0.0,
+        "min_text_height": 0.8,
+        "min_text_thickness": 0.08,
+        "min_through_hole_diameter": 0.225,
+        "min_track_width": 0.1,
+        "min_via_annular_width": 0.1,
+        "min_via_diameter": 0.45,
+        "solder_mask_to_copper_clearance": 0.0,
+        "use_height_for_length_calcs": true
+      },
+      "teardrop_options": [
+        {
+          "td_onpthpad": true,
+          "td_onroundshapesonly": false,
+          "td_onsmdpad": true,
+          "td_ontrackend": false,
+          "td_onvia": true
+        }
+      ],
+      "teardrop_parameters": [
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_on_pad_in_zone": false,
+          "td_target_name": "td_round_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_on_pad_in_zone": false,
+          "td_target_name": "td_rect_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_on_pad_in_zone": false,
+          "td_target_name": "td_track_end",
+          "td_width_to_size_filter_ratio": 0.9
+        }
+      ],
+      "track_widths": [],
+      "tuning_pattern_settings": {
+        "diff_pair_defaults": {
+          "corner_radius_percentage": 80,
+          "corner_style": 1,
+          "max_amplitude": 1.0,
+          "min_amplitude": 0.2,
+          "single_sided": false,
+          "spacing": 1.0
+        },
+        "diff_pair_skew_defaults": {
+          "corner_radius_percentage": 80,
+          "corner_style": 1,
+          "max_amplitude": 1.0,
+          "min_amplitude": 0.2,
+          "single_sided": false,
+          "spacing": 0.6
+        },
+        "single_track_defaults": {
+          "corner_radius_percentage": 80,
+          "corner_style": 1,
+          "max_amplitude": 1.0,
+          "min_amplitude": 0.2,
+          "single_sided": false,
+          "spacing": 0.6
+        }
+      },
+      "via_dimensions": [],
+      "zones_allow_external_fillets": false
+    },
+    "ipc2581": {
+      "bom_rev": "",
+      "dist": "",
+      "distpn": "",
+      "internal_id": "",
+      "mfg": "",
+      "mpn": "",
+      "sch_revision": ""
+    },
+    "layer_pairs": [],
+    "layer_presets": [],
+    "viewports": []
+  },
+  "boards": [],
+  "component_class_settings": {
+    "assignments": [],
+    "meta": {
+      "version": 0
+    },
+    "sheet_component_classes": {
+      "enabled": false
+    }
+  },
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "board.kicad_pro",
+    "version": 3
+  },
+  "net_settings": {
+    "classes": [
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+        "clearance": 0.1,
+        "diff_pair_gap": 0.15,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.135,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "priority": 2147483647,
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.12,
+        "tuning_profile": "",
+        "via_diameter": 0.45,
+        "via_drill": 0.225,
+        "wire_width": 6
+      },
+      {
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+        "clearance": 0.1,
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+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "BGA_ESCAPE",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "priority": -1,
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.1,
+        "tuning_profile": "",
+        "via_diameter": 0.45,
+        "via_drill": 0.225,
+        "wire_width": 6
+      },
+      {
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+        "clearance": 0.15,
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+        "diff_pair_width": 0.2,
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+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "CLOCK",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "priority": -1,
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.15,
+        "tuning_profile": "",
+        "via_diameter": 0.45,
+        "via_drill": 0.225,
+        "wire_width": 6
+      },
+      {
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+        "clearance": 0.1,
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+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "POWER",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "priority": -1,
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.4,
+        "tuning_profile": "",
+        "via_diameter": 0.45,
+        "via_drill": 0.225,
+        "wire_width": 6
+      },
+      {
+        "bus_width": 12,
+        "clearance": 0.2,
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+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "RF50_CPWG",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "priority": -1,
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.164,
+        "tuning_profile": "",
+        "via_diameter": 0.45,
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+        "wire_width": 6
+      },
+      {
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+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "USB90_DIFF",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "priority": -1,
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.135,
+        "tuning_profile": "",
+        "via_diameter": 0.45,
+        "via_drill": 0.225,
+        "wire_width": 6
+      }
+    ],
+    "meta": {
+      "version": 5
+    },
+    "net_colors": null,
+    "netclass_assignments": null,
+    "netclass_patterns": [
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+        "netclass": "RF50_CPWG",
+        "pattern": "RF_SMA"
+      },
+      {
+        "netclass": "RF50_CPWG",
+        "pattern": "RF_PRE_SAW"
+      },
+      {
+        "netclass": "RF50_CPWG",
+        "pattern": "RF_POST_SAW"
+      },
+      {
+        "netclass": "RF50_CPWG",
+        "pattern": "MAX_MIXIN_HI"
+      },
+      {
+        "netclass": "USB90_DIFF",
+        "pattern": "USB_D_P"
+      },
+      {
+        "netclass": "USB90_DIFF",
+        "pattern": "USB_D_N"
+      },
+      {
+        "netclass": "USB90_DIFF",
+        "pattern": "FTDI_D_P"
+      },
+      {
+        "netclass": "USB90_DIFF",
+        "pattern": "FTDI_D_N"
+      },
+      {
+        "netclass": "CLOCK",
+        "pattern": "MAX_CLKOUT*"
+      },
+      {
+        "netclass": "CLOCK",
+        "pattern": "MAX_SCLK*"
+      },
+      {
+        "netclass": "CLOCK",
+        "pattern": "MAX_ADC_CLKIN"
+      },
+      {
+        "netclass": "CLOCK",
+        "pattern": "QSPI_SCLK"
+      },
+      {
+        "netclass": "CLOCK",
+        "pattern": "CLK_40M_FPGA"
+      },
+      {
+        "netclass": "CLOCK",
+        "pattern": "OSC40_OUT"
+      },
+      {
+        "netclass": "CLOCK",
+        "pattern": "TCXO16_OUT"
+      },
+      {
+        "netclass": "CLOCK",
+        "pattern": "FTDI_OSC12"
+      },
+      {
+        "netclass": "CLOCK",
+        "pattern": "FTDI_OSCI"
+      },
+      {
+        "netclass": "CLOCK",
+        "pattern": "IMU_SCK*"
+      },
+      {
+        "netclass": "CLOCK",
+        "pattern": "*TCK*"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "VCC*"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "SYS5"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "VBUS_RAW"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "USB5_PROT"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "EXT5_*"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "GND"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "CORE_SW"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "BUCK1V8_SW"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "BUCK3V3_SW"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "ANT_BIAS_SEL"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "ANT_BIAS_SW"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "FTDI_1V8"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "FTDI_VPHY"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "FTDI_VPLL"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "IMU_3V3"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "IMU_VREGA2"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "IMU_VREGD"
+      },
+      {
+        "netclass": "POWER",
+        "pattern": "USB_SHIELD"
+      },
+      {
+        "netclass": "BGA_ESCAPE",
+        "pattern": "EXP_*"
+      },
+      {
+        "netclass": "BGA_ESCAPE",
+        "pattern": "PMOD*"
+      }
+    ]
+  },
+  "pcbnew": {
+    "last_paths": {
+      "idf": "",
+      "netlist": "",
+      "plot": "",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "bus_aliases": {},
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "top_level_sheets": []
+  },
+  "sheets": [],
+  "text_variables": {},
+  "tuning_profiles": {
+    "meta": {
+      "version": 0
+    },
+    "tuning_profiles_impedance_geometric": []
+  }
+}
@@ -0,0 +1,31 @@
+(footprint "Amphenol_20021121_00010C4LF"
+  (version 20240108)
+  (generator "board-footprints")
+  (layer "F.Cu")
+  (descr "Amphenol Minitek127 20021121-00010C4LF vertical SMT 2x5")
+  (attr smd)
+  (property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
+    (effects (font (size 1 1) (thickness 0.15))))
+  (property "Value" "" (at 0 5 0) (layer "F.Fab") hide
+    (effects (font (size 1 1) (thickness 0.15))))
+  (fp_rect (start -3.5 -2.3) (end 3.5 2.3)
+    (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
+  (fp_rect (start -3.7 -3) (end 3.7 3)
+    (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
+  (fp_line (start -3.5 -2.35) (end 3.5 -2.35) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 3.5 -2.35) (end 3.5 2.35) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 3.5 2.35) (end -3.5 2.35) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start -3.5 2.35) (end -3.5 -2.35) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_circle (center -3.8 2.3) (end -3.55 2.3) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
+  (pad "1" smd roundrect (at -2.54 1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "2" smd roundrect (at -2.54 -1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "3" smd roundrect (at -1.27 1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "4" smd roundrect (at -1.27 -1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "5" smd roundrect (at 0 1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "6" smd roundrect (at 0 -1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "7" smd roundrect (at 1.27 1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "8" smd roundrect (at 1.27 -1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "9" smd roundrect (at 2.54 1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "10" smd roundrect (at 2.54 -1.95) (size 0.76 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (embedded_fonts no)
+)
@@ -0,0 +1,23 @@
+(footprint "Coilcraft_XEL4030"
+  (version 20240108)
+  (generator "board-footprints")
+  (layer "F.Cu")
+  (descr "Coilcraft XEL4030 recommended land, March 2026")
+  (attr smd)
+  (property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
+    (effects (font (size 1 1) (thickness 0.15))))
+  (property "Value" "" (at 0 5 0) (layer "F.Fab") hide
+    (effects (font (size 1 1) (thickness 0.15))))
+  (fp_rect (start -2 -2) (end 2 2)
+    (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
+  (fp_rect (start -2.5 -2.4) (end 2.5 2.4)
+    (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
+  (fp_line (start -2.075 -2.075) (end 2.075 -2.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 2.075 -2.075) (end 2.075 2.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 2.075 2.075) (end -2.075 2.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start -2.075 2.075) (end -2.075 -2.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_circle (center -2.2 -2) (end -1.95 -2) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
+  (pad "1" smd roundrect (at -1.675 0) (size 0.98 3.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "2" smd roundrect (at 1.675 0) (size 0.98 3.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (embedded_fonts no)
+)
@@ -0,0 +1,30 @@
+(footprint "Digilent_PMOD_2x6_P2.54mm"
+  (version 20240108)
+  (generator "board-footprints")
+  (layer "F.Cu")
+  (descr "Digilent PMOD 2x6, 2.54-mm pitch, row-wise pins 1-6 and 7-12")
+  (attr through_hole)
+  (property "Reference" "REF**" (at 6.35 -2.5 0) (layer "F.SilkS")
+    (effects (font (size 1 1) (thickness 0.15))))
+  (property "Value" "" (at 6.35 5 0) (layer "F.Fab") hide
+    (effects (font (size 1 1) (thickness 0.15))))
+  (fp_rect (start -1.27 -1.27) (end 13.97 3.81)
+    (stroke (width 0.15) (type default)) (fill none) (layer "F.SilkS"))
+  (fp_rect (start -1.5 -1.5) (end 14.2 4.04)
+    (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
+  (fp_circle (center -0.8 -0.8) (end -0.5 -0.8)
+    (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
+  (pad "1" thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
+  (pad "2" thru_hole circle (at 2.54 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
+  (pad "3" thru_hole circle (at 5.08 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
+  (pad "4" thru_hole circle (at 7.62 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
+  (pad "5" thru_hole circle (at 10.16 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
+  (pad "6" thru_hole circle (at 12.7 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
+  (pad "7" thru_hole circle (at 0 2.54) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
+  (pad "8" thru_hole circle (at 2.54 2.54) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
+  (pad "9" thru_hole circle (at 5.08 2.54) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
+  (pad "10" thru_hole circle (at 7.62 2.54) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
+  (pad "11" thru_hole circle (at 10.16 2.54) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
+  (pad "12" thru_hole circle (at 12.7 2.54) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))
+  (embedded_fonts no)
+)
@@ -0,0 +1,25 @@
+(footprint "Epson_TG2016SMN"
+  (version 20240108)
+  (generator "board-footprints")
+  (layer "F.Cu")
+  (descr "Epson TG2016SMN official 2.0 x 1.6 mm land")
+  (attr smd)
+  (property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
+    (effects (font (size 1 1) (thickness 0.15))))
+  (property "Value" "" (at 0 5 0) (layer "F.Fab") hide
+    (effects (font (size 1 1) (thickness 0.15))))
+  (fp_rect (start -1 -0.8) (end 1 0.8)
+    (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
+  (fp_rect (start -1.5 -1.3) (end 1.5 1.3)
+    (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
+  (fp_line (start -1.075 -0.875) (end 1.075 -0.875) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 1.075 -0.875) (end 1.075 0.875) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 1.075 0.875) (end -1.075 0.875) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start -1.075 0.875) (end -1.075 -0.875) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_circle (center -1.35 -0.85) (end -1.1 -0.85) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
+  (pad "1" smd roundrect (at -0.825 -0.565) (size 0.6 0.75) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "2" smd roundrect (at -0.825 0.565) (size 0.6 0.75) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "3" smd roundrect (at 0.825 0.565) (size 0.6 0.75) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "4" smd roundrect (at 0.825 -0.565) (size 0.6 0.75) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (embedded_fonts no)
+)
@@ -0,0 +1,94 @@
+(footprint "FTDI_VQFN56_EP5p9"
+  (version 20240108)
+  (generator "board-footprints")
+  (layer "F.Cu")
+  (descr "FTDI FT4232H-56Q VQFN56 land from TN_166; 5.9-mm EP")
+  (attr smd)
+  (property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
+    (effects (font (size 1 1) (thickness 0.15))))
+  (property "Value" "" (at 0 5 0) (layer "F.Fab") hide
+    (effects (font (size 1 1) (thickness 0.15))))
+  (fp_rect (start -4 -4) (end 4 4)
+    (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
+  (fp_rect (start -4.6 -4.6) (end 4.6 4.6)
+    (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
+  (fp_line (start -4.075 -4.075) (end 4.075 -4.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 4.075 -4.075) (end 4.075 4.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 4.075 4.075) (end -4.075 4.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start -4.075 4.075) (end -4.075 -4.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_circle (center -4.4 -3.85) (end -4.15 -3.85) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
+  (pad "1" smd roundrect (at -4 -3.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "2" smd roundrect (at -4 -2.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "3" smd roundrect (at -4 -2.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "4" smd roundrect (at -4 -1.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "5" smd roundrect (at -4 -1.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "6" smd roundrect (at -4 -0.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "7" smd roundrect (at -4 -0.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "8" smd roundrect (at -4 0.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "9" smd roundrect (at -4 0.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "10" smd roundrect (at -4 1.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "11" smd roundrect (at -4 1.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "12" smd roundrect (at -4 2.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "13" smd roundrect (at -4 2.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "14" smd roundrect (at -4 3.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "15" smd roundrect (at -3.25 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "16" smd roundrect (at -2.75 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "17" smd roundrect (at -2.25 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "18" smd roundrect (at -1.75 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "19" smd roundrect (at -1.25 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "20" smd roundrect (at -0.75 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "21" smd roundrect (at -0.25 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "22" smd roundrect (at 0.25 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "23" smd roundrect (at 0.75 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "24" smd roundrect (at 1.25 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "25" smd roundrect (at 1.75 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "26" smd roundrect (at 2.25 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "27" smd roundrect (at 2.75 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "28" smd roundrect (at 3.25 4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "29" smd roundrect (at 4 3.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "30" smd roundrect (at 4 2.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "31" smd roundrect (at 4 2.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "32" smd roundrect (at 4 1.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "33" smd roundrect (at 4 1.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "34" smd roundrect (at 4 0.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "35" smd roundrect (at 4 0.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "36" smd roundrect (at 4 -0.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "37" smd roundrect (at 4 -0.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "38" smd roundrect (at 4 -1.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "39" smd roundrect (at 4 -1.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "40" smd roundrect (at 4 -2.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "41" smd roundrect (at 4 -2.75) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "42" smd roundrect (at 4 -3.25) (size 0.8 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "43" smd roundrect (at 3.25 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "44" smd roundrect (at 2.75 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "45" smd roundrect (at 2.25 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "46" smd roundrect (at 1.75 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "47" smd roundrect (at 1.25 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "48" smd roundrect (at 0.75 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "49" smd roundrect (at 0.25 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "50" smd roundrect (at -0.25 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "51" smd roundrect (at -0.75 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "52" smd roundrect (at -1.25 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "53" smd roundrect (at -1.75 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "54" smd roundrect (at -2.25 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "55" smd roundrect (at -2.75 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "56" smd roundrect (at -3.25 -4) (size 0.25 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "57" smd rect (at 0 0) (size 5.9 5.9) (layers "F.Cu" "F.Mask"))
+  (pad "" smd roundrect (at -2.22 -2.22) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "" smd roundrect (at -2.22 -0.74) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "" smd roundrect (at -2.22 0.74) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "" smd roundrect (at -2.22 2.22) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "" smd roundrect (at -0.74 -2.22) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "" smd roundrect (at -0.74 -0.74) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "" smd roundrect (at -0.74 0.74) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "" smd roundrect (at -0.74 2.22) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "" smd roundrect (at 0.74 -2.22) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "" smd roundrect (at 0.74 -0.74) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "" smd roundrect (at 0.74 0.74) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "" smd roundrect (at 0.74 2.22) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "" smd roundrect (at 2.22 -2.22) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "" smd roundrect (at 2.22 -0.74) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "" smd roundrect (at 2.22 0.74) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "" smd roundrect (at 2.22 2.22) (size 1.2 1.2) (layers "F.Paste") (roundrect_rratio 0.15))
+  (embedded_fonts no)
+)
@@ -0,0 +1,23 @@
+(footprint "Kyocera_600L_0402"
+  (version 20240108)
+  (generator "board-footprints")
+  (layer "F.Cu")
+  (descr "KYOCERA AVX 600L 0402 recommended land")
+  (attr smd)
+  (property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
+    (effects (font (size 1 1) (thickness 0.15))))
+  (property "Value" "" (at 0 5 0) (layer "F.Fab") hide
+    (effects (font (size 1 1) (thickness 0.15))))
+  (fp_rect (start -0.5 -0.25) (end 0.5 0.25)
+    (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
+  (fp_rect (start -1.1 -0.6) (end 1.1 0.6)
+    (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
+  (fp_line (start -0.575 -0.325) (end 0.575 -0.325) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 0.575 -0.325) (end 0.575 0.325) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 0.575 0.325) (end -0.575 0.325) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start -0.575 0.325) (end -0.575 -0.325) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_circle (center -0.7 -0.25) (end -0.45 -0.25) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
+  (pad "1" smd roundrect (at -0.65 0) (size 0.9 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "2" smd roundrect (at 0.65 0) (size 0.9 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (embedded_fonts no)
+)
@@ -0,0 +1,26 @@
+(footprint "Kyocera_SF14_5pad"
+  (version 20240108)
+  (generator "board-footprints")
+  (layer "F.Cu")
+  (descr "KYOCERA SF14-1582M5UUS2 SAW; official five-pad land")
+  (attr smd)
+  (property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
+    (effects (font (size 1 1) (thickness 0.15))))
+  (property "Value" "" (at 0 5 0) (layer "F.Fab") hide
+    (effects (font (size 1 1) (thickness 0.15))))
+  (fp_rect (start -0.55 -0.45) (end 0.55 0.45)
+    (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
+  (fp_rect (start -0.9 -0.75) (end 0.9 0.75)
+    (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
+  (fp_line (start -0.6 -0.5) (end 0.6 -0.5) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 0.6 -0.5) (end 0.6 0.5) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 0.6 0.5) (end -0.6 0.5) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start -0.6 0.5) (end -0.6 -0.5) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_circle (center -0.8 0) (end -0.55 0) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
+  (pad "1" smd roundrect (at -0.5 0) (size 0.25 0.325) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "2" smd roundrect (at 0 0.2875) (size 0.25 0.325) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "3" smd roundrect (at 0.5 0.2875) (size 0.25 0.325) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "4" smd roundrect (at 0.5 -0.2875) (size 0.25 0.325) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "5" smd roundrect (at 0 -0.2875) (size 0.25 0.325) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (embedded_fonts no)
+)
@@ -0,0 +1,23 @@
+(footprint "Murata_DFE201612E"
+  (version 20240108)
+  (generator "board-footprints")
+  (layer "F.Cu")
+  (descr "Murata DFE201612E recommended land J(E)TE243A-0006")
+  (attr smd)
+  (property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
+    (effects (font (size 1 1) (thickness 0.15))))
+  (property "Value" "" (at 0 5 0) (layer "F.Fab") hide
+    (effects (font (size 1 1) (thickness 0.15))))
+  (fp_rect (start -1 -0.8) (end 1 0.8)
+    (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
+  (fp_rect (start -1.4 -1.2) (end 1.4 1.2)
+    (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
+  (fp_line (start -1.075 -0.875) (end 1.075 -0.875) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 1.075 -0.875) (end 1.075 0.875) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 1.075 0.875) (end -1.075 0.875) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start -1.075 0.875) (end -1.075 -0.875) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_circle (center -1.2 -0.8) (end -0.95 -0.8) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
+  (pad "1" smd roundrect (at -0.8 0) (size 0.8 1.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "2" smd roundrect (at 0.8 0) (size 0.8 1.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (embedded_fonts no)
+)
@@ -0,0 +1,47 @@
+(footprint "Murata_SCH16T_K01"
+  (version 20240108)
+  (generator "board-footprints")
+  (layer "F.Cu")
+  (descr "Murata SCH16T-K01-1 official PCB land pattern")
+  (attr smd)
+  (property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
+    (effects (font (size 1 1) (thickness 0.15))))
+  (property "Value" "" (at 0 5 0) (layer "F.Fab") hide
+    (effects (font (size 1 1) (thickness 0.15))))
+  (fp_rect (start -6.7 -5.9) (end 6.7 5.9)
+    (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
+  (fp_rect (start -7.6 -6.4) (end 7.6 6.4)
+    (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
+  (fp_line (start -6.775 -5.975) (end 6.775 -5.975) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 6.775 -5.975) (end 6.775 5.975) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 6.775 5.975) (end -6.775 5.975) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start -6.775 5.975) (end -6.775 -5.975) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_circle (center -7.15 -5.45) (end -6.9 -5.45) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
+  (pad "1" smd roundrect (at -6.165 -4.4) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "2" smd roundrect (at -6.165 -3.6) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "3" smd roundrect (at -6.165 -2.8) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "4" smd roundrect (at -6.165 -2) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "5" smd roundrect (at -6.165 -1.2) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "6" smd roundrect (at -6.165 -0.4) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "7" smd roundrect (at -6.165 0.4) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "8" smd roundrect (at -6.165 1.2) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "9" smd roundrect (at -6.165 2) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "10" smd roundrect (at -6.165 2.8) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "11" smd roundrect (at -6.165 3.6) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "12" smd roundrect (at -6.165 4.4) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "24" smd roundrect (at 6.165 -4.4) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "23" smd roundrect (at 6.165 -3.6) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "22" smd roundrect (at 6.165 -2.8) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "21" smd roundrect (at 6.165 -2) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "20" smd roundrect (at 6.165 -1.2) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "19" smd roundrect (at 6.165 -0.4) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "18" smd roundrect (at 6.165 0.4) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "17" smd roundrect (at 6.165 1.2) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "16" smd roundrect (at 6.165 2) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "15" smd roundrect (at 6.165 2.8) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "14" smd roundrect (at 6.165 3.6) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "13" smd roundrect (at 6.165 4.4) (size 1.87 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (fp_text user "X+ ->" (at 0 -2) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.14))))
+  (fp_text user "Y+ ^" (at 0 0) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.14))))
+  (embedded_fonts no)
+)
@@ -0,0 +1,23 @@
+(footprint "Texas_DPY0002A_X1SON"
+  (version 20240108)
+  (generator "board-footprints")
+  (layer "F.Cu")
+  (descr "TI DPY0002A X1SON; ESD501 official land")
+  (attr smd)
+  (property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
+    (effects (font (size 1 1) (thickness 0.15))))
+  (property "Value" "" (at 0 5 0) (layer "F.Fab") hide
+    (effects (font (size 1 1) (thickness 0.15))))
+  (fp_rect (start -0.5 -0.3) (end 0.5 0.3)
+    (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
+  (fp_rect (start -0.7 -0.5) (end 0.7 0.5)
+    (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
+  (fp_line (start -0.575 -0.375) (end 0.575 -0.375) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 0.575 -0.375) (end 0.575 0.375) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 0.575 0.375) (end -0.575 0.375) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start -0.575 0.375) (end -0.575 -0.375) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_circle (center -0.7 -0.3) (end -0.45 -0.3) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
+  (pad "1" smd roundrect (at -0.35 0) (size 0.3 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "2" smd roundrect (at 0.35 0) (size 0.3 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (embedded_fonts no)
+)
@@ -0,0 +1,35 @@
+(footprint "Texas_RPW0010A_QFN10"
+  (version 20240108)
+  (generator "board-footprints")
+  (layer "F.Cu")
+  (descr "TI RPW0010A VQFN-HR; TI land pattern 4225183/A")
+  (attr smd)
+  (property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
+    (effects (font (size 1 1) (thickness 0.15))))
+  (property "Value" "" (at 0 5 0) (layer "F.Fab") hide
+    (effects (font (size 1 1) (thickness 0.15))))
+  (fp_rect (start -1 -1) (end 1 1)
+    (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
+  (fp_rect (start -1.5 -1.5) (end 1.5 1.5)
+    (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
+  (fp_line (start -1.175 -1.175) (end 1.175 -1.175) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 1.175 -1.175) (end 1.175 1.175) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 1.175 1.175) (end -1.175 1.175) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start -1.175 1.175) (end -1.175 -1.175) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_circle (center -1.45 -1.15) (end -1.2 -1.15) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
+  (pad "1" smd roundrect (at -0.725 -0.9) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "1" smd roundrect (at -0.9 -0.75) (size 0.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "4" smd roundrect (at -0.725 0.9) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "4" smd roundrect (at -0.9 0.75) (size 0.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "7" smd roundrect (at 0.725 0.9) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "7" smd roundrect (at 0.9 0.75) (size 0.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "10" smd roundrect (at 0.725 -0.9) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "10" smd roundrect (at 0.9 -0.75) (size 0.6 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "2" smd roundrect (at -0.9 -0.225) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "3" smd roundrect (at -0.9 0.225) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "5" smd roundrect (at -0.25 0) (size 0.3 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "6" smd roundrect (at 0.25 0) (size 0.3 2.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "8" smd roundrect (at 0.9 0.225) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "9" smd roundrect (at 0.9 -0.225) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (embedded_fonts no)
+)
@@ -0,0 +1,30 @@
+(footprint "Texas_RQY0009A_VQFN9"
+  (version 20240108)
+  (generator "board-footprints")
+  (layer "F.Cu")
+  (descr "TI RQY0009A VQFN-HR; TI land pattern 4225639/A")
+  (attr smd)
+  (property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
+    (effects (font (size 1 1) (thickness 0.15))))
+  (property "Value" "" (at 0 5 0) (layer "F.Fab") hide
+    (effects (font (size 1 1) (thickness 0.15))))
+  (fp_rect (start -0.75 -1) (end 0.75 1)
+    (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
+  (fp_rect (start -1.4 -1.6) (end 1.4 1.6)
+    (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
+  (fp_line (start -0.875 -1.225) (end 0.875 -1.225) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 0.875 -1.225) (end 0.875 1.225) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 0.875 1.225) (end -0.875 1.225) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start -0.875 1.225) (end -0.875 -1.225) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_circle (center -1.05 -1.25) (end -0.8 -1.25) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
+  (pad "1" smd roundrect (at -0.5 -1.175) (size 0.25 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "9" smd roundrect (at 0 -1.175) (size 0.25 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "8" smd roundrect (at 0.5 -1.175) (size 0.25 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "4" smd roundrect (at -0.5 1.175) (size 0.25 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "5" smd roundrect (at 0 1.175) (size 0.25 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "6" smd roundrect (at 0.5 1.175) (size 0.25 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "2" smd roundrect (at -0.475 -0.4) (size 0.95 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "3" smd roundrect (at -0.475 0.4) (size 0.95 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "7" smd roundrect (at 0.475 0) (size 0.95 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (embedded_fonts no)
+)
@@ -0,0 +1,33 @@
+(footprint "Texas_RUX0012A_VQFN12"
+  (version 20240108)
+  (generator "board-footprints")
+  (layer "F.Cu")
+  (descr "TI RUX0012A VQFN-HR; TI land pattern 4224010/A")
+  (attr smd)
+  (property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
+    (effects (font (size 1 1) (thickness 0.15))))
+  (property "Value" "" (at 0 5 0) (layer "F.Fab") hide
+    (effects (font (size 1 1) (thickness 0.15))))
+  (fp_rect (start -1.25 -1.25) (end 1.25 1.25)
+    (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
+  (fp_rect (start -1.7 -1.7) (end 1.7 1.7)
+    (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
+  (fp_line (start -1.325 -1.325) (end 1.325 -1.325) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 1.325 -1.325) (end 1.325 1.325) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 1.325 1.325) (end -1.325 1.325) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start -1.325 1.325) (end -1.325 -1.325) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_circle (center -1.45 -1.2) (end -1.2 -1.2) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
+  (pad "1" smd roundrect (at -0.675 -0.35) (size 1.05 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "2" smd roundrect (at -0.675 0.35) (size 1.05 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "8" smd roundrect (at 0.675 -0.35) (size 1.05 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "7" smd roundrect (at 0.675 0.35) (size 1.05 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "12" smd roundrect (at -0.75 -1.15) (size 0.2 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "11" smd roundrect (at -0.25 -1.15) (size 0.2 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "10" smd roundrect (at 0.25 -1.15) (size 0.2 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "9" smd roundrect (at 0.75 -1.15) (size 0.2 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "3" smd roundrect (at -0.75 1.15) (size 0.2 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "4" smd roundrect (at -0.25 1.15) (size 0.2 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "5" smd roundrect (at 0.25 1.15) (size 0.2 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "6" smd roundrect (at 0.75 1.15) (size 0.2 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (embedded_fonts no)
+)
@@ -0,0 +1,56 @@
+(footprint "Texas_RZV0024A_WQFN24"
+  (version 20240108)
+  (generator "board-footprints")
+  (layer "F.Cu")
+  (descr "TI RZV0024A WQFN-FCRLF; TI land pattern 4228538/A")
+  (attr smd)
+  (property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")
+    (effects (font (size 1 1) (thickness 0.15))))
+  (property "Value" "" (at 0 5 0) (layer "F.Fab") hide
+    (effects (font (size 1 1) (thickness 0.15))))
+  (fp_rect (start -1.525 -2.025) (end 1.525 2.025)
+    (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))
+  (fp_rect (start -1.75 -2.25) (end 1.75 2.25)
+    (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))
+  (fp_line (start -1.575 -2.075) (end 1.575 -2.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 1.575 -2.075) (end 1.575 2.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start 1.575 2.075) (end -1.575 2.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_line (start -1.575 2.075) (end -1.575 -2.075) (stroke (width 0.15) (type default)) (layer "F.SilkS"))
+  (fp_circle (center -1.75 -2.1) (end -1.5 -2.1) (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))
+  (pad "1" smd roundrect (at -1.25 -1.825) (size 0.25 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "1" smd roundrect (at -1.325 -1.75) (size 0.45 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "8" smd roundrect (at -1.25 1.825) (size 0.25 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "8" smd roundrect (at -1.325 1.75) (size 0.45 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "13" smd roundrect (at 1.25 1.825) (size 0.25 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "13" smd roundrect (at 1.325 1.75) (size 0.45 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "20" smd roundrect (at 1.25 -1.825) (size 0.25 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "20" smd roundrect (at 1.325 -1.75) (size 0.45 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "2" smd roundrect (at -1.25 -1.25) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "3" smd roundrect (at -1.25 -0.75) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "4" smd roundrect (at -1.25 -0.25) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
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+  (pad "19" smd roundrect (at 1.25 -1.25) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "18" smd roundrect (at 1.25 -0.75) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "17" smd roundrect (at 1.25 -0.25) (size 0.6 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
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+  (pad "24" smd roundrect (at -0.75 -1.75) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "23" smd roundrect (at -0.25 -1.75) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "22" smd roundrect (at 0.25 -1.75) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "21" smd roundrect (at 0.75 -1.75) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "9" smd roundrect (at -0.75 1.75) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "10" smd roundrect (at -0.25 1.75) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "11" smd roundrect (at 0.25 1.75) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "12" smd roundrect (at 0.75 1.75) (size 0.25 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15))
+  (pad "25" smd rect (at -0.425 -0.65) (size 0.6 1.1) (layers "F.Cu" "F.Mask"))
+  (pad "" smd roundrect (at -0.425 -0.65) (size 0.48 0.92) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "25" smd rect (at 0.425 -0.65) (size 0.6 1.1) (layers "F.Cu" "F.Mask"))
+  (pad "" smd roundrect (at 0.425 -0.65) (size 0.48 0.92) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "25" smd rect (at 0 0.65) (size 1.45 1.1) (layers "F.Cu" "F.Mask"))
+  (pad "" smd roundrect (at -0.3625 0.65) (size 0.605 0.92) (layers "F.Paste") (roundrect_rratio 0.15))
+  (pad "" smd roundrect (at 0.3625 0.65) (size 0.605 0.92) (layers "F.Paste") (roundrect_rratio 0.15))
+  (embedded_fonts no)
+)
@@ -0,0 +1,53 @@
+EESchema Schematic File Version 4
+LIBS:board-cache
+EELAYER 29 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 7
+Title "Ti375 C529 GNSS/IMU acquisition board"
+Date "2026-08-15"
+Rev "A0"
+Comp "JLCPCB manufacture/assembly package"
+Comment1 "USB-C 5 V primary; protected external 5 V; no back-feed"
+Comment2 "GPS L1/L1C direct MAX2771 MIXIN_HI; selectable active-antenna bias"
+Comment3 "Every Ti375 programmable GPIO has a documented disposition"
+Comment4 "Generated source - see docs/design_audit.md"
+$EndDescr
+$Sheet
+S 1400 1000 3600 1200
+U 66000001
+F0 "POWER USB" 60
+F1 "power_usb.sch" 60
+$EndSheet
+$Sheet
+S 6200 1000 3600 1200
+U 66000002
+F0 "RF CLOCK" 60
+F1 "rf_clock.sch" 60
+$EndSheet
+$Sheet
+S 1400 2900 3600 1200
+U 66000003
+F0 "IMU" 60
+F1 "imu.sch" 60
+$EndSheet
+$Sheet
+S 6200 2900 3600 1200
+U 66000004
+F0 "USB DEBUG" 60
+F1 "usb_debug.sch" 60
+$EndSheet
+$Sheet
+S 1400 4800 3600 1200
+U 66000005
+F0 "CONFIGURATION EXPANSION" 60
+F1 "configuration_expansion.sch" 60
+$EndSheet
+$Sheet
+S 6200 4800 3600 1200
+U 66000006
+F0 "FPGA" 60
+F1 "fpga.sch" 60
+$EndSheet
+$EndSCHEMATC
@@ -0,0 +1,373 @@
+EESchema Schematic File Version 4
+LIBS:board-cache
+EELAYER 29 0
+EELAYER END
+$Descr A0 46811 33110
+encoding utf-8
+Sheet 1 1
+Title "Ti375 GNSS/IMU board - Configuration Expansion"
+Date "2026-08-15"
+Rev "A0"
+Comp "Open hardware design for JLCPCB"
+Comment1 "Generated from scripts/design_data.py; do not hand-edit"
+Comment2 "No LEDs, no push buttons"
+Comment3 "Ti375C529C3 / MAX2771 / SCH16T-K01-1"
+Comment4 "JLC08161H-3313 eight-layer stack"
+$EndDescr
+$Comp
+L BOARD_U26 U26
+U 1 1 65050001
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+F 1 "512-Mbit QSPI flash" H 1800 1900 50  0000 C CNN
+F 2 "Package_SON:WSON-8-1EP_6x5mm_P1.27mm_EP3.4x4.3mm" H 1800 1600 50  0001 C CNN
+F 3 "" H 1800 1800 50  0001 C CNN
+F 4 "IS25WP512M-JLLE" H 1800 1800 50  0001 C CNN "MPN"
+F 5 "ISSI" H 1800 1800 50  0001 C CNN "Manufacturer"
+	1    1800 1800
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 2000 950 2000
+Text GLabel 950 2000 2    30   BiDi ~ 0
+QSPI_CS_N
+Wire Wire Line
+	2500 1950 2650 1950
+Text GLabel 2650 1950 0    30   BiDi ~ 0
+QSPI_IO1
+Wire Wire Line
+	1100 1900 950 1900
+Text GLabel 950 1900 2    30   BiDi ~ 0
+QSPI_IO2
+Wire Wire Line
+	2500 1850 2650 1850
+Text GLabel 2650 1850 0    30   BiDi ~ 0
+GND
+Wire Wire Line
+	1100 1800 950 1800
+Text GLabel 950 1800 2    30   BiDi ~ 0
+QSPI_IO0
+Wire Wire Line
+	2500 1750 2650 1750
+Text GLabel 2650 1750 0    30   BiDi ~ 0
+QSPI_SCLK
+Wire Wire Line
+	1100 1700 950 1700
+Text GLabel 950 1700 2    30   BiDi ~ 0
+QSPI_IO3
+Wire Wire Line
+	2500 1650 2650 1650
+Text GLabel 2650 1650 0    30   BiDi ~ 0
+VCC1V8
+Wire Wire Line
+	1100 1600 950 1600
+Text GLabel 950 1600 2    30   BiDi ~ 0
+GND
+$Comp
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+F 3 "" H 1800 2900 50  0001 C CNN
+F 4 "RC0402FR-0710KL" H 1800 2900 50  0001 C CNN "MPN"
+F 5 "Yageo" H 1800 2900 50  0001 C CNN "Manufacturer"
+	1    1800 2900
+	1    0    0    -1
+$EndComp
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+	2500 2900 2650 2900
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+QSPI_CS_N
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+F 5 "Yageo" H 1800 3700 50  0001 C CNN "Manufacturer"
+	1    1800 3700
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+$EndComp
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+Wire Wire Line
+	2500 3700 2650 3700
+Text GLabel 2650 3700 0    30   BiDi ~ 0
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+$Comp
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+F 3 "" H 1800 4500 50  0001 C CNN
+F 4 "RC0402FR-0710KL" H 1800 4500 50  0001 C CNN "MPN"
+F 5 "Yageo" H 1800 4500 50  0001 C CNN "Manufacturer"
+	1    1800 4500
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 4500 950 4500
+Text GLabel 950 4500 2    30   BiDi ~ 0
+VCC1V8
+Wire Wire Line
+	2500 4500 2650 4500
+Text GLabel 2650 4500 0    30   BiDi ~ 0
+QSPI_IO3
+$Comp
+L BOARD_JPMOD1 JPMOD1
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+F 3 "" H 1800 5300 50  0001 C CNN
+F 4 "67997-412HLF" H 1800 5300 50  0001 C CNN "MPN"
+F 5 "Amphenol ICC" H 1800 5300 50  0001 C CNN "Manufacturer"
+	1    1800 5300
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+$EndComp
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+	1100 5550 950 5550
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+Wire Wire Line
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+PMOD1_2
+Wire Wire Line
+	1100 5450 950 5450
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+Wire Wire Line
+	2500 5450 2650 5450
+Text GLabel 2650 5450 0    30   BiDi ~ 0
+PMOD1_4
+Wire Wire Line
+	1100 5350 950 5350
+Text GLabel 950 5350 2    30   BiDi ~ 0
+GND
+Wire Wire Line
+	2500 5350 2650 5350
+Text GLabel 2650 5350 0    30   BiDi ~ 0
+VCC3V3
+Wire Wire Line
+	1100 5250 950 5250
+Text GLabel 950 5250 2    30   BiDi ~ 0
+PMOD1_7
+Wire Wire Line
+	2500 5250 2650 5250
+Text GLabel 2650 5250 0    30   BiDi ~ 0
+PMOD1_8
+Wire Wire Line
+	1100 5150 950 5150
+Text GLabel 950 5150 2    30   BiDi ~ 0
+PMOD1_9
+Wire Wire Line
+	2500 5150 2650 5150
+Text GLabel 2650 5150 0    30   BiDi ~ 0
+PMOD1_10
+Wire Wire Line
+	1100 5050 950 5050
+Text GLabel 950 5050 2    30   BiDi ~ 0
+GND
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+	2500 5050 2650 5050
+Text GLabel 2650 5050 0    30   BiDi ~ 0
+VCC3V3
+$Comp
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+F 3 "" H 1800 6500 50  0001 C CNN
+F 4 "67997-412HLF" H 1800 6500 50  0001 C CNN "MPN"
+F 5 "Amphenol ICC" H 1800 6500 50  0001 C CNN "Manufacturer"
+	1    1800 6500
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 6750 950 6750
+Text GLabel 950 6750 2    30   BiDi ~ 0
+PMOD2_1
+Wire Wire Line
+	2500 6750 2650 6750
+Text GLabel 2650 6750 0    30   BiDi ~ 0
+PMOD2_2
+Wire Wire Line
+	1100 6650 950 6650
+Text GLabel 950 6650 2    30   BiDi ~ 0
+PMOD2_3
+Wire Wire Line
+	2500 6650 2650 6650
+Text GLabel 2650 6650 0    30   BiDi ~ 0
+PMOD2_4
+Wire Wire Line
+	1100 6550 950 6550
+Text GLabel 950 6550 2    30   BiDi ~ 0
+GND
+Wire Wire Line
+	2500 6550 2650 6550
+Text GLabel 2650 6550 0    30   BiDi ~ 0
+VCC3V3
+Wire Wire Line
+	1100 6450 950 6450
+Text GLabel 950 6450 2    30   BiDi ~ 0
+PMOD2_7
+Wire Wire Line
+	2500 6450 2650 6450
+Text GLabel 2650 6450 0    30   BiDi ~ 0
+PMOD2_8
+Wire Wire Line
+	1100 6350 950 6350
+Text GLabel 950 6350 2    30   BiDi ~ 0
+PMOD2_9
+Wire Wire Line
+	2500 6350 2650 6350
+Text GLabel 2650 6350 0    30   BiDi ~ 0
+PMOD2_10
+Wire Wire Line
+	1100 6250 950 6250
+Text GLabel 950 6250 2    30   BiDi ~ 0
+GND
+Wire Wire Line
+	2500 6250 2650 6250
+Text GLabel 2650 6250 0    30   BiDi ~ 0
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+$Comp
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+F 2 "board:Digilent_PMOD_2x6_P2.54mm" H 1800 7500 50  0001 C CNN
+F 3 "" H 1800 7700 50  0001 C CNN
+F 4 "67997-412HLF" H 1800 7700 50  0001 C CNN "MPN"
+F 5 "Amphenol ICC" H 1800 7700 50  0001 C CNN "Manufacturer"
+	1    1800 7700
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 7950 950 7950
+Text GLabel 950 7950 2    30   BiDi ~ 0
+PMOD3_1
+Wire Wire Line
+	2500 7950 2650 7950
+Text GLabel 2650 7950 0    30   BiDi ~ 0
+PMOD3_2
+Wire Wire Line
+	1100 7850 950 7850
+Text GLabel 950 7850 2    30   BiDi ~ 0
+PMOD3_3
+Wire Wire Line
+	2500 7850 2650 7850
+Text GLabel 2650 7850 0    30   BiDi ~ 0
+PMOD3_4
+Wire Wire Line
+	1100 7750 950 7750
+Text GLabel 950 7750 2    30   BiDi ~ 0
+GND
+Wire Wire Line
+	2500 7750 2650 7750
+Text GLabel 2650 7750 0    30   BiDi ~ 0
+VCC1V8
+Wire Wire Line
+	1100 7650 950 7650
+Text GLabel 950 7650 2    30   BiDi ~ 0
+PMOD3_7
+Wire Wire Line
+	2500 7650 2650 7650
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+PMOD3_8
+Wire Wire Line
+	1100 7550 950 7550
+Text GLabel 950 7550 2    30   BiDi ~ 0
+PMOD3_9
+Wire Wire Line
+	2500 7550 2650 7550
+Text GLabel 2650 7550 0    30   BiDi ~ 0
+PMOD3_10
+Wire Wire Line
+	1100 7450 950 7450
+Text GLabel 950 7450 2    30   BiDi ~ 0
+GND
+Wire Wire Line
+	2500 7450 2650 7450
+Text GLabel 2650 7450 0    30   BiDi ~ 0
+VCC1V8
+$Comp
+L BOARD_JPMOD4 JPMOD4
+U 1 1 65050008
+P 1800 8900
+F 0 "JPMOD4" H 1800 8800 50  0000 C CNN
+F 1 "PMOD 1.8 V" H 1800 9000 50  0000 C CNN
+F 2 "board:Digilent_PMOD_2x6_P2.54mm" H 1800 8700 50  0001 C CNN
+F 3 "" H 1800 8900 50  0001 C CNN
+F 4 "67997-412HLF" H 1800 8900 50  0001 C CNN "MPN"
+F 5 "Amphenol ICC" H 1800 8900 50  0001 C CNN "Manufacturer"
+	1    1800 8900
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 9150 950 9150
+Text GLabel 950 9150 2    30   BiDi ~ 0
+PMOD4_1
+Wire Wire Line
+	2500 9150 2650 9150
+Text GLabel 2650 9150 0    30   BiDi ~ 0
+PMOD4_2
+Wire Wire Line
+	1100 9050 950 9050
+Text GLabel 950 9050 2    30   BiDi ~ 0
+PMOD4_3
+Wire Wire Line
+	2500 9050 2650 9050
+Text GLabel 2650 9050 0    30   BiDi ~ 0
+PMOD4_4
+Wire Wire Line
+	1100 8950 950 8950
+Text GLabel 950 8950 2    30   BiDi ~ 0
+GND
+Wire Wire Line
+	2500 8950 2650 8950
+Text GLabel 2650 8950 0    30   BiDi ~ 0
+VCC1V8
+Wire Wire Line
+	1100 8850 950 8850
+Text GLabel 950 8850 2    30   BiDi ~ 0
+PMOD4_7
+Wire Wire Line
+	2500 8850 2650 8850
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+PMOD4_8
+Wire Wire Line
+	1100 8750 950 8750
+Text GLabel 950 8750 2    30   BiDi ~ 0
+PMOD4_9
+Wire Wire Line
+	2500 8750 2650 8750
+Text GLabel 2650 8750 0    30   BiDi ~ 0
+PMOD4_10
+Wire Wire Line
+	1100 8650 950 8650
+Text GLabel 950 8650 2    30   BiDi ~ 0
+GND
+Wire Wire Line
+	2500 8650 2650 8650
+Text GLabel 2650 8650 0    30   BiDi ~ 0
+VCC1V8
+$EndSCHEMATC
@@ -0,0 +1,4 @@
+(fp_lib_table
+  (version 7)
+  (lib (name "board")(type "KiCad")(uri "${KIPRJMOD}/board.pretty")(options "")(descr "Official-land-pattern custom footprints"))
+)
@@ -0,0 +1,333 @@
+EESchema Schematic File Version 4
+LIBS:board-cache
+EELAYER 29 0
+EELAYER END
+$Descr A0 46811 33110
+encoding utf-8
+Sheet 1 1
+Title "Ti375 GNSS/IMU board - Imu"
+Date "2026-08-15"
+Rev "A0"
+Comp "Open hardware design for JLCPCB"
+Comment1 "Generated from scripts/design_data.py; do not hand-edit"
+Comment2 "No LEDs, no push buttons"
+Comment3 "Ti375C529C3 / MAX2771 / SCH16T-K01-1"
+Comment4 "JLC08161H-3313 eight-layer stack"
+$EndDescr
+$Comp
+L BOARD_U22 U22
+U 1 1 65030001
+P 1800 1800
+F 0 "U22" H 1800 1700 50  0000 C CNN
+F 1 "SCH16T-K01-1" H 1800 1900 50  0000 C CNN
+F 2 "board:Murata_SCH16T_K01" H 1800 1600 50  0001 C CNN
+F 3 "" H 1800 1800 50  0001 C CNN
+F 4 "SCH16T-K01-1" H 1800 1800 50  0001 C CNN "MPN"
+F 5 "Murata" H 1800 1800 50  0001 C CNN "Manufacturer"
+	1    1800 1800
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 2350 950 2350
+Text GLabel 950 2350 2    30   BiDi ~ 0
+GND
+NoConn ~ 2500 2350
+Wire Wire Line
+	1100 2250 950 2250
+Text GLabel 950 2250 2    30   BiDi ~ 0
+GND
+Wire Wire Line
+	2500 2250 2650 2250
+Text GLabel 2650 2250 0    30   BiDi ~ 0
+GND
+Wire Wire Line
+	1100 2150 950 2150
+Text GLabel 950 2150 2    30   BiDi ~ 0
+GND
+Wire Wire Line
+	2500 2150 2650 2150
+Text GLabel 2650 2150 0    30   BiDi ~ 0
+IMU_EXTRESN
+Wire Wire Line
+	1100 2050 950 2050
+Text GLabel 950 2050 2    30   BiDi ~ 0
+GND
+Wire Wire Line
+	2500 2050 2650 2050
+Text GLabel 2650 2050 0    30   BiDi ~ 0
+IMU_3V3
+Wire Wire Line
+	1100 1950 950 1950
+Text GLabel 950 1950 2    30   BiDi ~ 0
+GND
+Wire Wire Line
+	2500 1950 2650 1950
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+IMU_VREGA2
+Wire Wire Line
+	1100 1850 950 1850
+Text GLabel 950 1850 2    30   BiDi ~ 0
+IMU_VREGA2
+Wire Wire Line
+	2500 1850 2650 1850
+Text GLabel 2650 1850 0    30   BiDi ~ 0
+GND
+Wire Wire Line
+	1100 1750 950 1750
+Text GLabel 950 1750 2    30   BiDi ~ 0
+GND
+Wire Wire Line
+	2500 1750 2650 1750
+Text GLabel 2650 1750 0    30   BiDi ~ 0
+IMU_VREGD
+Wire Wire Line
+	1100 1650 950 1650
+Text GLabel 950 1650 2    30   BiDi ~ 0
+IMU_VREGD
+Wire Wire Line
+	2500 1650 2650 1650
+Text GLabel 2650 1650 0    30   BiDi ~ 0
+GND
+Wire Wire Line
+	1100 1550 950 1550
+Text GLabel 950 1550 2    30   BiDi ~ 0
+IMU_3V3
+Wire Wire Line
+	2500 1550 2650 1550
+Text GLabel 2650 1550 0    30   BiDi ~ 0
+VCC3V3
+Wire Wire Line
+	1100 1450 950 1450
+Text GLabel 950 1450 2    30   BiDi ~ 0
+IMU_MISO_DEV
+Wire Wire Line
+	2500 1450 2650 1450
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+IMU_DRY_SYNC
+Wire Wire Line
+	1100 1350 950 1350
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+IMU_SCK_DEV
+Wire Wire Line
+	2500 1350 2650 1350
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+IMU_CS_DEV
+Wire Wire Line
+	1100 1250 950 1250
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+IMU_MOSI_DEV
+Wire Wire Line
+	2500 1250 2650 1250
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+F 3 "" H 1800 3600 50  0001 C CNN
+F 4 "BLM15AG601SN1D" H 1800 3600 50  0001 C CNN "MPN"
+F 5 "Murata" H 1800 3600 50  0001 C CNN "Manufacturer"
+	1    1800 3600
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 3600 950 3600
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+Wire Wire Line
+	2500 3600 2650 3600
+Text GLabel 2650 3600 0    30   BiDi ~ 0
+IMU_3V3
+$Comp
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+$EndSCHEMATC
@@ -0,0 +1,894 @@
+EESchema Schematic File Version 4
+LIBS:board-cache
+EELAYER 29 0
+EELAYER END
+$Descr A0 46811 33110
+encoding utf-8
+Sheet 1 1
+Title "Ti375 GNSS/IMU board - Rf Clock"
+Date "2026-08-15"
+Rev "A0"
+Comp "Open hardware design for JLCPCB"
+Comment1 "Generated from scripts/design_data.py; do not hand-edit"
+Comment2 "No LEDs, no push buttons"
+Comment3 "Ti375C529C3 / MAX2771 / SCH16T-K01-1"
+Comment4 "JLC08161H-3313 eight-layer stack"
+$EndDescr
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+	1    1800 9200
+	1    0    0    -1
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+$EndComp
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+	1    1800 10800
+	1    0    0    -1
+$EndComp
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+	1100 10800 950 10800
+Text GLabel 950 10800 2    30   BiDi ~ 0
+VCC3V3_AUX
+Wire Wire Line
+	2500 10800 2650 10800
+Text GLabel 2650 10800 0    30   BiDi ~ 0
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+	1    1800 11600
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+$EndComp
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+	2500 11600 2650 11600
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+	1    1800 12400
+	1    0    0    -1
+$EndComp
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+Wire Wire Line
+	2500 12400 2650 12400
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+$Comp
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+	1    1800 13200
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+$EndComp
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+$Comp
+L BOARD_U21 U21
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+	1    1800 14800
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+$EndComp
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+MAX_CPOUT
+Wire Wire Line
+	2500 15450 2650 15450
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+VCC3V0_RF
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+Wire Wire Line
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+Text GLabel 2650 15350 0    30   BiDi ~ 0
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+MAX_ADC_CLKIN
+Wire Wire Line
+	2500 15250 2650 15250
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+VCC3V0_DIG
+Wire Wire Line
+	1100 15200 950 15200
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+MAX_SDATA_DEV
+Wire Wire Line
+	2500 15150 2650 15150
+Text GLabel 2650 15150 0    30   BiDi ~ 0
+MAX_SCLK_DEV
+Wire Wire Line
+	1100 15100 950 15100
+Text GLabel 950 15100 2    30   BiDi ~ 0
+MAX_CSN_DEV
+Wire Wire Line
+	2500 15050 2650 15050
+Text GLabel 2650 15050 0    30   BiDi ~ 0
+MAX_Q1_DEV
+Wire Wire Line
+	1100 15000 950 15000
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+MAX_Q0_DEV
+Wire Wire Line
+	2500 14950 2650 14950
+Text GLabel 2650 14950 0    30   BiDi ~ 0
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+Wire Wire Line
+	1100 14900 950 14900
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+MAX_I1_DEV
+Wire Wire Line
+	2500 14850 2650 14850
+Text GLabel 2650 14850 0    30   BiDi ~ 0
+VCC3V0_DIG
+NoConn ~ 1100 14800
+NoConn ~ 2500 14750
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+	1100 14700 950 14700
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+Wire Wire Line
+	2500 14650 2650 14650
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+MAX_SHDN_DEV
+NoConn ~ 1100 14600
+NoConn ~ 2500 14550
+NoConn ~ 1100 14500
+Wire Wire Line
+	2500 14450 2650 14450
+Text GLabel 2650 14450 0    30   BiDi ~ 0
+VCC3V0_RF
+NoConn ~ 1100 14400
+NoConn ~ 2500 14350
+Wire Wire Line
+	1100 14300 950 14300
+Text GLabel 950 14300 2    30   BiDi ~ 0
+MAX_MIXIN_HI
+NoConn ~ 2500 14250
+Wire Wire Line
+	1100 14200 950 14200
+Text GLabel 950 14200 2    30   BiDi ~ 0
+VCC3V0_RF
+Wire Wire Line
+	2500 14150 2650 14150
+Text GLabel 2650 14150 0    30   BiDi ~ 0
+VCC3V0_RF
+Wire Wire Line
+	1100 14100 950 14100
+Text GLabel 950 14100 2    30   BiDi ~ 0
+GND
+$Comp
+L BOARD_C88 C88
+U 1 1 65020012
+P 1800 16900
+F 0 "C88" H 1800 16800 50  0000 C CNN
+F 1 "15pF" H 1800 17000 50  0000 C CNN
+F 2 "Capacitor_SMD:C_0402_1005Metric" H 1800 16700 50  0001 C CNN
+F 3 "" H 1800 16900 50  0001 C CNN
+F 4 "GRM1555C1H150JA01D" H 1800 16900 50  0001 C CNN "MPN"
+F 5 "Murata" H 1800 16900 50  0001 C CNN "Manufacturer"
+	1    1800 16900
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 16900 950 16900
+Text GLabel 950 16900 2    30   BiDi ~ 0
+MAX_CPOUT
+Wire Wire Line
+	2500 16900 2650 16900
+Text GLabel 2650 16900 0    30   BiDi ~ 0
+GND
+$Comp
+L BOARD_R43 R43
+U 1 1 65020013
+P 1800 17700
+F 0 "R43" H 1800 17600 50  0000 C CNN
+F 1 "15K" H 1800 17800 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 17500 50  0001 C CNN
+F 3 "" H 1800 17700 50  0001 C CNN
+F 4 "RC0402FR-0715KL" H 1800 17700 50  0001 C CNN "MPN"
+F 5 "Yageo" H 1800 17700 50  0001 C CNN "Manufacturer"
+	1    1800 17700
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 17700 950 17700
+Text GLabel 950 17700 2    30   BiDi ~ 0
+MAX_CPOUT
+Wire Wire Line
+	2500 17700 2650 17700
+Text GLabel 2650 17700 0    30   BiDi ~ 0
+MAX_LOOP_RC
+$Comp
+L BOARD_C89 C89
+U 1 1 65020014
+P 1800 18500
+F 0 "C89" H 1800 18400 50  0000 C CNN
+F 1 "750pF" H 1800 18600 50  0000 C CNN
+F 2 "Capacitor_SMD:C_0402_1005Metric" H 1800 18300 50  0001 C CNN
+F 3 "" H 1800 18500 50  0001 C CNN
+F 4 "GRM1555C1H751JA01D" H 1800 18500 50  0001 C CNN "MPN"
+F 5 "Murata" H 1800 18500 50  0001 C CNN "Manufacturer"
+	1    1800 18500
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 18500 950 18500
+Text GLabel 950 18500 2    30   BiDi ~ 0
+MAX_LOOP_RC
+Wire Wire Line
+	2500 18500 2650 18500
+Text GLabel 2650 18500 0    30   BiDi ~ 0
+GND
+$Comp
+L BOARD_C90 C90
+U 1 1 65020015
+P 1800 19300
+F 0 "C90" H 1800 19200 50  0000 C CNN
+F 1 "10nF" H 1800 19400 50  0000 C CNN
+F 2 "Capacitor_SMD:C_0402_1005Metric" H 1800 19100 50  0001 C CNN
+F 3 "" H 1800 19300 50  0001 C CNN
+F 4 "GRM155R71H103KA88D" H 1800 19300 50  0001 C CNN "MPN"
+F 5 "Murata" H 1800 19300 50  0001 C CNN "Manufacturer"
+	1    1800 19300
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 19300 950 19300
+Text GLabel 950 19300 2    30   BiDi ~ 0
+TCXO16_OUT
+Wire Wire Line
+	2500 19300 2650 19300
+Text GLabel 2650 19300 0    30   BiDi ~ 0
+MAX_XTAL
+$Comp
+L BOARD_R44 R44
+U 1 1 65020016
+P 1800 20100
+F 0 "R44" H 1800 20000 50  0000 C CNN
+F 1 "33R" H 1800 20200 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 19900 50  0001 C CNN
+F 3 "" H 1800 20100 50  0001 C CNN
+F 4 "RC0402FR-0733RL" H 1800 20100 50  0001 C CNN "MPN"
+F 5 "Yageo" H 1800 20100 50  0001 C CNN "Manufacturer"
+	1    1800 20100
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 20100 950 20100
+Text GLabel 950 20100 2    30   BiDi ~ 0
+OSC40_OUT
+Wire Wire Line
+	2500 20100 2650 20100
+Text GLabel 2650 20100 0    30   BiDi ~ 0
+MAX_ADC_CLKIN
+$Comp
+L BOARD_R45 R45
+U 1 1 65020017
+P 1800 20900
+F 0 "R45" H 1800 20800 50  0000 C CNN
+F 1 "22R" H 1800 21000 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 20700 50  0001 C CNN
+F 3 "" H 1800 20900 50  0001 C CNN
+F 4 "RC0402FR-0722RL" H 1800 20900 50  0001 C CNN "MPN"
+F 5 "Yageo" H 1800 20900 50  0001 C CNN "Manufacturer"
+	1    1800 20900
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 20900 950 20900
+Text GLabel 950 20900 2    30   BiDi ~ 0
+MAX_CLKOUT_SRC
+Wire Wire Line
+	2500 20900 2650 20900
+Text GLabel 2650 20900 0    30   BiDi ~ 0
+MAX_CLKOUT
+$Comp
+L BOARD_R46 R46
+U 1 1 65020018
+P 1800 21700
+F 0 "R46" H 1800 21600 50  0000 C CNN
+F 1 "22R" H 1800 21800 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 21500 50  0001 C CNN
+F 3 "" H 1800 21700 50  0001 C CNN
+F 4 "RC0402FR-0722RL" H 1800 21700 50  0001 C CNN "MPN"
+F 5 "Yageo" H 1800 21700 50  0001 C CNN "Manufacturer"
+	1    1800 21700
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 21700 950 21700
+Text GLabel 950 21700 2    30   BiDi ~ 0
+MAX_I0_DEV
+Wire Wire Line
+	2500 21700 2650 21700
+Text GLabel 2650 21700 0    30   BiDi ~ 0
+MAX_I0
+$Comp
+L BOARD_R47 R47
+U 1 1 65020019
+P 1800 22500
+F 0 "R47" H 1800 22400 50  0000 C CNN
+F 1 "22R" H 1800 22600 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 22300 50  0001 C CNN
+F 3 "" H 1800 22500 50  0001 C CNN
+F 4 "RC0402FR-0722RL" H 1800 22500 50  0001 C CNN "MPN"
+F 5 "Yageo" H 1800 22500 50  0001 C CNN "Manufacturer"
+	1    1800 22500
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 22500 950 22500
+Text GLabel 950 22500 2    30   BiDi ~ 0
+MAX_I1_DEV
+Wire Wire Line
+	2500 22500 2650 22500
+Text GLabel 2650 22500 0    30   BiDi ~ 0
+MAX_I1
+$Comp
+L BOARD_R48 R48
+U 1 1 6502001A
+P 1800 23300
+F 0 "R48" H 1800 23200 50  0000 C CNN
+F 1 "22R" H 1800 23400 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 23100 50  0001 C CNN
+F 3 "" H 1800 23300 50  0001 C CNN
+F 4 "RC0402FR-0722RL" H 1800 23300 50  0001 C CNN "MPN"
+F 5 "Yageo" H 1800 23300 50  0001 C CNN "Manufacturer"
+	1    1800 23300
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 23300 950 23300
+Text GLabel 950 23300 2    30   BiDi ~ 0
+MAX_Q0_DEV
+Wire Wire Line
+	2500 23300 2650 23300
+Text GLabel 2650 23300 0    30   BiDi ~ 0
+MAX_Q0
+$Comp
+L BOARD_R49 R49
+U 1 1 6502001B
+P 1800 24100
+F 0 "R49" H 1800 24000 50  0000 C CNN
+F 1 "22R" H 1800 24200 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 23900 50  0001 C CNN
+F 3 "" H 1800 24100 50  0001 C CNN
+F 4 "RC0402FR-0722RL" H 1800 24100 50  0001 C CNN "MPN"
+F 5 "Yageo" H 1800 24100 50  0001 C CNN "Manufacturer"
+	1    1800 24100
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 24100 950 24100
+Text GLabel 950 24100 2    30   BiDi ~ 0
+MAX_Q1_DEV
+Wire Wire Line
+	2500 24100 2650 24100
+Text GLabel 2650 24100 0    30   BiDi ~ 0
+MAX_Q1
+$Comp
+L BOARD_R50 R50
+U 1 1 6502001C
+P 1800 24900
+F 0 "R50" H 1800 24800 50  0000 C CNN
+F 1 "22R" H 1800 25000 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 24700 50  0001 C CNN
+F 3 "" H 1800 24900 50  0001 C CNN
+F 4 "RC0402FR-0722RL" H 1800 24900 50  0001 C CNN "MPN"
+F 5 "Yageo" H 1800 24900 50  0001 C CNN "Manufacturer"
+	1    1800 24900
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 24900 950 24900
+Text GLabel 950 24900 2    30   BiDi ~ 0
+MAX_LD_DEV
+Wire Wire Line
+	2500 24900 2650 24900
+Text GLabel 2650 24900 0    30   BiDi ~ 0
+MAX_LD
+$Comp
+L BOARD_R51 R51
+U 1 1 6502001D
+P 1800 25700
+F 0 "R51" H 1800 25600 50  0000 C CNN
+F 1 "22R" H 1800 25800 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 25500 50  0001 C CNN
+F 3 "" H 1800 25700 50  0001 C CNN
+F 4 "RC0402FR-0722RL" H 1800 25700 50  0001 C CNN "MPN"
+F 5 "Yageo" H 1800 25700 50  0001 C CNN "Manufacturer"
+	1    1800 25700
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 25700 950 25700
+Text GLabel 950 25700 2    30   BiDi ~ 0
+MAX_SCLK
+Wire Wire Line
+	2500 25700 2650 25700
+Text GLabel 2650 25700 0    30   BiDi ~ 0
+MAX_SCLK_DEV
+$Comp
+L BOARD_R52 R52
+U 1 1 6502001E
+P 1800 26500
+F 0 "R52" H 1800 26400 50  0000 C CNN
+F 1 "22R" H 1800 26600 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 26300 50  0001 C CNN
+F 3 "" H 1800 26500 50  0001 C CNN
+F 4 "RC0402FR-0722RL" H 1800 26500 50  0001 C CNN "MPN"
+F 5 "Yageo" H 1800 26500 50  0001 C CNN "Manufacturer"
+	1    1800 26500
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 26500 950 26500
+Text GLabel 950 26500 2    30   BiDi ~ 0
+MAX_CSN
+Wire Wire Line
+	2500 26500 2650 26500
+Text GLabel 2650 26500 0    30   BiDi ~ 0
+MAX_CSN_DEV
+$Comp
+L BOARD_R53 R53
+U 1 1 6502001F
+P 1800 27300
+F 0 "R53" H 1800 27200 50  0000 C CNN
+F 1 "22R" H 1800 27400 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 27100 50  0001 C CNN
+F 3 "" H 1800 27300 50  0001 C CNN
+F 4 "RC0402FR-0722RL" H 1800 27300 50  0001 C CNN "MPN"
+F 5 "Yageo" H 1800 27300 50  0001 C CNN "Manufacturer"
+	1    1800 27300
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 27300 950 27300
+Text GLabel 950 27300 2    30   BiDi ~ 0
+MAX_SDATA
+Wire Wire Line
+	2500 27300 2650 27300
+Text GLabel 2650 27300 0    30   BiDi ~ 0
+MAX_SDATA_DEV
+$Comp
+L BOARD_R54 R54
+U 1 1 65020020
+P 1800 28100
+F 0 "R54" H 1800 28000 50  0000 C CNN
+F 1 "22R" H 1800 28200 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 27900 50  0001 C CNN
+F 3 "" H 1800 28100 50  0001 C CNN
+F 4 "RC0402FR-0722RL" H 1800 28100 50  0001 C CNN "MPN"
+F 5 "Yageo" H 1800 28100 50  0001 C CNN "Manufacturer"
+	1    1800 28100
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 28100 950 28100
+Text GLabel 950 28100 2    30   BiDi ~ 0
+MAX_SHDN
+Wire Wire Line
+	2500 28100 2650 28100
+Text GLabel 2650 28100 0    30   BiDi ~ 0
+MAX_SHDN_DEV
+$Comp
+L BOARD_R55 R55
+U 1 1 65020021
+P 1800 28900
+F 0 "R55" H 1800 28800 50  0000 C CNN
+F 1 "100K" H 1800 29000 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 28700 50  0001 C CNN
+F 3 "" H 1800 28900 50  0001 C CNN
+F 4 "RC0402FR-07100KL" H 1800 28900 50  0001 C CNN "MPN"
+F 5 "Yageo" H 1800 28900 50  0001 C CNN "Manufacturer"
+	1    1800 28900
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 28900 950 28900
+Text GLabel 950 28900 2    30   BiDi ~ 0
+MAX_SHDN_DEV
+Wire Wire Line
+	2500 28900 2650 28900
+Text GLabel 2650 28900 0    30   BiDi ~ 0
+GND
+$Comp
+L BOARD_U23 U23
+U 1 1 65020022
+P 1800 29700
+F 0 "U23" H 1800 29600 50  0000 C CNN
+F 1 "16.368 MHz TCXO" H 1800 29800 50  0000 C CNN
+F 2 "board:Epson_TG2016SMN" H 1800 29500 50  0001 C CNN
+F 3 "" H 1800 29700 50  0001 C CNN
+F 4 "X1G005441030125" H 1800 29700 50  0001 C CNN "MPN"
+F 5 "Epson" H 1800 29700 50  0001 C CNN "Manufacturer"
+	1    1800 29700
+	1    0    0    -1
+$EndComp
+NoConn ~ 1100 29750
+Wire Wire Line
+	2500 29750 2650 29750
+Text GLabel 2650 29750 0    30   BiDi ~ 0
+GND
+Wire Wire Line
+	1100 29650 950 29650
+Text GLabel 950 29650 2    30   BiDi ~ 0
+TCXO16_OUT
+Wire Wire Line
+	2500 29650 2650 29650
+Text GLabel 2650 29650 0    30   BiDi ~ 0
+VCC3V0_CLK
+$Comp
+L BOARD_U24 U24
+U 1 1 65020023
+P 1800 30500
+F 0 "U24" H 1800 30400 50  0000 C CNN
+F 1 "40.000 MHz XO" H 1800 30600 50  0000 C CNN
+F 2 "Oscillator:Oscillator_SMD_SeikoEpson_SG210-4Pin_2.5x2.0mm" H 1800 30300 50  0001 C CNN
+F 3 "" H 1800 30500 50  0001 C CNN
+F 4 "X1G004171041100" H 1800 30500 50  0001 C CNN "MPN"
+F 5 "Epson" H 1800 30500 50  0001 C CNN "Manufacturer"
+	1    1800 30500
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 30550 950 30550
+Text GLabel 950 30550 2    30   BiDi ~ 0
+VCC3V0_CLK
+Wire Wire Line
+	2500 30550 2650 30550
+Text GLabel 2650 30550 0    30   BiDi ~ 0
+GND
+Wire Wire Line
+	1100 30450 950 30450
+Text GLabel 950 30450 2    30   BiDi ~ 0
+OSC40_OUT
+Wire Wire Line
+	2500 30450 2650 30450
+Text GLabel 2650 30450 0    30   BiDi ~ 0
+VCC3V0_CLK
+$Comp
+L BOARD_R56 R56
+U 1 1 65020024
+P 1800 31300
+F 0 "R56" H 1800 31200 50  0000 C CNN
+F 1 "33R" H 1800 31400 50  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" H 1800 31100 50  0001 C CNN
+F 3 "" H 1800 31300 50  0001 C CNN
+F 4 "RC0402FR-0733RL" H 1800 31300 50  0001 C CNN "MPN"
+F 5 "Yageo" H 1800 31300 50  0001 C CNN "Manufacturer"
+	1    1800 31300
+	1    0    0    -1
+$EndComp
+Wire Wire Line
+	1100 31300 950 31300
+Text GLabel 950 31300 2    30   BiDi ~ 0
+OSC40_OUT
+Wire Wire Line
+	2500 31300 2650 31300
+Text GLabel 2650 31300 0    30   BiDi ~ 0
+CLK_40M_FPGA
+$EndSCHEMATC
@@ -0,0 +1,4 @@
+(sym_lib_table
+  (version 7)
+  (lib (name "board")(type "KiCad")(uri "${KIPRJMOD}/board.kicad_sym")(options "")(descr "Generated board symbols"))
+)
@@ -0,0 +1,18 @@
+# Çıktılar
+
+Bu klasör build/routing çalışma alanıdır. Repository'de yalnızca güncel ve
+anlamlı teslim çıktıları tutulur:
+
+- `bom.csv`: ayrıntılı mühendislik BOM'u.
+- `jlcpcb_bom.csv`: montaj servisi için sadeleştirilmiş BOM.
+- `erc_final_reset.rpt`: güncel şema ERC raporu; 0 ihlal.
+- `drc_final_placement.rpt`: unrouted placement DRC raporu.
+- `board_final_reset_top.png`: güncel üst görünüm.
+
+Eski `.dsn`, `.ses`, preview PCB ve ara DRC raporları yeni netlist için
+authoritative değildir. Routing her netlist/placement değişiminden sonra güncel
+`hardware/board.kicad_pcb` üzerinden yeniden başlatılmalıdır.
+
+Güncel placement raporundaki 12 `isolated_copper` ve 499 unconnected kayıt,
+kartın henüz route edilmemiş olduğunu gösterir. Bunlar üretime hazır olunduğu
+anlamına gelmez; final routed raporda sıfır açık bağlantı hedeflenir.
@@ -0,0 +1,210 @@
+Reference,Qty,Value,Manufacturer,MPN,Footprint,Assembly,DNP,Description
+C1,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,TUSB320 local bypass
+"C10,C11",2,47uF,Murata,GRM32ER70J476ME19L,Capacitor_SMD:C_1210_3225Metric,SMT,no,5-V system bulk
+C100,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,16.368-MHz TCXO bypass
+C101,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Clock-rail local bulk
+C102,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,40-MHz oscillator bypass
+C103,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Murata V3P3 HF bypass
+C104,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Murata V3P3 local capacitor
+C105,1,10uF,Murata,GRM188R60J106ME47D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Murata required VREGA2 capacitor
+C106,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Murata required VREGD capacitor
+C107,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Murata VDDIO bypass
+"C108,C109",2,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,FT4232H VCCIO/VREGIN bypass
+"C110,C111",2,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,FT4232H VCORE bypass
+C112,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,FT4232H regulator output capacitor
+C113,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,FTDI VPHY bypass
+C114,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,FTDI VPLL bypass
+C115,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,FTDI oscillator local bypass
+C116,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,FTDI EEPROM bypass
+C117,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Additional FT4232H channel-A VCCIO bypass
+C118,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Configuration flash bypass
+C119,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Configuration flash local bulk
+C12,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Power-qualification logic local bypass
+C120,1,4.7nF,Murata,GRM155R71H472KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,TPS3808 SENSE transient filter
+C121,1,4.7nF,Murata,GRM155R71H472KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Manual/external reset cable-noise filter
+C122,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,TPS3808 local bypass
+C123,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,SN74LVC244A local bypass
+C124,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,SN74LVC1G125 local bypass
+C125,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,SN74LVC1G07 local bypass
+C126,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Power-good open-drain buffer local bypass
+C127,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,External-reset open-drain buffer local bypass
+C128,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,All-rail-valid logic local bypass
+C13,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Power qualification logic bypass
+C14,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U12 local input capacitor
+C15,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U12 low-noise LDO output capacitor
+C16,1,1.8nF,Murata,GRM155R71H182KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,TPS6287B calculated compensation CC
+C17,1,10pF,Murata,GRM1555C1H100JA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,TPS6287B HF compensation bypass CC2
+"C18,C19,C20,C21",4,22uF,Murata,GCM31CR71A226KE02L,Capacitor_SMD:C_1206_3216Metric,SMT,no,Core buck butterfly input capacitor
+C2,1,4.7nF,Murata,GRM155R71H472KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,USB shield HF coupling
+"C22,C23,C24,C25",4,100uF,Murata,GRT32EC70J107ME13L,Capacitor_SMD:C_1210_3225Metric,SMT,no,"Core output; 400-uF nominal, >=195-uF effective target"
+"C26,C27",2,10uF,Murata,GRM188R60J106ME47D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U14 input capacitor
+"C28,C29",2,22uF,Murata,GRM21BZ70J226ME44L,Capacitor_SMD:C_0805_2012Metric,SMT,no,U14 output capacitor
+"C3,C6",2,4.7nF,Murata,GRM155R71H472KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,eFuse output slew control
+"C30,C31",2,10uF,Murata,GRM188R60J106ME47D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U15 input capacitor
+"C32,C33",2,22uF,Murata,GRM21BZ70J226ME44L,Capacitor_SMD:C_0805_2012Metric,SMT,no,U15 output capacitor
+C34,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,LM3880 bypass
+C35,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U17 local input capacitor
+C36,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U17 low-noise LDO output capacitor
+C37,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U18 local input capacitor
+C38,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U18 low-noise LDO output capacitor
+C39,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U19 local input capacitor
+"C4,C7",2,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,eFuse local input bypass
+C40,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U19 low-noise LDO output capacitor
+C41,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U20 local input capacitor
+C42,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U20 low-noise LDO output capacitor
+"C43,C44,C45,C46,C47,C48,C49,C50,C51,C52,C53,C54,C55,C56,C57,C58,C59,C60",18,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Ti375 core/VCCA/VDD_SOC HF bypass
+"C5,C8",2,10uF,Murata,GRM188R60J106ME47D,Capacitor_SMD:C_0402_1005Metric,SMT,no,eFuse local output bypass
+"C61,C62,C63,C64",4,10uF,Murata,GRM188R60J106ME47D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Ti375 core local bulk
+"C65,C66,C67,C68,C69,C70",6,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Ti375 VCCAUX/HSIO/config bypass
+"C71,C72",2,10uF,Murata,GRM188R60J106ME47D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Ti375 1.8-V local bulk
+"C73,C74,C75,C76",4,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Ti375 HVIO bank bypass on VCC3V3
+C77,1,10uF,Murata,GRM188R60J106ME47D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Ti375 I/O-rail bulk on VCC3V3
+"C78,C79,C80,C81",4,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Ti375 HVIO bank bypass on VCC3V0_DIG
+C82,1,10uF,Murata,GRM188R60J106ME47D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Ti375 I/O-rail bulk on VCC3V0_DIG
+C83,1,27pF,Murata,600L270JT200T,board:Kyocera_600L_0402,SMT,no,High-Q 200-V C0G GNSS RF DC block
+C84,1,DNP,Murata,,Capacitor_SMD:C_0402_1005Metric,SMT,yes,RF tuning shunt C1
+C85,1,DNP,Murata,,Capacitor_SMD:C_0402_1005Metric,SMT,yes,RF tuning shunt C2
+C86,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Bias-switch input bypass
+C87,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Bias-switch output bypass before choke
+C88,1,15pF,Murata,GRM1555C1H150JA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,MAX2771 PLL loop-filter shunt capacitor
+C89,1,750pF,Murata,GRM1555C1H751JA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,MAX2771 PLL loop integrating capacitor
+C9,1,10nF,Murata,GRM155R71H103KA88D,Capacitor_SMD:C_0402_1005Metric,SMT,no,TPS2121 soft-start
+C90,1,10nF,Murata,GRM155R71H103KA88D,Capacitor_SMD:C_0402_1005Metric,SMT,no,MAX2771 external reference AC coupling
+"C91,C92,C93,C94,C95",5,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,MAX2771 local VCC3V0_RF bypass
+C96,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,MAX2771 local VCC3V0_RF bulk
+"C97,C98",2,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,MAX2771 local VCC3V0_DIG bypass
+C99,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,MAX2771 local VCC3V0_DIG bulk
+D1,1,ESD501,Texas Instruments,ESD501DPYR,board:Texas_DPY0002A_X1SON,SMT,no,0.3-pF bidirectional 12-V RF ESD protector
+D2,1,RESET ESD,onsemi,ESD5Z3.3T1G,Diode_SMD:D_SOD-523,SMT,no,External-reset connector ESD clamp
+FB1,1,600R@100MHz,Murata,BLM15AG601SN1D,Inductor_SMD:L_0402_1005Metric,SMT,no,IMU supply ferrite isolation
+FB2,1,600R@100MHz,Murata,BLM15AG601SN1D,Inductor_SMD:L_0402_1005Metric,SMT,no,FTDI USB-PHY supply ferrite
+FB3,1,600R@100MHz,Murata,BLM15AG601SN1D,Inductor_SMD:L_0402_1005Metric,SMT,no,FTDI PLL supply ferrite
+FL1,1,GPS L1/L1C SAW,Kyocera,SF14-1582M5UUS2,board:Kyocera_SF14_5pad,SMT,no,"1565.19-1585.65-MHz SAW, 1.2-dB typical insertion loss"
+J1,1,USB-C USB2 sink,GCT,USB4105-GF-A-120,Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal,SMT,no,"USB 2.0 Type-C receptacle, UFP/sink"
+J2,1,GPS L1 SMA,Amphenol RF,132289,Connector_Coaxial:SMA_Amphenol_132289_EdgeMount,THT,no,Edge-launch 50-ohm active GNSS antenna input
+J3,1,EXT_5V,Phoenix Contact,1935161,"TerminalBlock_Phoenix:TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal",THT,no,Clearly labelled external regulated 5-V input
+J4,1,EXT RESET_N,JST,SM02B-SRSS-TB(LF)(SN),Connector_JST:JST_SH_SM02B-SRSS-TB_1x02-1MP_P1.00mm_Horizontal,SMT,no,External active-low open-drain reset input; JST-SH 1.0-mm
+J5,1,ANT BIAS OFF/3V3/5V,Wuerth Elektronik,61300311121,Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical,THT,no,One-shunt hardware antenna bias selection; no shunt is OFF
+"JPMOD1,JPMOD2",2,PMOD 3.3 V,Amphenol ICC,67997-412HLF,board:Digilent_PMOD_2x6_P2.54mm,THT,no,"Digilent 2x6 PMOD: eight 3.3 V GPIO, two GND, two 3.3 V"
+"JPMOD3,JPMOD4",2,PMOD 1.8 V,Amphenol ICC,67997-412HLF,board:Digilent_PMOD_2x6_P2.54mm,THT,no,"Digilent 2x6 PMOD: eight 1.8 V GPIO, two GND, two 1.8 V"
+L1,1,100nH,Coilcraft,XEL4030-101MEC,board:Coilcraft_XEL4030,SMT,no,"Core inductor: 30-A saturation, 1.5-mohm DCR"
+"L2,L3",2,240nH,Murata,DFE201612E-R24M=P2,board:Murata_DFE201612E,SMT,no,TPS62867 manufacturer-recommended 6.6-A inductor
+L4,1,56nH,Coilcraft,0402HPH-56NXJRW,Inductor_SMD:L_0402_1005Metric,SMT,no,"L1 bias-tee choke: SRF 2.1 GHz, Q 64, 330 mA"
+Q1,1,MMBT3904,onsemi,MMBT3904LT1G,Package_TO_SOT_SMD:SOT-23,SMT,no,Power-good inverter: enables FTDI-to-FPGA buffers only after all rails are valid
+"R1,R2,R3,R4,R5",5,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Efinix mandatory 10-kohm 1% reference resistor
+R10,1,0R,Yageo,RC0402JR-070RL,Resistor_SMD:R_0402_1005Metric,SMT,yes,Optional direct shield bond
+R100,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,All-rail-good inverter base-current limiter
+R101,1,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Power-good inverter default-off base pull-down
+R102,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,External/manual reset input pull-up
+R103,1,1K,Yageo,RC0402FR-071KL,Resistor_SMD:R_0402_1005Metric,SMT,no,External-reset input current and ESD limiting
+R104,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,LM3880 final-flag pull-up for all-power logic
+R105,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,1.8-V power-good pull-up for all-power logic
+R106,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,3.3-V power-good pull-up for all-power logic
+"R11,R16",2,232K,Yageo,RC0402FR-07232KL,Resistor_SMD:R_0402_1005Metric,SMT,no,4.0-V nominal eFuse UV divider top
+"R12,R17",2,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,eFuse UV divider bottom
+"R13,R18",2,383K,Yageo,RC0402FR-07383KL,Resistor_SMD:R_0402_1005Metric,SMT,no,5.8-V nominal eFuse OV divider top
+"R14,R19",2,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,eFuse OV divider bottom
+R15,1,1.24K,Yageo,RC0402FR-071K24L,Resistor_SMD:R_0402_1005Metric,SMT,no,eFuse RILM=3334/ILIM
+R20,1,825R,Yageo,RC0402FR-07825RL,Resistor_SMD:R_0402_1005Metric,SMT,no,eFuse RILM=3334/ILIM
+R21,1,442K,Yageo,RC0402FR-07442KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS2121 IN1 5.75-V OV divider top
+R22,1,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS2121 IN1 OV divider bottom
+R23,1,442K,Yageo,RC0402FR-07442KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS2121 IN2 5.75-V OV divider top
+R24,1,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS2121 IN2 OV divider bottom
+R25,1,22.1K,Yageo,RC0402FR-0722K1L,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS2121 4.5-A typical output limit
+R26,1,15K,Yageo,RC0402FR-0715KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS6287B mandatory >=15-kohm EN series resistor
+R27,1,0R,Yageo,RC0402JR-070RL,Resistor_SMD:R_0402_1005Metric,SMT,no,Remote positive sense link at FPGA PDN
+R28,1,0R,Yageo,RC0402JR-070RL,Resistor_SMD:R_0402_1005Metric,SMT,no,Remote ground sense link at FPGA PDN
+R29,1,2.1K,Yageo,RC0402FR-072K1L,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS6287B calculated compensation RZ
+R30,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Core buck PG pull-up
+R31,1,133K,Yageo,RC0402FR-07133KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS62867 fixed 1.8 V VSET resistor
+R32,1,205K,Yageo,RC0402FR-07205KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS62867 fixed 3.3 V VSET resistor
+"R33,R34",2,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,LM3880 open-drain flag pull-up
+R35,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,FPGA CRESET_N configuration-rail pull-up
+R36,1,0R,Yageo,RC0402JR-070RL,Resistor_SMD:R_0402_1005Metric,SMT,no,Sequencer final-flag sense link
+R37,1,0R,Yageo,RC0402JR-070RL,Resistor_SMD:R_0402_1005Metric,SMT,no,1.8-V buck power-good sense link
+R38,1,0R,Yageo,RC0402JR-070RL,Resistor_SMD:R_0402_1005Metric,SMT,no,3.3-V buck power-good sense link
+R39,1,0R,Yageo,RC0402JR-070RL,Resistor_SMD:R_0402_1005Metric,SMT,no,RF tuning series link
+R40,1,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Bias switch follows selected source
+R41,1,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,No-jumper default OFF
+R42,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Antenna overcurrent pull-up
+R43,1,15K,Yageo,RC0402FR-0715KL,Resistor_SMD:R_0402_1005Metric,SMT,no,MAX2771 PLL loop-filter resistor
+R44,1,33R,Yageo,RC0402FR-0733RL,Resistor_SMD:R_0402_1005Metric,SMT,no,40-MHz ADC-clock source termination
+"R45,R46,R47,R48,R49,R50",6,22R,Yageo,RC0402FR-0722RL,Resistor_SMD:R_0402_1005Metric,SMT,no,MAX2771 source-series digital damping
+"R51,R52,R53,R54",4,22R,Yageo,RC0402FR-0722RL,Resistor_SMD:R_0402_1005Metric,SMT,no,MAX2771 serial/control source damping
+R55,1,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,MAX2771 remains shut down before FPGA configuration
+R56,1,33R,Yageo,RC0402FR-0733RL,Resistor_SMD:R_0402_1005Metric,SMT,no,40-MHz FPGA-clock source termination
+"R57,R58,R59",3,22R,Yageo,RC0402FR-0722RL,Resistor_SMD:R_0402_1005Metric,SMT,no,SafeSPI source-series damping
+R6,1,900K,Yageo,RC0402FR-07909KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TUSB320 VBUS_DET current limiter
+R60,1,22R,Yageo,RC0402FR-0722RL,Resistor_SMD:R_0402_1005Metric,SMT,no,SafeSPI MISO source damping at IMU
+R61,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Hold IMU reset until FPGA releases it
+R62,1,27R,Yageo,RC0402FR-0727RL,Resistor_SMD:R_0402_1005Metric,SMT,no,FTDI USB D+ series termination
+R63,1,27R,Yageo,RC0402FR-0727RL,Resistor_SMD:R_0402_1005Metric,SMT,no,FTDI USB D- series termination
+R64,1,12K,Yageo,RC0402FR-0712KL,Resistor_SMD:R_0402_1005Metric,SMT,no,"FT4232H USB PHY reference resistor, 1%"
+R65,1,4.7K,Yageo,RC0402FR-074K7L,Resistor_SMD:R_0402_1005Metric,SMT,no,Self-powered VBUS-present reset divider top
+R66,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Self-powered VBUS-present reset divider bottom
+R67,1,33R,Yageo,RC0402FR-0733RL,Resistor_SMD:R_0402_1005Metric,SMT,no,FTDI oscillator source termination
+R68,1,2.2K,Yageo,RC0402FR-072K2L,Resistor_SMD:R_0402_1005Metric,SMT,no,EEPROM shared-data isolation
+R69,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,EEPROM DO pull-up
+R7,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TUSB320 open-drain OUT1 pull-up
+"R70,R71,R72,R73",4,33R,Yageo,RC0402FR-0733RL,Resistor_SMD:R_0402_1005Metric,SMT,no,FTDI interface-1 hard-JTAG source damping
+"R74,R90,R91,R92",4,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Efinix-required hard-JTAG weak pull-up
+"R75,R76,R77,R78,R79,R80,R81,R82,R83",9,33R,Yageo,RC0402FR-0733RL,Resistor_SMD:R_0402_1005Metric,SMT,no,FT4232H channel signal damping
+R8,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TUSB320 open-drain OUT2 pull-up
+R84,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Configuration flash CS pull-up
+R85,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Efinix mandatory TEST_N weak pull-up
+R86,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Efinix mandatory CSI weak pull-up
+"R87,R88",2,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Configuration flash hold/write-protect pull-up
+R89,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Efinix-required CDONE open-drain pull-up
+R9,1,1M,Yageo,RC0402FR-071ML,Resistor_SMD:R_0402_1005Metric,SMT,no,USB shield bleed
+"R93,R94,R95,R96",4,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,RISC-V JTAG idle-state pull-up
+R97,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,FTDI FPGA-reset request default release
+R98,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS3808 open-drain power-good pull-up
+R99,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Keep FTDI-to-FPGA buffers disabled until power-good
+SW1,1,FPGA RESET,Omron,B3U-1000P,Button_Switch_SMD:SW_SPST_B3U-1000P,SMT,no,User-accessible momentary FPGA configuration reset
+TP1,1,U7 FLT,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
+TP10,1,3V3,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
+TP11,1,RF 3V0,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
+TP12,1,DIG 3V0,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
+TP13,1,CRESET_N,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
+TP14,1,CDONE,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
+TP15,1,GND,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
+TP2,1,U8 FLT,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
+TP3,1,ANT OC,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
+TP4,1,USB VBUS,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
+TP5,1,EXT 5V,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
+TP6,1,SYS 5V,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
+TP7,1,AUX 3V3,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
+TP8,1,CORE 0V95,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
+TP9,1,1V8,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
+U1,1,Ti375C529C3,Efinix,Ti375C529C3,Package_BGA:BGA-529_19x19mm_Layout23x23_P0.8mm,SMT,no,"Titanium Ti375 FPGA, commercial standard-power 0.95-V option, C529"
+U10,1,SN74LVC2G02,Texas Instruments,SN74LVC2G02DCUR,Package_SO:VSSOP-8_2.3x2mm_P0.5mm,SMT,no,USB 3-A advertisement NOR decode and mux-status inversion
+U11,1,SN74LVC1G32,Texas Instruments,SN74LVC1G32DBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Main-rail enable OR: qualified 3-A USB or selected external 5 V
+U12,1,TPS7A2033,Texas Instruments,TPS7A2033PDBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Always-on 300-mA auxiliary 3.3-V LDO
+U13,1,TPS6287B15HA0,Texas Instruments,TPS6287B15HA0WRZVR,board:Texas_RZV0024A_WQFN24,SMT,no,"15-A synchronous 0.95-V FPGA core/VCCA/VDD_SOC buck, fixed PWM"
+U14,1,TPS62867 1.8 V,Texas Instruments,TPS62867RQYR,board:Texas_RQY0009A_VQFN9,SMT,no,6-A synchronous 1.8 V FPGA auxiliary/I/O buck
+U15,1,TPS62867 3.3 V,Texas Instruments,TPS62867RQYR,board:Texas_RQY0009A_VQFN9,SMT,no,6-A synchronous 3.3 V FPGA auxiliary/I/O buck
+U16,1,LM3880-1AA,Texas Instruments,LM3880MF-1AA/NOPB,Package_TO_SOT_SMD:SOT-23-6,SMT,no,"Three-rail sequencer, 10-ms delay per rail"
+U17,1,TPS7A2030,Texas Instruments,TPS7A2030PDBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Dedicated low-noise 3.0-V MAX2771 analog LDO
+U18,1,TPS7A2030,Texas Instruments,TPS7A2030PDBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Dedicated low-noise 3.0-V MAX2771 digital and FPGA-bank LDO
+U19,1,TPS7A2030,Texas Instruments,TPS7A2030PDBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Dedicated low-noise 3.0-V oscillator LDO
+U2,1,FT4232H-56Q,FTDI,FT4232H-56Q-REEL,board:FTDI_VQFN56_EP5p9,SMT,no,Quad high-speed USB bridge; all four channels assigned
+U20,1,TPS7A2033,Texas Instruments,TPS7A2033PDBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Clean 3.3-V active-antenna bias LDO
+U21,1,MAX2771,Analog Devices,MAX2771ETI+,Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.25x3.25mm,SMT,no,GNSS receiver; both LNAs disabled; direct high-band mixer input
+U22,1,SCH16T-K01-1,Murata,SCH16T-K01-1,board:Murata_SCH16T_K01,SMT,no,"Six-DoF SafeSPI IMU, exact K01-1 variant"
+U23,1,16.368 MHz TCXO,Epson,X1G005441030125,board:Epson_TG2016SMN,SMT,no,TG2016SMN clipped-sine ±0.5-ppm MAX2771 reference
+U24,1,40.000 MHz XO,Epson,X1G004171041100,Oscillator:Oscillator_SMD_SeikoEpson_SG210-4Pin_2.5x2.0mm,SMT,no,SG-210STF ±25-ppm CMOS FPGA/system ADC oscillator
+U25,1,12.000 MHz XO,ECS,ECS-2520MV-120-BN-TR,Oscillator:Oscillator_SMD_ECS_2520MV-xxx-xx-4Pin_2.5x2.0mm,SMT,no,Current-production 12-MHz CMOS FT4232H clock
+U26,1,512-Mbit QSPI flash,ISSI,IS25WP512M-JLLE,Package_SON:WSON-8-1EP_6x5mm_P1.27mm_EP3.4x4.3mm,SMT,no,1.8-V 512-Mbit FPGA active-serial configuration flash
+U27,1,TPS22944,Texas Instruments,TPS22944DCKR,Package_TO_SOT_SMD:SOT-353_SC-70-5,SMT,no,Fixed 100-mA current-limited active-antenna load switch
+U28,1,TPS3808G30,Texas Instruments,TPS3808G30DBVR,Package_TO_SOT_SMD:SOT-23-6,SMT,no,3.0-V FPGA-bank supervisor; open-drain reset with 20-ms release delay
+U29,1,SN74LVC244A,Texas Instruments,SN74LVC244APWR,Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm,SMT,no,Ioff-protected FPGA-input buffer; automatically isolates when FPGA 3.3 V is off
+U3,1,93LC56B x16,Microchip,93LC56BT-I/OT,Package_TO_SOT_SMD:SOT-23-6,SMT,no,"FTDI descriptor/channel-mode EEPROM, fixed 16-bit organization"
+U30,1,SN74LVC1G125,Texas Instruments,SN74LVC1G125DBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Ioff-protected tri-state debug-GPIO buffer powered from FPGA 3.3 V
+U31,1,SN74LVC1G07,Texas Instruments,SN74LVC1G07DBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Open-drain FTDI reset request into FPGA CRESET_N
+U32,1,SN74LVC1G07,Texas Instruments,SN74LVC1G07DBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Open-drain all-rail-valid translation into FPGA CRESET_N
+U33,1,SN74LVC1G07,Texas Instruments,SN74LVC1G07DBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Open-drain external/manual reset isolation into FPGA CRESET_N
+U34,1,SN74LVC08A,Texas Instruments,SN74LVC08APWR,Package_SO:TSSOP-14_4.4x5mm_P0.65mm,SMT,no,Always-on all-rail power-valid logic for reset release and debug isolation
+U5,1,TUSB320LAI,Texas Instruments,TUSB320LAIRSW(R),Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm,SMT,no,USB Type-C port controller in UFP GPIO mode; integrated Rd on CC1/CC2
+U6,1,TPD2EUSB30A,Texas Instruments,TPD2EUSB30ADRTR,Package_TO_SOT_SMD:Texas_DRT-3,SMT,no,Low-capacitance USB 2.0 ESD protection
+"U7,U8",2,TPS259470A,Texas Instruments,TPS259470ARPWR,board:Texas_RPW0010A_QFN10,SMT,no,True-reverse-blocking eFuse; UV/OV/current/inrush protection
+U9,1,TPS2121,Texas Instruments,TPS2121RUXR,board:Texas_RUX0012A_VQFN12,SMT,no,4.5-A power mux; external input wins near-equal valid 5-V inputs
@@ -0,0 +1,12 @@
+ERC report (2026-08-15T18:09:04, Encoding UTF8)
+Report includes: Errors, Warnings, Exclusions
+
+***** Sheet /
+
+ ** ERC messages: 0  Errors 0  Warnings 0
+
+ ** Ignored checks:
+    - Global label only appears once in the schematic
+    - Four connection points are joined together
+    - SPICE model issue
+    - Assigned footprint doesn't match footprint filters
@@ -0,0 +1,210 @@
+Comment,Designator,Footprint,LCSC Part #,Manufacturer,Manufacturer Part Number,Quantity,Assembly Type,DNP
+100nF,C1,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+47uF,"C10,C11",Capacitor_SMD:C_1210_3225Metric,,Murata,GRM32ER70J476ME19L,2,SMT,no
+100nF,C100,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+1uF,C101,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+100nF,C102,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+100nF,C103,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+1uF,C104,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+10uF,C105,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM188R60J106ME47D,1,SMT,no
+1uF,C106,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+100nF,C107,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+100nF,"C108,C109",Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,2,SMT,no
+100nF,"C110,C111",Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,2,SMT,no
+1uF,C112,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+100nF,C113,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+100nF,C114,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+100nF,C115,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+100nF,C116,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+100nF,C117,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+100nF,C118,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+1uF,C119,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+100nF,C12,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+4.7nF,C120,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71H472KA01D,1,SMT,no
+4.7nF,C121,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71H472KA01D,1,SMT,no
+100nF,C122,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+100nF,C123,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+100nF,C124,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+100nF,C125,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+100nF,C126,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+100nF,C127,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+100nF,C128,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+100nF,C13,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+1uF,C14,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+1uF,C15,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+1.8nF,C16,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71H182KA01D,1,SMT,no
+10pF,C17,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM1555C1H100JA01D,1,SMT,no
+22uF,"C18,C19,C20,C21",Capacitor_SMD:C_1206_3216Metric,,Murata,GCM31CR71A226KE02L,4,SMT,no
+4.7nF,C2,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71H472KA01D,1,SMT,no
+100uF,"C22,C23,C24,C25",Capacitor_SMD:C_1210_3225Metric,,Murata,GRT32EC70J107ME13L,4,SMT,no
+10uF,"C26,C27",Capacitor_SMD:C_0402_1005Metric,,Murata,GRM188R60J106ME47D,2,SMT,no
+22uF,"C28,C29",Capacitor_SMD:C_0805_2012Metric,,Murata,GRM21BZ70J226ME44L,2,SMT,no
+4.7nF,"C3,C6",Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71H472KA01D,2,SMT,no
+10uF,"C30,C31",Capacitor_SMD:C_0402_1005Metric,,Murata,GRM188R60J106ME47D,2,SMT,no
+22uF,"C32,C33",Capacitor_SMD:C_0805_2012Metric,,Murata,GRM21BZ70J226ME44L,2,SMT,no
+100nF,C34,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
+1uF,C35,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+1uF,C36,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+1uF,C37,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+1uF,C38,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+1uF,C39,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+1uF,"C4,C7",Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,2,SMT,no
+1uF,C40,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+1uF,C41,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+1uF,C42,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+100nF,"C43,C44,C45,C46,C47,C48,C49,C50,C51,C52,C53,C54,C55,C56,C57,C58,C59,C60",Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,18,SMT,no
+10uF,"C5,C8",Capacitor_SMD:C_0402_1005Metric,,Murata,GRM188R60J106ME47D,2,SMT,no
+10uF,"C61,C62,C63,C64",Capacitor_SMD:C_0402_1005Metric,,Murata,GRM188R60J106ME47D,4,SMT,no
+100nF,"C65,C66,C67,C68,C69,C70",Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,6,SMT,no
+10uF,"C71,C72",Capacitor_SMD:C_0402_1005Metric,,Murata,GRM188R60J106ME47D,2,SMT,no
+100nF,"C73,C74,C75,C76",Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,4,SMT,no
+10uF,C77,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM188R60J106ME47D,1,SMT,no
+100nF,"C78,C79,C80,C81",Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,4,SMT,no
+10uF,C82,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM188R60J106ME47D,1,SMT,no
+27pF,C83,board:Kyocera_600L_0402,,Murata,600L270JT200T,1,SMT,no
+DNP,C84,Capacitor_SMD:C_0402_1005Metric,,Murata,,1,DNP,yes
+DNP,C85,Capacitor_SMD:C_0402_1005Metric,,Murata,,1,DNP,yes
+1uF,C86,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+1uF,C87,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+15pF,C88,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM1555C1H150JA01D,1,SMT,no
+750pF,C89,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM1555C1H751JA01D,1,SMT,no
+10nF,C9,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71H103KA88D,1,SMT,no
+10nF,C90,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71H103KA88D,1,SMT,no
+100nF,"C91,C92,C93,C94,C95",Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,5,SMT,no
+1uF,C96,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+100nF,"C97,C98",Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,2,SMT,no
+1uF,C99,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
+ESD501,D1,board:Texas_DPY0002A_X1SON,,Texas Instruments,ESD501DPYR,1,SMT,no
+RESET ESD,D2,Diode_SMD:D_SOD-523,,onsemi,ESD5Z3.3T1G,1,SMT,no
+600R@100MHz,FB1,Inductor_SMD:L_0402_1005Metric,,Murata,BLM15AG601SN1D,1,SMT,no
+600R@100MHz,FB2,Inductor_SMD:L_0402_1005Metric,,Murata,BLM15AG601SN1D,1,SMT,no
+600R@100MHz,FB3,Inductor_SMD:L_0402_1005Metric,,Murata,BLM15AG601SN1D,1,SMT,no
+GPS L1/L1C SAW,FL1,board:Kyocera_SF14_5pad,,Kyocera,SF14-1582M5UUS2,1,SMT,no
+USB-C USB2 sink,J1,Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal,,GCT,USB4105-GF-A-120,1,SMT,no
+GPS L1 SMA,J2,Connector_Coaxial:SMA_Amphenol_132289_EdgeMount,,Amphenol RF,132289,1,THT,no
+EXT_5V,J3,"TerminalBlock_Phoenix:TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal",,Phoenix Contact,1935161,1,THT,no
+EXT RESET_N,J4,Connector_JST:JST_SH_SM02B-SRSS-TB_1x02-1MP_P1.00mm_Horizontal,,JST,SM02B-SRSS-TB(LF)(SN),1,SMT,no
+ANT BIAS OFF/3V3/5V,J5,Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical,,Wuerth Elektronik,61300311121,1,THT,no
+PMOD 3.3 V,"JPMOD1,JPMOD2",board:Digilent_PMOD_2x6_P2.54mm,,Amphenol ICC,67997-412HLF,2,THT,no
+PMOD 1.8 V,"JPMOD3,JPMOD4",board:Digilent_PMOD_2x6_P2.54mm,,Amphenol ICC,67997-412HLF,2,THT,no
+100nH,L1,board:Coilcraft_XEL4030,,Coilcraft,XEL4030-101MEC,1,SMT,no
+240nH,"L2,L3",board:Murata_DFE201612E,,Murata,DFE201612E-R24M=P2,2,SMT,no
+56nH,L4,Inductor_SMD:L_0402_1005Metric,,Coilcraft,0402HPH-56NXJRW,1,SMT,no
+MMBT3904,Q1,Package_TO_SOT_SMD:SOT-23,,onsemi,MMBT3904LT1G,1,SMT,no
+10K,"R1,R2,R3,R4,R5",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,5,SMT,no
+0R,R10,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402JR-070RL,1,DNP,yes
+10K,R100,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+100K,R101,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07100KL,1,SMT,no
+10K,R102,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+1K,R103,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-071KL,1,SMT,no
+10K,R104,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+10K,R105,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+10K,R106,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+232K,"R11,R16",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07232KL,2,SMT,no
+100K,"R12,R17",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07100KL,2,SMT,no
+383K,"R13,R18",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07383KL,2,SMT,no
+100K,"R14,R19",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07100KL,2,SMT,no
+1.24K,R15,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-071K24L,1,SMT,no
+825R,R20,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07825RL,1,SMT,no
+442K,R21,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07442KL,1,SMT,no
+100K,R22,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07100KL,1,SMT,no
+442K,R23,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07442KL,1,SMT,no
+100K,R24,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07100KL,1,SMT,no
+22.1K,R25,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0722K1L,1,SMT,no
+15K,R26,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0715KL,1,SMT,no
+0R,R27,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402JR-070RL,1,SMT,no
+0R,R28,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402JR-070RL,1,SMT,no
+2.1K,R29,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-072K1L,1,SMT,no
+10K,R30,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+133K,R31,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07133KL,1,SMT,no
+205K,R32,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07205KL,1,SMT,no
+10K,"R33,R34",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,2,SMT,no
+10K,R35,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+0R,R36,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402JR-070RL,1,SMT,no
+0R,R37,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402JR-070RL,1,SMT,no
+0R,R38,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402JR-070RL,1,SMT,no
+0R,R39,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402JR-070RL,1,SMT,no
+100K,R40,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07100KL,1,SMT,no
+100K,R41,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07100KL,1,SMT,no
+10K,R42,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+15K,R43,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0715KL,1,SMT,no
+33R,R44,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0733RL,1,SMT,no
+22R,"R45,R46,R47,R48,R49,R50",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0722RL,6,SMT,no
+22R,"R51,R52,R53,R54",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0722RL,4,SMT,no
+100K,R55,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07100KL,1,SMT,no
+33R,R56,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0733RL,1,SMT,no
+22R,"R57,R58,R59",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0722RL,3,SMT,no
+900K,R6,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07909KL,1,SMT,no
+22R,R60,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0722RL,1,SMT,no
+10K,R61,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+27R,R62,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0727RL,1,SMT,no
+27R,R63,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0727RL,1,SMT,no
+12K,R64,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0712KL,1,SMT,no
+4.7K,R65,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-074K7L,1,SMT,no
+10K,R66,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+33R,R67,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0733RL,1,SMT,no
+2.2K,R68,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-072K2L,1,SMT,no
+10K,R69,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+10K,R7,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+33R,"R70,R71,R72,R73",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0733RL,4,SMT,no
+10K,"R74,R90,R91,R92",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,4,SMT,no
+33R,"R75,R76,R77,R78,R79,R80,R81,R82,R83",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0733RL,9,SMT,no
+10K,R8,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+10K,R84,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+10K,R85,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+10K,R86,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+10K,"R87,R88",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,2,SMT,no
+10K,R89,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+1M,R9,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-071ML,1,SMT,no
+10K,"R93,R94,R95,R96",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,4,SMT,no
+10K,R97,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+10K,R98,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+10K,R99,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
+FPGA RESET,SW1,Button_Switch_SMD:SW_SPST_B3U-1000P,,Omron,B3U-1000P,1,SMT,no
+U7 FLT,TP1,TestPoint:TestPoint_Pad_D1.0mm,,,,1,SMT,no
+3V3,TP10,TestPoint:TestPoint_Pad_D1.0mm,,,,1,SMT,no
+RF 3V0,TP11,TestPoint:TestPoint_Pad_D1.0mm,,,,1,SMT,no
+DIG 3V0,TP12,TestPoint:TestPoint_Pad_D1.0mm,,,,1,SMT,no
+CRESET_N,TP13,TestPoint:TestPoint_Pad_D1.0mm,,,,1,SMT,no
+CDONE,TP14,TestPoint:TestPoint_Pad_D1.0mm,,,,1,SMT,no
+GND,TP15,TestPoint:TestPoint_Pad_D1.0mm,,,,1,SMT,no
+U8 FLT,TP2,TestPoint:TestPoint_Pad_D1.0mm,,,,1,SMT,no
+ANT OC,TP3,TestPoint:TestPoint_Pad_D1.0mm,,,,1,SMT,no
+USB VBUS,TP4,TestPoint:TestPoint_Pad_D1.0mm,,,,1,SMT,no
+EXT 5V,TP5,TestPoint:TestPoint_Pad_D1.0mm,,,,1,SMT,no
+SYS 5V,TP6,TestPoint:TestPoint_Pad_D1.0mm,,,,1,SMT,no
+AUX 3V3,TP7,TestPoint:TestPoint_Pad_D1.0mm,,,,1,SMT,no
+CORE 0V95,TP8,TestPoint:TestPoint_Pad_D1.0mm,,,,1,SMT,no
+1V8,TP9,TestPoint:TestPoint_Pad_D1.0mm,,,,1,SMT,no
+Ti375C529C3,U1,Package_BGA:BGA-529_19x19mm_Layout23x23_P0.8mm,,Efinix,Ti375C529C3,1,SMT,no
+SN74LVC2G02,U10,Package_SO:VSSOP-8_2.3x2mm_P0.5mm,,Texas Instruments,SN74LVC2G02DCUR,1,SMT,no
+SN74LVC1G32,U11,Package_TO_SOT_SMD:SOT-23-5,,Texas Instruments,SN74LVC1G32DBVR,1,SMT,no
+TPS7A2033,U12,Package_TO_SOT_SMD:SOT-23-5,,Texas Instruments,TPS7A2033PDBVR,1,SMT,no
+TPS6287B15HA0,U13,board:Texas_RZV0024A_WQFN24,,Texas Instruments,TPS6287B15HA0WRZVR,1,SMT,no
+TPS62867 1.8 V,U14,board:Texas_RQY0009A_VQFN9,,Texas Instruments,TPS62867RQYR,1,SMT,no
+TPS62867 3.3 V,U15,board:Texas_RQY0009A_VQFN9,,Texas Instruments,TPS62867RQYR,1,SMT,no
+LM3880-1AA,U16,Package_TO_SOT_SMD:SOT-23-6,,Texas Instruments,LM3880MF-1AA/NOPB,1,SMT,no
+TPS7A2030,U17,Package_TO_SOT_SMD:SOT-23-5,,Texas Instruments,TPS7A2030PDBVR,1,SMT,no
+TPS7A2030,U18,Package_TO_SOT_SMD:SOT-23-5,,Texas Instruments,TPS7A2030PDBVR,1,SMT,no
+TPS7A2030,U19,Package_TO_SOT_SMD:SOT-23-5,,Texas Instruments,TPS7A2030PDBVR,1,SMT,no
+FT4232H-56Q,U2,board:FTDI_VQFN56_EP5p9,,FTDI,FT4232H-56Q-REEL,1,SMT,no
+TPS7A2033,U20,Package_TO_SOT_SMD:SOT-23-5,,Texas Instruments,TPS7A2033PDBVR,1,SMT,no
+MAX2771,U21,Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.25x3.25mm,,Analog Devices,MAX2771ETI+,1,SMT,no
+SCH16T-K01-1,U22,board:Murata_SCH16T_K01,,Murata,SCH16T-K01-1,1,SMT,no
+16.368 MHz TCXO,U23,board:Epson_TG2016SMN,,Epson,X1G005441030125,1,SMT,no
+40.000 MHz XO,U24,Oscillator:Oscillator_SMD_SeikoEpson_SG210-4Pin_2.5x2.0mm,,Epson,X1G004171041100,1,SMT,no
+12.000 MHz XO,U25,Oscillator:Oscillator_SMD_ECS_2520MV-xxx-xx-4Pin_2.5x2.0mm,,ECS,ECS-2520MV-120-BN-TR,1,SMT,no
+512-Mbit QSPI flash,U26,Package_SON:WSON-8-1EP_6x5mm_P1.27mm_EP3.4x4.3mm,,ISSI,IS25WP512M-JLLE,1,SMT,no
+TPS22944,U27,Package_TO_SOT_SMD:SOT-353_SC-70-5,,Texas Instruments,TPS22944DCKR,1,SMT,no
+TPS3808G30,U28,Package_TO_SOT_SMD:SOT-23-6,,Texas Instruments,TPS3808G30DBVR,1,SMT,no
+SN74LVC244A,U29,Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm,,Texas Instruments,SN74LVC244APWR,1,SMT,no
+93LC56B x16,U3,Package_TO_SOT_SMD:SOT-23-6,,Microchip,93LC56BT-I/OT,1,SMT,no
+SN74LVC1G125,U30,Package_TO_SOT_SMD:SOT-23-5,,Texas Instruments,SN74LVC1G125DBVR,1,SMT,no
+SN74LVC1G07,U31,Package_TO_SOT_SMD:SOT-23-5,,Texas Instruments,SN74LVC1G07DBVR,1,SMT,no
+SN74LVC1G07,U32,Package_TO_SOT_SMD:SOT-23-5,,Texas Instruments,SN74LVC1G07DBVR,1,SMT,no
+SN74LVC1G07,U33,Package_TO_SOT_SMD:SOT-23-5,,Texas Instruments,SN74LVC1G07DBVR,1,SMT,no
+SN74LVC08A,U34,Package_SO:TSSOP-14_4.4x5mm_P0.65mm,,Texas Instruments,SN74LVC08APWR,1,SMT,no
+TUSB320LAI,U5,Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm,,Texas Instruments,TUSB320LAIRSW(R),1,SMT,no
+TPD2EUSB30A,U6,Package_TO_SOT_SMD:Texas_DRT-3,,Texas Instruments,TPD2EUSB30ADRTR,1,SMT,no
+TPS259470A,"U7,U8",board:Texas_RPW0010A_QFN10,,Texas Instruments,TPS259470ARPWR,2,SMT,no
+TPS2121,U9,board:Texas_RUX0012A_VQFN12,,Texas Instruments,TPS2121RUXR,1,SMT,no
@@ -0,0 +1,22 @@
+# Referanslar
+
+Tasarım kararları Efinix Ti375 datasheet/konfigürasyon notları ve development
+board şeması; MAX2771, SCH16T, FT4232H ve güç komponentlerinin üretici
+datasheetleri; ayrıca JLCPCB JLC08161H-3313 stackup verileri kullanılarak alındı.
+
+Üretici PDF'leri boyut, lisans ve sürüm eskimesi nedeniyle Git deposuna dahil
+edilmez. Lokal `references/official/` klasörü çalışma kopyasında bulunabilir.
+Yeni karar alınırken üreticinin güncel resmi dokümanı kontrol edilmelidir.
+
+`jlcpcb/` altındaki JSON dosyaları seçilen üretim stackup'ının yerel hesap ve
+karşılaştırma verileridir. Kontrollü empedans üretim siparişinde üreticinin
+güncel stackup tablosuyla tekrar doğrulanmalıdır.
+
+Temel resmi kaynaklar:
+
+- Efinix Titanium Ti375 Datasheet: <https://www.efinixinc.com/docs/titanium375-ds-v1.7.pdf>
+- Efinix Titanium Configuration Guide: <https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v3.1.pdf>
+- Efinix Ti375 C529 Development Kit Guide: <https://www.efinixinc.com/docs/ti375c529-devkit-ug-v1.6.pdf>
+- Texas Instruments ürün/datasheet araması: <https://www.ti.com/>
+- Analog Devices MAX2771: <https://www.analog.com/en/products/max2771.html>
+- Murata SCH16T-K01: <https://www.murata.com/en-global/products/sensor/gyro/overview/lineup/sch16t-k01>
@@ -0,0 +1 @@
+{"success":true,"code":200,"message":null,"errorCode":null,"data":[{"impedanceConfigCoverlayId":560413206669881346,"systemCopperThickness":1.00,"coatingAboveSubstrate":1.00,"coatingAboveTrace":0.60,"coatingBetweenTraces":1.00,"layerType":1,"baseCopperThickness":0.33},{"impedanceConfigCoverlayId":560413206669881349,"systemCopperThickness":1.00,"coatingAboveSubstrate":1.00,"coatingAboveTrace":0.60,"coatingBetweenTraces":1.00,"layerType":1,"baseCopperThickness":0.50},{"impedanceConfigCoverlayId":560413206669881352,"systemCopperThickness":0.50,"coatingAboveSubstrate":1.00,"coatingAboveTrace":0.60,"coatingBetweenTraces":1.00,"layerType":2,"baseCopperThickness":0.50},{"impedanceConfigCoverlayId":560413206669881355,"systemCopperThickness":1.50,"coatingAboveSubstrate":1.00,"coatingAboveTrace":0.60,"coatingBetweenTraces":1.00,"layerType":1,"baseCopperThickness":1.00},{"impedanceConfigCoverlayId":560413206669881358,"systemCopperThickness":1.00,"coatingAboveSubstrate":1.00,"coatingAboveTrace":0.60,"coatingBetweenTraces":1.00,"layerType":2,"baseCopperThickness":1.00},{"impedanceConfigCoverlayId":560413206669881361,"systemCopperThickness":2.00,"coatingAboveSubstrate":1.20,"coatingAboveTrace":0.80,"coatingBetweenTraces":1.20,"layerType":1,"baseCopperThickness":1.50},{"impedanceConfigCoverlayId":560413206669881364,"systemCopperThickness":1.50,"coatingAboveSubstrate":1.00,"coatingAboveTrace":0.60,"coatingBetweenTraces":1.00,"layerType":2,"baseCopperThickness":1.50},{"impedanceConfigCoverlayId":560413206669881367,"systemCopperThickness":2.50,"coatingAboveSubstrate":1.20,"coatingAboveTrace":0.80,"coatingBetweenTraces":1.20,"layerType":1,"baseCopperThickness":2.00},{"impedanceConfigCoverlayId":560413206669881370,"systemCopperThickness":2.00,"coatingAboveSubstrate":1.20,"coatingAboveTrace":0.80,"coatingBetweenTraces":1.20,"layerType":2,"baseCopperThickness":2.00}]}
@@ -0,0 +1 @@
+{"success":true,"code":200,"message":null,"errorCode":null,"data":[{"impedanceConfigCopperTraceWidthId":560411994507636740,"baseCopperThickness":0.33,"systemCopperThickness":1.00,"traceCopperThickness":1.20,"traceWidthDelta":0.50,"layerType":1},{"impedanceConfigCopperTraceWidthId":560411994507636743,"baseCopperThickness":0.50,"systemCopperThickness":1.00,"traceCopperThickness":1.60,"traceWidthDelta":0.50,"layerType":1},{"impedanceConfigCopperTraceWidthId":560411994507636746,"baseCopperThickness":1.00,"systemCopperThickness":1.50,"traceCopperThickness":2.20,"traceWidthDelta":1.00,"layerType":1},{"impedanceConfigCopperTraceWidthId":560411994507636749,"baseCopperThickness":1.50,"systemCopperThickness":2.00,"traceCopperThickness":2.85,"traceWidthDelta":1.00,"layerType":1},{"impedanceConfigCopperTraceWidthId":560411994507636752,"baseCopperThickness":2.00,"systemCopperThickness":2.50,"traceCopperThickness":3.50,"traceWidthDelta":1.20,"layerType":1},{"impedanceConfigCopperTraceWidthId":560411994507636755,"baseCopperThickness":2.00,"systemCopperThickness":2.00,"traceCopperThickness":2.50,"traceWidthDelta":1.20,"layerType":2},{"impedanceConfigCopperTraceWidthId":560411994507636758,"baseCopperThickness":1.50,"systemCopperThickness":1.50,"traceCopperThickness":1.90,"traceWidthDelta":1.00,"layerType":2},{"impedanceConfigCopperTraceWidthId":560411994507636761,"baseCopperThickness":1.00,"systemCopperThickness":1.00,"traceCopperThickness":1.20,"traceWidthDelta":0.80,"layerType":2},{"impedanceConfigCopperTraceWidthId":560411994507636764,"baseCopperThickness":0.50,"systemCopperThickness":0.50,"traceCopperThickness":0.60,"traceWidthDelta":0.50,"layerType":2}]}
@@ -0,0 +1 @@
+kiutils==1.4.8
@@ -0,0 +1,144 @@
+# Üretim, doğrulama ve routing akışı
+
+## Gereksinimler
+
+- KiCad 10.x ve `kicad-cli`.
+- KiCad ile aynı sürümden `/usr/bin/python3` ve `pcbnew` modülü.
+- Python paketleri: `pip install -r requirements.txt`.
+- Yoğun sinyal routing aşaması için isteğe bağlı Freerouting 2.3.x.
+
+`pcbnew` kullanan scriptler sistem Python'u ile çalıştırılmalıdır. Normal
+Python ortamına yalnızca `pip install pcbnew` yapmak KiCad ABI uyumluluğunu
+garanti etmez.
+
+## Dosya üretim sırası
+
+Repository kökünden:
+
+```bash
+python3 scripts/generate_footprints.py
+python3 scripts/generate_kicad.py
+python3 scripts/generate_design_tables.py
+/usr/bin/python3 scripts/generate_pcb.py
+```
+
+Bu sıralama:
+
+1. Özel footprintleri üretir.
+2. `design_data.py` üzerinden şema hiyerarşisini ve BOM'u üretir.
+3. Efinity C529 paket verisine karşı pin tablolarını doğrular ve üretir.
+4. 8 katmanlı stackup, kurallar, zone'lar ve placement ile PCB'yi üretir.
+
+`design_data.py` çalıştırıldığında dahili bağlantı assertion'ları da yürütülür:
+
+```bash
+python3 scripts/design_data.py
+```
+
+## Şema ve placement doğrulaması
+
+```bash
+kicad-cli sch erc --severity-all \
+  -o outputs/erc_final_reset.rpt hardware/board.kicad_sch
+
+kicad-cli pcb drc --severity-all \
+  -o outputs/drc_final_placement.rpt hardware/board.kicad_pcb
+```
+
+Unrouted placement aşamasında unconnected-pad ve isolated-zone kayıtları
+beklenir. Clearance, short, courtyard, solder-mask, edge ve footprint hataları
+beklenmez.
+
+## Routing sırası
+
+### 1. BGA escape
+
+```bash
+/usr/bin/python3 scripts/preroute_bga.py \
+  hardware/board.kicad_pcb hardware/board_prerouted.kicad_pcb
+```
+
+Ti375'in bağlı ball'larına kilitli 0.8 mm pitch dogbone/via escape ekler.
+
+### 2. Yerel plane bağlantıları
+
+```bash
+/usr/bin/python3 scripts/stitch_plane_pads.py \
+  hardware/board_prerouted.kicad_pcb \
+  hardware/board_plane_stitched.kicad_pcb
+```
+
+Yalnızca altında gerçekten aynı nete ait dolu plane bulunan SMD güç/GND
+padlerini kısa dogbone ile bağlar. Bu işlem yüksek akım buck loop routinginin
+yerini tutmaz.
+
+### 3. Güç katı
+
+KiCad içinde önce aşağıdaki hatlar elle route edilmelidir:
+
+- TPS6287B15 giriş kapasitörü, SW, indüktör, çıkış kapasitörü ve remote-sense.
+- TPS62867 1.8 V ve 3.3 V converter loopları.
+- SYS5 dağıtımı ve ana güç geçişleri.
+- LDO giriş/çıkış bypass bağlantıları.
+
+SW node bakırı küçük tutulmalı; feedback/sense hatları SW ve indüktörden uzak,
+Kelvin bağlantılı götürülmelidir. Autorouter bu kararları vermez.
+
+### 4. Freerouting için sınıf bazlı DSN
+
+```bash
+/usr/bin/python3 scripts/export_routing_stage.py \
+  hardware/board_plane_stitched.kicad_pcb outputs/signal_stage.dsn \
+  --classes "Default;BGA_ESCAPE;CLOCK" \
+  --preview outputs/signal_stage_preview.kicad_pcb
+
+python3 scripts/prepare_freerouting_dsn.py \
+  outputs/signal_stage.dsn outputs/signal_stage_freerouting.dsn
+```
+
+İkinci script Freerouting 2.3.0/KiCad 10 DSN clearance ölçek farkını düzeltir;
+koordinatlara, track genişliklerine, via veya keepoutlara dokunmaz. Freerouting
+arayüzünde düzeltilmiş DSN açılır, en fazla 8 thread kullanılır ve sonuç `.ses`
+olarak kaydedilir.
+
+RF, USB, güç converter loopları ve hassas clock kararları otomatik sonuca
+bırakılmamalıdır. `to route` sayısının uzun süre düşmemesi halinde aynı işlemi
+saatlerce sürdürmek yerine placement/escape/keepout çatışması incelenmelidir.
+
+### 5. Kritik hatları kur ve session'ı sonlandır
+
+```bash
+/usr/bin/python3 scripts/finalize_routing.py \
+  outputs/signal_stage.ses \
+  --output hardware/board_routed.kicad_pcb
+```
+
+Bu işlem Freerouter'ın RF ve USB üzerindeki copperını kaldırır, denetlenmiş
+RF/USB geometrisini ekler, RF GND via fence'i kurar ve zone'ları doldurur.
+
+### 6. Final kontroller
+
+```bash
+kicad-cli pcb drc --severity-all --schematic-parity --refill-zones \
+  --save-board -o outputs/drc_final_routed.rpt \
+  hardware/board_routed.kicad_pcb
+```
+
+Final kartta unconnected item, short, clearance, isolated copper veya
+schematic-parity hatası kabul edilmez. RF uzunlukları, USB eşleşmesi, güç
+loopları, return path ve test-point erişimi görsel olarak da incelenmelidir.
+
+## Script özeti
+
+| Script | Görev |
+|---|---|
+| `design_data.py` | Tek kaynak komponent/net verisi ve bağlantı assertion'ları |
+| `generate_footprints.py` | Üretici land-patternlerinden özel footprint üretimi |
+| `generate_kicad.py` | Şema, sembol ve BOM üretimi |
+| `generate_design_tables.py` | Ti375 pinout/constraint ve MAX2771 tablo üretimi |
+| `generate_pcb.py` | Stackup, rule, zone ve deterministic placement üretimi |
+| `preroute_bga.py` | Kilitli Ti375 dogbone escape |
+| `stitch_plane_pads.py` | Yerel pad-to-plane bağlantıları |
+| `export_routing_stage.py` | Seçili net-class için DSN üretimi |
+| `prepare_freerouting_dsn.py` | Freerouting 2.3 clearance düzeltmesi |
+| `finalize_routing.py` | SES importu ve denetlenmiş RF/USB geometrisi |
@@ -0,0 +1,794 @@
+#!/usr/bin/env python3
+"""Single-source component and connectivity data for the GNSS/IMU FPGA PCB.
+
+Generated KiCad, BOM, pinout, and assembly data import this module. Ti375 ball
+data comes from the Efinity 2025.2 C529 resource DB, never a hand transcription.
+"""
+
+from __future__ import annotations
+
+import csv
+from dataclasses import dataclass, field
+from pathlib import Path
+
+ROOT = Path(__file__).resolve().parents[1]
+
+
+@dataclass
+class Pin:
+    number: str
+    name: str
+    net: str | None
+    etype: str = "passive"
+
+
+@dataclass
+class Component:
+    ref: str
+    value: str
+    mpn: str
+    manufacturer: str
+    footprint: str
+    pins: list[Pin]
+    description: str = ""
+    assembly: str = "SMT"
+    dnp: bool = False
+    fields: dict[str, str] = field(default_factory=dict)
+
+
+def p(number: str | int, name: str, net: str | None, etype: str = "passive") -> Pin:
+    return Pin(str(number), name, net, etype)
+
+
+components: list[Component] = []
+_refs = {"R": 0, "C": 0, "L": 0, "FB": 0, "TP": 0}
+
+
+def add(component: Component) -> Component:
+    assert not any(c.ref == component.ref for c in components), component.ref
+    components.append(component)
+    return component
+
+
+def two_pin(prefix: str, value: str, mpn: str, manufacturer: str,
+            footprint: str, net1: str, net2: str, description: str,
+            *, dnp: bool = False, ref: str | None = None) -> Component:
+    if ref is None:
+        _refs[prefix] += 1
+        ref = f"{prefix}{_refs[prefix]}"
+    return add(Component(ref, value, mpn, manufacturer, footprint,
+                         [p(1, "1", net1), p(2, "2", net2)],
+                         description, dnp=dnp))
+
+
+def r(value: str, net1: str, net2: str, *, mpn: str = "",
+      description: str = "Resistor", dnp: bool = False) -> Component:
+    values = {
+        "0R": "RC0402JR-070RL", "22R": "RC0402FR-0722RL",
+        "27R": "RC0402FR-0727RL", "33R": "RC0402FR-0733RL",
+        "825R": "RC0402FR-07825RL", "1K": "RC0402FR-071KL", "1.24K": "RC0402FR-071K24L",
+        "2.1K": "RC0402FR-072K1L", "2.2K": "RC0402FR-072K2L",
+        "4.7K": "RC0402FR-074K7L", "10K": "RC0402FR-0710KL",
+        "12K": "RC0402FR-0712KL", "15K": "RC0402FR-0715KL",
+        "22.1K": "RC0402FR-0722K1L", "100K": "RC0402FR-07100KL",
+        "133K": "RC0402FR-07133KL", "205K": "RC0402FR-07205KL",
+        "232K": "RC0402FR-07232KL", "383K": "RC0402FR-07383KL",
+        "442K": "RC0402FR-07442KL", "900K": "RC0402FR-07909KL",
+        "1M": "RC0402FR-071ML",
+    }
+    return two_pin("R", value, mpn or values.get(value, ""), "Yageo",
+                   "Resistor_SMD:R_0402_1005Metric", net1, net2, description,
+                   dnp=dnp)
+
+
+def c(value: str, net1: str, net2: str, *, mpn: str = "",
+      footprint: str = "Capacitor_SMD:C_0402_1005Metric",
+      description: str = "MLCC", dnp: bool = False) -> Component:
+    values = {
+        "10pF": "GRM1555C1H100JA01D", "15pF": "GRM1555C1H150JA01D",
+        "27pF": "600L270JT200T", "750pF": "GRM1555C1H751JA01D",
+        "1.8nF": "GRM155R71H182KA01D", "4.7nF": "GRM155R71H472KA01D",
+        "10nF": "GRM155R71H103KA88D", "100nF": "GRM155R71A104KA01D",
+        "470nF": "GCM155C71A474KE36D", "1uF": "GRM155R60J105KE19D",
+        "10uF": "GRM188R60J106ME47D", "22uF": "GRM21BZ70J226ME44L",
+        "47uF": "GRM32ER70J476ME19L", "100uF": "GRT32EC70J107ME13L",
+    }
+    return two_pin("C", value, mpn or values.get(value, ""), "Murata",
+                   footprint, net1, net2, description, dnp=dnp)
+
+
+def tp(net: str, label: str) -> Component:
+    _refs["TP"] += 1
+    return add(Component(f"TP{_refs['TP']}", label, "", "",
+                         "TestPoint:TestPoint_Pad_D1.0mm",
+                         [p(1, label, net)], "Local labelled SMT bring-up test pad", "SMT"))
+
+
+def add_ic(ref: str, value: str, mpn: str, manufacturer: str, footprint: str,
+           pins: list[Pin], description: str) -> Component:
+    return add(Component(ref, value, mpn, manufacturer, footprint, pins, description))
+
+
+# Ti375 C529: represent every package ball exactly once.
+pinout = {row["ball"]: row for row in csv.DictReader(
+    (ROOT / "docs" / "ti375_pinout.csv").open(newline=""))}
+package = list(csv.DictReader((ROOT / "docs" / "ti375_c529_package.csv").open(newline="")))
+
+
+def fpga_net(row: dict[str, str]) -> str | None:
+    ball = row["ball"]
+    if ball in pinout:
+        return pinout[ball]["signal"]
+    name = row["official_pad_name"]
+    if name in ("GND", "VQPS"):
+        return "GND"
+    if name == "VCC" or name.startswith("VCCA_") or name == "VDD_SOC":
+        return "VCC0V95"
+    if name == "VCCAUX":
+        return "VCC1V8"
+    vccio = {
+        "VCCIO4C": "VCC1V8", "VCCIO4A_4B": "VCC1V8", "VCCIO4D": "VCC1V8",
+        "VCCIO2A": "VCC1V8", "VCCIO2B": "VCC1V8", "VCCIO2C": "VCC1V8",
+        "VCCIO2D": "VCC1V8", "VCCIO2E": "VCC1V8",
+        "VCCIO33_BR0": "VCC3V0_DIG", "VCCIO33_TR0": "VCC3V0_DIG",
+        "VCCIO33_TR1": "VCC3V3", "VCCIO33_TR2": "VCC3V3",
+        "VCCIO33_BR3_BR4": "VCC3V3", "VCCIO33_TL1_TL5": "VCC3V3",
+        "VCCIO33_BL2_BL3": "VCC3V3",
+    }
+    if name in vccio:
+        return vccio[name]
+    if name.startswith("REF_RES_"):
+        return name
+    # JTAG_VCCIO_SEL floats for 3.3-V BR3/BR4. Official NC, unused DDR
+    # signals, and unused DDR rails remain open per Efinix's unused table.
+    return None
+
+
+fpga_pins = []
+for row in package:
+    etype = {"power": "power_in", "input": "input", "output": "output"}.get(
+        row["direction"], "bidirectional")
+    fpga_pins.append(p(row["ball"], row["official_pad_name"], fpga_net(row), etype))
+add_ic("U1", "Ti375C529C3", "Ti375C529C3", "Efinix",
+       "Package_BGA:BGA-529_19x19mm_Layout23x23_P0.8mm", fpga_pins,
+       "Titanium Ti375 FPGA, commercial standard-power 0.95-V option, C529")
+for name in ("REF_RES_4A", "REF_RES_4B", "REF_RES_4D", "REF_RES_2E", "REF_RES_2A"):
+    r("10K", name, "GND", description="Efinix mandatory 10-kohm 1% reference resistor")
+
+
+# USB-C and sink role detection.
+add_ic("J1", "USB-C USB2 sink", "USB4105-GF-A-120", "GCT",
+       "Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal", [
+           p("A1", "GND", "GND"), p("A4", "VBUS", "VBUS_RAW"), p("A5", "CC1", "USB_CC1"),
+           p("A6", "D+", "USB_D_P"), p("A7", "D-", "USB_D_N"), p("A8", "SBU1", None),
+           p("A9", "VBUS", "VBUS_RAW"), p("A12", "GND", "GND"),
+           p("B1", "GND", "GND"), p("B4", "VBUS", "VBUS_RAW"), p("B5", "CC2", "USB_CC2"),
+           p("B6", "D+", "USB_D_P"), p("B7", "D-", "USB_D_N"), p("B8", "SBU2", None),
+           p("B9", "VBUS", "VBUS_RAW"), p("B12", "GND", "GND"), p("SH", "SHIELD", "USB_SHIELD")],
+       "USB 2.0 Type-C receptacle, UFP/sink")
+add_ic("U5", "TUSB320LAI", "TUSB320LAIRSW(R)", "Texas Instruments",
+       "Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm", [
+           p(1, "CC1", "USB_CC1", "bidirectional"), p(2, "CC2", "USB_CC2", "bidirectional"),
+           p(3, "PORT", "GND", "input"), p(4, "VBUS_DET", "USB_VBUS_DET", "input"),
+           p(5, "ADDR", None), p(6, "OUT3", None, "output"),
+           p(7, "OUT1", "TUSB_OUT1", "output"), p(8, "OUT2", "TUSB_OUT2", "output"),
+           p(9, "ID", None, "output"), p(10, "GND", "GND", "power_in"),
+           p(11, "EN_N", "GND", "input"), p(12, "VDD", "VCC3V3_AUX", "power_in")],
+       "USB Type-C port controller in UFP GPIO mode; integrated Rd on CC1/CC2")
+r("900K", "VBUS_RAW", "USB_VBUS_DET", description="TUSB320 VBUS_DET current limiter")
+r("10K", "VCC3V3_AUX", "TUSB_OUT1", description="TUSB320 open-drain OUT1 pull-up")
+r("10K", "VCC3V3_AUX", "TUSB_OUT2", description="TUSB320 open-drain OUT2 pull-up")
+c("100nF", "VCC3V3_AUX", "GND", description="TUSB320 local bypass")
+add_ic("U6", "TPD2EUSB30A", "TPD2EUSB30ADRTR", "Texas Instruments",
+       "Package_TO_SOT_SMD:Texas_DRT-3", [p(1, "IO1", "USB_D_P"), p(2, "GND", "GND"), p(3, "IO2", "USB_D_N")],
+       "Low-capacitance USB 2.0 ESD protection")
+c("4.7nF", "USB_SHIELD", "GND", description="USB shield HF coupling")
+r("1M", "USB_SHIELD", "GND", description="USB shield bleed")
+r("0R", "USB_SHIELD", "GND", description="Optional direct shield bond", dnp=True)
+
+add_ic("J3", "EXT_5V", "1935161", "Phoenix Contact",
+       "TerminalBlock_Phoenix:TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal", [
+           p(1, "EXT_5V", "EXT5_RAW", "power_in"), p(2, "GND", "GND", "power_in")],
+       "Clearly labelled external regulated 5-V input")
+components[-1].assembly = "THT"
+
+
+def add_efuse(ref: str, input_net: str, output_net: str, ilim: str) -> None:
+    add_ic(ref, "TPS259470A", "TPS259470ARPWR", "Texas Instruments",
+           "board:Texas_RPW0010A_QFN10", [
+               p(1, "EN/UVLO", f"{ref}_ENUV", "input"), p(2, "OVLO", f"{ref}_OV", "input"),
+               p(3, "AUXOFF", None, "open_collector"), p(4, "FLT", f"{ref}_FLT", "open_collector"),
+               p(5, "IN", input_net, "power_in"), p(6, "OUT", output_net, "power_out"),
+               p(7, "DVDT", f"{ref}_DVDT", "output"), p(8, "GND", "GND", "power_in"),
+               p(9, "ILM", f"{ref}_ILM", "output"), p(10, "ITIMER", None)],
+           "True-reverse-blocking eFuse; UV/OV/current/inrush protection")
+    r("232K", input_net, f"{ref}_ENUV", description="4.0-V nominal eFuse UV divider top")
+    r("100K", f"{ref}_ENUV", "GND", description="eFuse UV divider bottom")
+    r("383K", input_net, f"{ref}_OV", description="5.8-V nominal eFuse OV divider top")
+    r("100K", f"{ref}_OV", "GND", description="eFuse OV divider bottom")
+    r(ilim, f"{ref}_ILM", "GND", description="eFuse RILM=3334/ILIM")
+    c("4.7nF", f"{ref}_DVDT", "GND", description="eFuse output slew control")
+    c("1uF", input_net, "GND", description="eFuse local input bypass")
+    c("10uF", output_net, "GND", description="eFuse local output bypass")
+    tp(f"{ref}_FLT", f"{ref} FLT")
+
+
+add_efuse("U7", "VBUS_RAW", "USB5_PROT", "1.24K")  # 2.69 A typical, <3 A max.
+add_efuse("U8", "EXT5_RAW", "EXT5_PROT", "825R")   # 4.04 A typical.
+add_ic("U9", "TPS2121", "TPS2121RUXR", "Texas Instruments", "board:Texas_RUX0012A_VQFN12", [
+    p(1, "OUT", "SYS5", "power_out"), p(2, "IN2", "EXT5_PROT", "power_in"), p(3, "CP2", "VCC3V3_AUX", "input"),
+    p(4, "OV2", "MUX_OV2", "input"), p(5, "OV1", "MUX_OV1", "input"), p(6, "PR1", "GND", "input"),
+    p(7, "IN1", "USB5_PROT", "power_in"), p(8, "OUT", "SYS5", "power_out"), p(9, "ST", "MUX_ST", "output"),
+    p(10, "ILM", "MUX_ILM", "output"), p(11, "SS", "MUX_SS", "output"), p(12, "GND", "GND", "power_in")],
+    "4.5-A power mux; external input wins near-equal valid 5-V inputs")
+r("442K", "USB5_PROT", "MUX_OV1", description="TPS2121 IN1 5.75-V OV divider top")
+r("100K", "MUX_OV1", "GND", description="TPS2121 IN1 OV divider bottom")
+r("442K", "EXT5_PROT", "MUX_OV2", description="TPS2121 IN2 5.75-V OV divider top")
+r("100K", "MUX_OV2", "GND", description="TPS2121 IN2 OV divider bottom")
+r("22.1K", "MUX_ILM", "GND", description="TPS2121 4.5-A typical output limit")
+c("10nF", "MUX_SS", "GND", description="TPS2121 soft-start")
+for _ in range(2):
+    c("47uF", "SYS5", "GND", footprint="Capacitor_SMD:C_1210_3225Metric", description="5-V system bulk")
+
+add_ic("U10", "SN74LVC2G02", "SN74LVC2G02DCUR", "Texas Instruments",
+       "Package_SO:VSSOP-8_2.3x2mm_P0.5mm", [
+           p(1, "1Y", "USB_3A_OK", "output"), p(2, "1A", "TUSB_OUT1", "input"), p(3, "1B", "TUSB_OUT2", "input"),
+           p(4, "GND", "GND", "power_in"), p(5, "2A", "MUX_ST", "input"), p(6, "2B", "MUX_ST", "input"),
+           p(7, "2Y", "EXT_SELECTED", "output"), p(8, "VCC", "VCC3V3_AUX", "power_in")],
+       "USB 3-A advertisement NOR decode and mux-status inversion")
+add_ic("U11", "SN74LVC1G32", "SN74LVC1G32DBVR", "Texas Instruments", "Package_TO_SOT_SMD:SOT-23-5", [
+    p(1, "A", "USB_3A_OK", "input"), p(2, "B", "EXT_SELECTED", "input"), p(3, "GND", "GND", "power_in"),
+    p(4, "Y", "MAIN_EN", "output"), p(5, "VCC", "VCC3V3_AUX", "power_in")],
+    "Main-rail enable OR: qualified 3-A USB or selected external 5 V")
+c("100nF", "VCC3V3_AUX", "GND", description="Power-qualification logic local bypass")
+c("100nF", "VCC3V3_AUX", "GND", description="Power qualification logic bypass")
+
+
+# Rail generation and Efinix sequencing.
+def add_ldo(ref: str, value: str, mpn: str, vin: str, vout: str, enable: str, desc: str) -> None:
+    add_ic(ref, value, mpn, "Texas Instruments", "Package_TO_SOT_SMD:SOT-23-5", [
+        p(1, "IN", vin, "power_in"), p(2, "GND", "GND", "power_in"), p(3, "EN", enable, "input"),
+        p(4, "NC", None), p(5, "OUT", vout, "power_out")], desc)
+    c("1uF", vin, "GND", description=f"{ref} local input capacitor")
+    c("1uF", vout, "GND", description=f"{ref} low-noise LDO output capacitor")
+
+
+add_ldo("U12", "TPS7A2033", "TPS7A2033PDBVR", "SYS5", "VCC3V3_AUX", "SYS5",
+        "Always-on 300-mA auxiliary 3.3-V LDO")
+add_ic("U13", "TPS6287B15HA0", "TPS6287B15HA0WRZVR", "Texas Instruments",
+       "board:Texas_RZV0024A_WQFN24", [
+           p(1, "VOSNS", "CORE_SENSE_P", "input"), p(2, "EN", "CORE_EN_R", "input"),
+           p(3, "VSET1", "GND", "input"), p(4, "VSET2", "SYS5", "input"),
+           p(5, "VIN", "SYS5", "power_in"), p(6, "VIN", "SYS5", "power_in"),
+           p(7, "GND", "GND", "power_in"), p(8, "GND", "GND", "power_in"),
+           p(9, "SW", "CORE_SW", "power_out"), p(10, "SW", "CORE_SW", "power_out"),
+           p(11, "SW", "CORE_SW", "power_out"), p(12, "SW", "CORE_SW", "power_out"),
+           p(13, "GND", "GND", "power_in"), p(14, "GND", "GND", "power_in"),
+           p(15, "VIN", "SYS5", "power_in"), p(16, "VIN", "SYS5", "power_in"),
+           p(17, "SYNCOUT", None, "output"), p(18, "MODE/SYNC", "SYS5", "input"),
+           p(19, "SDA", "GND", "bidirectional"), p(20, "SCL", "GND", "bidirectional"),
+           p(21, "PG", "CORE_PG", "open_collector"), p(22, "AGND", "GND", "power_in"),
+           p(23, "COMP", "CORE_COMP", "input"), p(24, "GOSNS", "CORE_SENSE_N", "input"),
+           p(25, "THERMAL_PADS", "GND", "power_in")],
+       "15-A synchronous 0.95-V FPGA core/VCCA/VDD_SOC buck, fixed PWM")
+r("15K", "MAIN_EN", "CORE_EN_R", description="TPS6287B mandatory >=15-kohm EN series resistor")
+r("0R", "VCC0V95", "CORE_SENSE_P", description="Remote positive sense link at FPGA PDN")
+r("0R", "GND", "CORE_SENSE_N", description="Remote ground sense link at FPGA PDN")
+r("2.1K", "CORE_COMP", "CORE_COMP_RC", description="TPS6287B calculated compensation RZ")
+c("1.8nF", "CORE_COMP_RC", "GND", description="TPS6287B calculated compensation CC")
+c("10pF", "CORE_COMP", "GND", description="TPS6287B HF compensation bypass CC2")
+two_pin("L", "100nH", "XEL4030-101MEC", "Coilcraft", "board:Coilcraft_XEL4030",
+        "CORE_SW", "VCC0V95", "Core inductor: 30-A saturation, 1.5-mohm DCR")
+for _ in range(4):
+    c("22uF", "SYS5", "GND", mpn="GCM31CR71A226KE02L",
+      footprint="Capacitor_SMD:C_1206_3216Metric", description="Core buck butterfly input capacitor")
+for _ in range(4):
+    c("100uF", "VCC0V95", "GND", footprint="Capacitor_SMD:C_1210_3225Metric",
+      description="Core output; 400-uF nominal, >=195-uF effective target")
+r("10K", "VCC3V3_AUX", "CORE_PG", description="Core buck PG pull-up")
+
+
+def add_tps62867(ref: str, output: str, sw: str, en: str, pg: str, vset: str, value: str) -> None:
+    add_ic(ref, f"TPS62867 {value}", "TPS62867RQYR", "Texas Instruments",
+           "board:Texas_RQY0009A_VQFN9", [
+               p(1, "AGND", "GND", "power_in"), p(2, "PGND", "GND", "power_in"),
+               p(3, "VIN", "SYS5", "power_in"), p(4, "EN", en, "input"),
+               p(5, "PG", pg, "open_collector"), p(6, "VSET/MODE", f"{ref}_VSET", "input"),
+               p(7, "SW", sw, "power_out"), p(8, "VOS", output, "input"), p(9, "FB", output, "input")],
+           f"6-A synchronous {value} FPGA auxiliary/I/O buck")
+    r(vset, f"{ref}_VSET", "GND", description=f"TPS62867 fixed {value} VSET resistor")
+    two_pin("L", "240nH", "DFE201612E-R24M=P2", "Murata", "board:Murata_DFE201612E",
+            sw, output, "TPS62867 manufacturer-recommended 6.6-A inductor")
+    for _ in range(2):
+        c("10uF", "SYS5", "GND", description=f"{ref} input capacitor")
+    for _ in range(2):
+        c("22uF", output, "GND", footprint="Capacitor_SMD:C_0805_2012Metric",
+          description=f"{ref} output capacitor")
+
+
+add_tps62867("U14", "VCC1V8", "BUCK1V8_SW", "SEQ_FLAG1", "PG_1V8", "133K", "1.8 V")
+add_tps62867("U15", "VCC3V3", "BUCK3V3_SW", "SEQ_FLAG2", "PG_3V3", "205K", "3.3 V")
+add_ic("U16", "LM3880-1AA", "LM3880MF-1AA/NOPB", "Texas Instruments",
+       "Package_TO_SOT_SMD:SOT-23-6", [
+           p(1, "VCC", "VCC3V3_AUX", "power_in"), p(2, "GND", "GND", "power_in"),
+           p(3, "EN", "CORE_PG", "input"), p(4, "FLAG3", "SEQ_FLAG3", "open_collector"),
+           p(5, "FLAG2", "SEQ_FLAG2", "open_collector"), p(6, "FLAG1", "SEQ_FLAG1", "open_collector")],
+       "Three-rail sequencer, 10-ms delay per rail")
+for net in ("SEQ_FLAG1", "SEQ_FLAG2"):
+    r("10K", "VCC3V3_AUX", net, description="LM3880 open-drain flag pull-up")
+c("100nF", "VCC3V3_AUX", "GND", description="LM3880 bypass")
+
+# Keep the four independent rail-valid indications separate from CRESET_N.
+# They are combined below by always-on logic; this prevents an intentional
+# configuration reset from corrupting the power-good state used to isolate the
+# FTDI drivers.
+r("10K", "VCC1V8", "FPGA_CRESET_N", description="FPGA CRESET_N configuration-rail pull-up")
+r("0R", "SEQ_FLAG3", "PWR_SEQ_OK", description="Sequencer final-flag sense link")
+r("0R", "PG_1V8", "PWR_1V8_OK", description="1.8-V buck power-good sense link")
+r("0R", "PG_3V3", "PWR_3V3_OK", description="3.3-V buck power-good sense link")
+
+add_ldo("U17", "TPS7A2030", "TPS7A2030PDBVR", "VCC3V3", "VCC3V0_RF", "VCC3V3",
+        "Dedicated low-noise 3.0-V MAX2771 analog LDO")
+add_ldo("U18", "TPS7A2030", "TPS7A2030PDBVR", "VCC3V3", "VCC3V0_DIG", "VCC3V3",
+        "Dedicated low-noise 3.0-V MAX2771 digital and FPGA-bank LDO")
+add_ldo("U19", "TPS7A2030", "TPS7A2030PDBVR", "VCC3V3", "VCC3V0_CLK", "VCC3V3",
+        "Dedicated low-noise 3.0-V oscillator LDO")
+add_ldo("U20", "TPS7A2033", "TPS7A2033PDBVR", "SYS5", "VCC3V3_ANT", "MAIN_EN",
+        "Clean 3.3-V active-antenna bias LDO")
+
+# The supervisor is powered from the always-on auxiliary rail, so its open-drain
+# output remains authoritative even while the monitored 3.0-V FPGA I/O rail is
+# absent.  Its 20-ms (CT open) timeout also guarantees the configuration delay
+# after the last FPGA supply becomes valid.  Power-good is kept separate from
+# user/FTDI reset so the JTAG buffers stay enabled during deliberate resets.
+add_ic("U28", "TPS3808G30", "TPS3808G30DBVR", "Texas Instruments",
+       "Package_TO_SOT_SMD:SOT-23-6", [
+           p(1, "RESET_N", "FPGA_POWER_OK_N", "open_collector"), p(2, "GND", "GND", "power_in"),
+           p(3, "MR_N", "VCC3V3_AUX", "input"), p(4, "CT", None, "input"),
+           p(5, "SENSE", "VCC3V0_DIG", "input"), p(6, "VDD", "VCC3V3_AUX", "power_in")],
+       "3.0-V FPGA-bank supervisor; open-drain reset with 20-ms release delay")
+
+# Always-on AND tree creates a true all-rail-valid signal.  The fourth gate
+# includes LM3880 FLAG3, so both the programmed power-up interval and every
+# converter/supervisor indication must be valid before FPGA-facing FTDI
+# drivers are enabled or CRESET_N is released.
+add_ic("U34", "SN74LVC08A", "SN74LVC08APWR", "Texas Instruments",
+       "Package_SO:TSSOP-14_4.4x5mm_P0.65mm", [
+           p(1, "1A", "CORE_PG", "input"), p(2, "1B", "PWR_1V8_OK", "input"),
+           p(3, "1Y", "PWR_OK_A", "output"),
+           p(4, "2A", "PWR_3V3_OK", "input"), p(5, "2B", "FPGA_POWER_OK_N", "input"),
+           p(6, "2Y", "PWR_OK_B", "output"), p(7, "GND", "GND", "power_in"),
+           p(8, "3Y", "PWR_OK_C", "output"), p(9, "3A", "PWR_OK_A", "input"),
+           p(10, "3B", "PWR_OK_B", "input"),
+           p(11, "4Y", "ALL_FPGA_POWER_OK", "output"),
+           p(12, "4A", "PWR_OK_C", "input"), p(13, "4B", "PWR_SEQ_OK", "input"),
+           p(14, "VCC", "VCC3V3_AUX", "power_in")],
+       "Always-on all-rail power-valid logic for reset release and debug isolation")
+
+# Dense reference-design-style bypassing plus one bulk group per rail.
+for _ in range(18):
+    c("100nF", "VCC0V95", "GND", description="Ti375 core/VCCA/VDD_SOC HF bypass")
+for _ in range(4):
+    c("10uF", "VCC0V95", "GND", description="Ti375 core local bulk")
+for _ in range(6):
+    c("100nF", "VCC1V8", "GND", description="Ti375 VCCAUX/HSIO/config bypass")
+for _ in range(2):
+    c("10uF", "VCC1V8", "GND", description="Ti375 1.8-V local bulk")
+for rail in ("VCC3V3", "VCC3V0_DIG"):
+    for _ in range(4):
+        c("100nF", rail, "GND", description=f"Ti375 HVIO bank bypass on {rail}")
+    c("10uF", rail, "GND", description=f"Ti375 I/O-rail bulk on {rail}")
+
+
+# MAX2771 direct MIXIN_HI path and OFF/3.3-V/5-V active-antenna bias.
+add_ic("J2", "GPS L1 SMA", "132289", "Amphenol RF",
+       "Connector_Coaxial:SMA_Amphenol_132289_EdgeMount",
+       [p(1, "RF", "RF_SMA"), p(2, "GND", "GND")],
+       "Edge-launch 50-ohm active GNSS antenna input")
+components[-1].assembly = "THT"
+add_ic("D1", "ESD501", "ESD501DPYR", "Texas Instruments", "board:Texas_DPY0002A_X1SON",
+       [p(1, "RF", "RF_SMA"), p(2, "GND", "GND")],
+       "0.3-pF bidirectional 12-V RF ESD protector")
+c("27pF", "RF_SMA", "RF_PRE_SAW", mpn="600L270JT200T", footprint="board:Kyocera_600L_0402",
+  description="High-Q 200-V C0G GNSS RF DC block")
+add_ic("FL1", "GPS L1/L1C SAW", "SF14-1582M5UUS2", "Kyocera", "board:Kyocera_SF14_5pad", [
+    p(1, "IN", "RF_PRE_SAW"), p(2, "GND", "GND"), p(3, "GND", "GND"),
+    p(4, "OUT", "RF_POST_SAW"), p(5, "GND", "GND")],
+    "1565.19-1585.65-MHz SAW, 1.2-dB typical insertion loss")
+c("DNP", "RF_POST_SAW", "GND", mpn="", description="RF tuning shunt C1", dnp=True)
+r("0R", "RF_POST_SAW", "MAX_MIXIN_HI", description="RF tuning series link")
+c("DNP", "MAX_MIXIN_HI", "GND", mpn="", description="RF tuning shunt C2", dnp=True)
+
+add_ic("J5", "ANT BIAS OFF/3V3/5V", "61300311121", "Wuerth Elektronik",
+       "Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical", [
+           p(1, "3V3", "VCC3V3_ANT", "power_in"), p(2, "SELECT", "ANT_BIAS_SEL", "power_in"),
+           p(3, "5V", "SYS5", "power_in")],
+       "One-shunt hardware antenna bias selection; no shunt is OFF")
+components[-1].assembly = "THT"
+add_ic("U27", "TPS22944", "TPS22944DCKR", "Texas Instruments",
+       "Package_TO_SOT_SMD:SOT-353_SC-70-5", [
+           p(1, "VOUT", "ANT_BIAS_SW", "power_out"), p(2, "GND", "GND", "power_in"),
+           p(3, "OC", "ANT_BIAS_OC", "open_collector"), p(4, "ON", "ANT_BIAS_ON", "input"),
+           p(5, "VIN", "ANT_BIAS_SEL", "power_in")],
+       "Fixed 100-mA current-limited active-antenna load switch")
+r("100K", "ANT_BIAS_SEL", "ANT_BIAS_ON", description="Bias switch follows selected source")
+r("100K", "ANT_BIAS_ON", "GND", description="No-jumper default OFF")
+r("10K", "VCC3V3_AUX", "ANT_BIAS_OC", description="Antenna overcurrent pull-up")
+c("1uF", "ANT_BIAS_SEL", "GND", description="Bias-switch input bypass")
+c("1uF", "ANT_BIAS_SW", "GND", description="Bias-switch output bypass before choke")
+two_pin("L", "56nH", "0402HPH-56NXJRW", "Coilcraft", "Inductor_SMD:L_0402_1005Metric",
+        "ANT_BIAS_SW", "RF_SMA", "L1 bias-tee choke: SRF 2.1 GHz, Q 64, 330 mA")
+tp("ANT_BIAS_OC", "ANT OC")
+
+add_ic("U21", "MAX2771", "MAX2771ETI+", "Analog Devices",
+       "Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.25x3.25mm", [
+           p(1, "CPOUT", "MAX_CPOUT", "output"), p(2, "VCCCP", "VCC3V0_RF", "power_in"),
+           p(3, "XTAL", "MAX_XTAL", "input"), p(4, "CLKOUT", "MAX_CLKOUT_SRC", "output"),
+           p(5, "ADC_CLKIN", "MAX_ADC_CLKIN", "input"), p(6, "VCCD", "VCC3V0_DIG", "power_in"),
+           p(7, "SDATA", "MAX_SDATA_DEV", "bidirectional"), p(8, "SCLK", "MAX_SCLK_DEV", "input"),
+           p(9, "CSN", "MAX_CSN_DEV", "input"), p(10, "Q1", "MAX_Q1_DEV", "output"),
+           p(11, "Q0", "MAX_Q0_DEV", "output"), p(12, "I0", "MAX_I0_DEV", "output"),
+           p(13, "I1", "MAX_I1_DEV", "output"), p(14, "VCCADC", "VCC3V0_DIG", "power_in"),
+           p(15, "ANAIPOUT", None, "output"), p(16, "ANAINOUT", None, "output"),
+           p(17, "LD", "MAX_LD_DEV", "output"), p(18, "SHDN", "MAX_SHDN_DEV", "input"),
+           p(19, "LNAIN_HI", None, "input"), p(20, "LNAIN_LO", None, "input"), p(21, "NC", None),
+           p(22, "VCCRF", "VCC3V0_RF", "power_in"), p(23, "LNAOUT_LO", None, "output"),
+           p(24, "LNAOUT_HI", None, "output"), p(25, "MIXIN_HI", "MAX_MIXIN_HI", "input"),
+           p(26, "MIXIN_LO", None, "input"), p(27, "VCCIF", "VCC3V0_RF", "power_in"),
+           p(28, "VCCVCO", "VCC3V0_RF", "power_in"), p(29, "EP", "GND", "power_in")],
+       "GNSS receiver; both LNAs disabled; direct high-band mixer input")
+
+# Official typical topology: CPOUT has a small direct capacitor and an R-C
+# series integrating branch to ground.
+c("15pF", "MAX_CPOUT", "GND", description="MAX2771 PLL loop-filter shunt capacitor")
+r("15K", "MAX_CPOUT", "MAX_LOOP_RC", description="MAX2771 PLL loop-filter resistor")
+c("750pF", "MAX_LOOP_RC", "GND", description="MAX2771 PLL loop integrating capacitor")
+c("10nF", "TCXO16_OUT", "MAX_XTAL", description="MAX2771 external reference AC coupling")
+r("33R", "OSC40_OUT", "MAX_ADC_CLKIN", description="40-MHz ADC-clock source termination")
+for signal in ("MAX_CLKOUT", "MAX_I0", "MAX_I1", "MAX_Q0", "MAX_Q1", "MAX_LD"):
+    source = f"{signal}_SRC" if signal == "MAX_CLKOUT" else f"{signal}_DEV"
+    r("22R", source, signal, description="MAX2771 source-series digital damping")
+for signal in ("MAX_SCLK", "MAX_CSN", "MAX_SDATA", "MAX_SHDN"):
+    r("22R", signal, f"{signal}_DEV", description="MAX2771 serial/control source damping")
+r("100K", "MAX_SHDN_DEV", "GND", description="MAX2771 remains shut down before FPGA configuration")
+for rail, count in (("VCC3V0_RF", 5), ("VCC3V0_DIG", 2)):
+    for _ in range(count):
+        c("100nF", rail, "GND", description=f"MAX2771 local {rail} bypass")
+    c("1uF", rail, "GND", description=f"MAX2771 local {rail} bulk")
+
+add_ic("U23", "16.368 MHz TCXO", "X1G005441030125", "Epson", "board:Epson_TG2016SMN", [
+    p(1, "NC", None), p(2, "GND", "GND", "power_in"), p(3, "OUT", "TCXO16_OUT", "output"),
+    p(4, "VCC", "VCC3V0_CLK", "power_in")],
+    "TG2016SMN clipped-sine ±0.5-ppm MAX2771 reference")
+c("100nF", "VCC3V0_CLK", "GND", description="16.368-MHz TCXO bypass")
+c("1uF", "VCC3V0_CLK", "GND", description="Clock-rail local bulk")
+add_ic("U24", "40.000 MHz XO", "X1G004171041100", "Epson",
+       "Oscillator:Oscillator_SMD_SeikoEpson_SG210-4Pin_2.5x2.0mm", [
+    p(1, "ST", "VCC3V0_CLK", "input"), p(2, "GND", "GND", "power_in"),
+    p(3, "OUT", "OSC40_OUT", "output"), p(4, "VCC", "VCC3V0_CLK", "power_in")],
+    "SG-210STF ±25-ppm CMOS FPGA/system ADC oscillator")
+r("33R", "OSC40_OUT", "CLK_40M_FPGA", description="40-MHz FPGA-clock source termination")
+c("100nF", "VCC3V0_CLK", "GND", description="40-MHz oscillator bypass")
+
+
+# Exact Murata SCH16T-K01-1 SafeSPI pinout and carrier-board capacitors.
+add_ic("U22", "SCH16T-K01-1", "SCH16T-K01-1", "Murata", "board:Murata_SCH16T_K01", [
+    p(1, "HS_GND", "GND", "power_in"), p(2, "RESERVED", None),
+    p(3, "TA9_GND", "GND", "power_in"), p(4, "TA8_GND", "GND", "power_in"),
+    p(5, "RESERVED_GND", "GND", "power_in"), p(6, "EXTRESN", "IMU_EXTRESN", "input"),
+    p(7, "RESERVED_GND", "GND", "power_in"), p(8, "V3P3", "IMU_3V3", "power_in"),
+    p(9, "GND", "GND", "power_in"), p(10, "VREGA2", "IMU_VREGA2", "power_out"),
+    p(11, "VREGA", "IMU_VREGA2", "power_out"), p(12, "GND", "GND", "power_in"),
+    p(13, "GND", "GND", "power_in"), p(14, "VREGD2", "IMU_VREGD", "power_out"),
+    p(15, "VREGD", "IMU_VREGD", "power_out"), p(16, "GND", "GND", "power_in"),
+    p(17, "V3P3", "IMU_3V3", "power_in"), p(18, "VDDIO", "VCC3V3", "power_in"),
+    p(19, "MISO", "IMU_MISO_DEV", "output"), p(20, "DRY_SYNC", "IMU_DRY_SYNC", "bidirectional"),
+    p(21, "SCK", "IMU_SCK_DEV", "input"), p(22, "CS", "IMU_CS_DEV", "input"),
+    p(23, "MOSI", "IMU_MOSI_DEV", "input"), p(24, "HS_GND", "GND", "power_in")],
+    "Six-DoF SafeSPI IMU, exact K01-1 variant")
+two_pin("FB", "600R@100MHz", "BLM15AG601SN1D", "Murata", "Inductor_SMD:L_0402_1005Metric",
+        "VCC3V3", "IMU_3V3", "IMU supply ferrite isolation")
+for signal in ("IMU_SCK", "IMU_MOSI", "IMU_CS"):
+    r("22R", signal, f"{signal}_DEV", description="SafeSPI source-series damping")
+r("22R", "IMU_MISO_DEV", "IMU_MISO", description="SafeSPI MISO source damping at IMU")
+r("10K", "IMU_EXTRESN", "GND", description="Hold IMU reset until FPGA releases it")
+c("100nF", "IMU_3V3", "GND", description="Murata V3P3 HF bypass")
+c("1uF", "IMU_3V3", "GND", description="Murata V3P3 local capacitor")
+c("10uF", "IMU_VREGA2", "GND", description="Murata required VREGA2 capacitor")
+c("1uF", "IMU_VREGD", "GND", description="Murata required VREGD capacitor")
+c("100nF", "VCC3V3", "GND", description="Murata VDDIO bypass")
+
+
+# FT4232H follows the Efinix development-kit interface order:
+# A/interface 0 = RISC-V JTAG, B/interface 1 = FPGA hard JTAG.
+ftdi_pins = [
+    p(1, "EECS", "FTDI_EECS", "output"), p(2, "VCORE", "FTDI_1V8", "power_in"),
+    p(3, "OSCI", "FTDI_OSCI", "input"), p(4, "OSCO", None, "output"),
+    p(5, "VPHY", "FTDI_VPHY", "power_in"), p(6, "REF", "FTDI_REF", "input"),
+    p(7, "DM", "FTDI_D_N", "bidirectional"), p(8, "DP", "FTDI_D_P", "bidirectional"),
+    p(9, "VPLL", "FTDI_VPLL", "power_in"), p(10, "TEST", "GND", "input"),
+    p(11, "RESET_N", "FTDI_RESET_N", "input"),
+    p(12, "ADBUS0/TCK", "FTDI_A_TCK_SRC", "bidirectional"),
+    p(13, "ADBUS1/TDI", "FTDI_A_TDI_SRC", "bidirectional"),
+    p(14, "ADBUS2/TDO", "FTDI_A_TDO_SRC", "bidirectional"),
+    p(15, "ADBUS3/TMS", "FTDI_A_TMS_SRC", "bidirectional"),
+    p(16, "VCCIO", "VCC3V3_AUX", "power_in"),
+    p(17, "ADBUS4", None, "bidirectional"), p(18, "ADBUS5", None, "bidirectional"),
+    p(19, "ADBUS6", None, "bidirectional"), p(20, "ADBUS7", None, "bidirectional"),
+    p(21, "GND", "GND", "power_in"),
+    p(22, "BDBUS0/TCK", "FTDI_B_TCK_SRC", "bidirectional"),
+    p(23, "BDBUS1/TDI", "FTDI_B_TDI_SRC", "bidirectional"),
+    p(24, "BDBUS2/TDO", "FTDI_B_TDO_SRC", "bidirectional"),
+    p(25, "BDBUS3/TMS", "FTDI_B_TMS_SRC", "bidirectional"),
+    p(26, "BDBUS4", "FTDI_B_RESET_N_SRC", "bidirectional"), p(27, "BDBUS5", None, "bidirectional"),
+    p(28, "BDBUS6", None, "bidirectional"), p(29, "BDBUS7", None, "bidirectional"),
+    p(30, "SUSPEND_N", None, "output"), p(31, "VCORE", "FTDI_1V8", "power_in"),
+    p(32, "CDBUS0/TXD", "FTDI_C_TXD_SRC", "bidirectional"),
+    p(33, "CDBUS1/RXD", "FTDI_C_RXD_SRC", "bidirectional"),
+    p(34, "CDBUS2", None, "bidirectional"), p(35, "CDBUS3", None, "bidirectional"),
+    p(36, "VCCIO", "VCC3V3_AUX", "power_in"),
+    p(37, "CDBUS4", None, "bidirectional"), p(38, "CDBUS5", None, "bidirectional"),
+    p(39, "CDBUS6", None, "bidirectional"), p(40, "CDBUS7", None, "bidirectional"),
+    p(41, "GND", "GND", "power_in"),
+    p(42, "DDBUS0/TXD", "FTDI_D_TXD_SRC", "bidirectional"),
+    p(43, "VREGOUT", "FTDI_1V8", "power_out"), p(44, "VREGIN", "VCC3V3_AUX", "power_in"),
+    p(45, "GND", "GND", "power_in"),
+    p(46, "DDBUS1/RXD", "FTDI_D_RXD_SRC", "bidirectional"),
+    p(47, "DDBUS2/RTS", "FTDI_D_DBG_SRC", "bidirectional"),
+    p(48, "DDBUS3", None, "bidirectional"), p(49, "DDBUS4", None, "bidirectional"),
+    p(50, "VCCIO", "VCC3V3_AUX", "power_in"),
+    p(51, "DDBUS5", None, "bidirectional"), p(52, "DDBUS6", None, "bidirectional"),
+    p(53, "DDBUS7", None, "bidirectional"), p(54, "PWREN_N", None, "output"),
+    p(55, "EEDATA", "FTDI_EEDATA", "bidirectional"), p(56, "EECLK", "FTDI_EECLK", "output"),
+    p(57, "EP", "GND", "power_in")]
+add_ic("U2", "FT4232H-56Q", "FT4232H-56Q-REEL", "FTDI", "board:FTDI_VQFN56_EP5p9",
+       ftdi_pins, "Quad high-speed USB bridge; all four channels assigned")
+r("27R", "USB_D_P", "FTDI_D_P", description="FTDI USB D+ series termination")
+r("27R", "USB_D_N", "FTDI_D_N", description="FTDI USB D- series termination")
+r("12K", "FTDI_REF", "GND", description="FT4232H USB PHY reference resistor, 1%")
+r("4.7K", "VBUS_RAW", "FTDI_RESET_N", description="Self-powered VBUS-present reset divider top")
+r("10K", "FTDI_RESET_N", "GND", description="Self-powered VBUS-present reset divider bottom")
+for _ in range(2):
+    c("100nF", "VCC3V3_AUX", "GND", description="FT4232H VCCIO/VREGIN bypass")
+for _ in range(2):
+    c("100nF", "FTDI_1V8", "GND", description="FT4232H VCORE bypass")
+c("1uF", "FTDI_1V8", "GND", description="FT4232H regulator output capacitor")
+two_pin("FB", "600R@100MHz", "BLM15AG601SN1D", "Murata", "Inductor_SMD:L_0402_1005Metric",
+        "VCC3V3_AUX", "FTDI_VPHY", "FTDI USB-PHY supply ferrite")
+two_pin("FB", "600R@100MHz", "BLM15AG601SN1D", "Murata", "Inductor_SMD:L_0402_1005Metric",
+        "VCC3V3_AUX", "FTDI_VPLL", "FTDI PLL supply ferrite")
+c("100nF", "FTDI_VPHY", "GND", description="FTDI VPHY bypass")
+c("100nF", "FTDI_VPLL", "GND", description="FTDI VPLL bypass")
+
+add_ic("U25", "12.000 MHz XO", "ECS-2520MV-120-BN-TR", "ECS",
+       "Oscillator:Oscillator_SMD_ECS_2520MV-xxx-xx-4Pin_2.5x2.0mm", [
+    p(1, "OE", "VCC3V3_AUX", "input"), p(2, "GND", "GND", "power_in"),
+    p(3, "OUT", "FTDI_OSC12", "output"), p(4, "VDD", "VCC3V3_AUX", "power_in")],
+    "Current-production 12-MHz CMOS FT4232H clock")
+r("33R", "FTDI_OSC12", "FTDI_OSCI", description="FTDI oscillator source termination")
+c("100nF", "VCC3V3_AUX", "GND", description="FTDI oscillator local bypass")
+
+add_ic("U3", "93LC56B x16", "93LC56BT-I/OT", "Microchip", "Package_TO_SOT_SMD:SOT-23-6", [
+    p(1, "CS", "FTDI_EECS", "input"), p(2, "CLK", "FTDI_EECLK", "input"),
+    p(3, "DI", "FTDI_EEDATA", "input"), p(4, "DO", "FTDI_EEDO", "output"),
+    p(5, "VSS", "GND", "power_in"), p(6, "VCC", "VCC3V3_AUX", "power_in")],
+    "FTDI descriptor/channel-mode EEPROM, fixed 16-bit organization")
+r("2.2K", "FTDI_EEDO", "FTDI_EEDATA", description="EEPROM shared-data isolation")
+r("10K", "FTDI_EEDO", "VCC3V3_AUX", description="EEPROM DO pull-up")
+c("100nF", "VCC3V3_AUX", "GND", description="FTDI EEPROM bypass")
+
+# FTDI is intentionally powered from the always-on debug rail.  All signals
+# that can drive the FPGA therefore pass through Ioff-capable buffers powered
+# by the FPGA's 3.3-V I/O rail.  When the FPGA rail is absent, the buffer
+# outputs are high impedance and no unpowered FPGA pin can be back-driven.
+add_ic("U29", "SN74LVC244A", "SN74LVC244APWR", "Texas Instruments",
+       "Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm", [
+           p(1, "1OE_N", "FTDI_FPGA_BUF_OE_N", "input"),
+           p(2, "1A1", "FTDI_A_TCK_SRC", "input"), p(18, "1Y1", "BUF_A_TCK", "output"),
+           p(4, "1A2", "FTDI_A_TDI_SRC", "input"), p(16, "1Y2", "BUF_A_TDI", "output"),
+           p(6, "1A3", "FTDI_A_TMS_SRC", "input"), p(14, "1Y3", "BUF_A_TMS", "output"),
+           p(8, "1A4", "FTDI_B_TCK_SRC", "input"), p(12, "1Y4", "BUF_B_TCK", "output"),
+           p(19, "2OE_N", "FTDI_FPGA_BUF_OE_N", "input"),
+           p(11, "2A1", "FTDI_B_TDI_SRC", "input"), p(9, "2Y1", "BUF_B_TDI", "output"),
+           p(13, "2A2", "FTDI_B_TMS_SRC", "input"), p(7, "2Y2", "BUF_B_TMS", "output"),
+           p(15, "2A3", "FTDI_C_TXD_SRC", "input"), p(5, "2Y3", "BUF_C_TXD", "output"),
+           p(17, "2A4", "FTDI_D_TXD_SRC", "input"), p(3, "2Y4", "BUF_D_TXD", "output"),
+           p(10, "GND", "GND", "power_in"), p(20, "VCC", "VCC3V3", "power_in")],
+       "Ioff-protected FPGA-input buffer; automatically isolates when FPGA 3.3 V is off")
+add_ic("U30", "SN74LVC1G125", "SN74LVC1G125DBVR", "Texas Instruments",
+       "Package_TO_SOT_SMD:SOT-23-5", [p(1, "OE_N", "FTDI_FPGA_BUF_OE_N", "input"),
+           p(2, "A", "FTDI_D_DBG_SRC", "input"),
+           p(3, "GND", "GND", "power_in"), p(4, "Y", "BUF_D_DBG", "output"),
+           p(5, "VCC", "VCC3V3", "power_in")],
+       "Ioff-protected tri-state debug-GPIO buffer powered from FPGA 3.3 V")
+add_ic("U31", "SN74LVC1G07", "SN74LVC1G07DBVR", "Texas Instruments",
+       "Package_TO_SOT_SMD:SOT-23-5", [p(1, "NC", None), p(2, "A", "FTDI_B_RESET_N_SRC", "input"),
+           p(3, "GND", "GND", "power_in"), p(4, "Y_OD", "FPGA_CRESET_N", "open_collector"),
+           p(5, "VCC", "VCC3V3_AUX", "power_in")],
+       "Open-drain FTDI reset request into FPGA CRESET_N")
+add_ic("U32", "SN74LVC1G07", "SN74LVC1G07DBVR", "Texas Instruments",
+       "Package_TO_SOT_SMD:SOT-23-5", [p(1, "NC", None), p(2, "A", "ALL_FPGA_POWER_OK", "input"),
+           p(3, "GND", "GND", "power_in"), p(4, "Y_OD", "FPGA_CRESET_N", "open_collector"),
+           p(5, "VCC", "VCC3V3_AUX", "power_in")],
+       "Open-drain all-rail-valid translation into FPGA CRESET_N")
+add_ic("U33", "SN74LVC1G07", "SN74LVC1G07DBVR", "Texas Instruments",
+       "Package_TO_SOT_SMD:SOT-23-5", [p(1, "NC", None), p(2, "A", "EXT_RESET_FILTER_N", "input"),
+           p(3, "GND", "GND", "power_in"), p(4, "Y_OD", "FPGA_CRESET_N", "open_collector"),
+           p(5, "VCC", "VCC1V8", "power_in")],
+       "Open-drain external/manual reset isolation into FPGA CRESET_N")
+add_ic("Q1", "MMBT3904", "MMBT3904LT1G", "onsemi", "Package_TO_SOT_SMD:SOT-23", [
+           p(1, "B", "FTDI_BUF_OE_BASE", "input"), p(2, "E", "GND", "power_in"),
+           p(3, "C", "FTDI_FPGA_BUF_OE_N", "open_collector")],
+       "Power-good inverter: enables FTDI-to-FPGA buffers only after all rails are valid")
+
+for src, dst in (("BUF_B_TCK", "HARD_TCK"), ("BUF_B_TMS", "HARD_TMS"),
+                 ("BUF_B_TDI", "HARD_TDI"), ("HARD_TDO", "FTDI_B_TDO_SRC")):
+    r("33R", src, dst, description="FTDI interface-1 hard-JTAG source damping")
+r("10K", "VCC3V3", "HARD_TMS", description="Efinix-required hard-JTAG weak pull-up")
+c("100nF", "VCC3V3_AUX", "GND", description="Additional FT4232H channel-A VCCIO bypass")
+for src, dst in (("BUF_A_TCK", "RISCV_TCK"), ("BUF_A_TDI", "RISCV_TDI"),
+                 ("BUF_A_TMS", "RISCV_TMS"), ("RISCV_TDO", "FTDI_A_TDO_SRC"),
+                 ("BUF_C_TXD", "UART0_RX"), ("UART0_TX", "FTDI_C_RXD_SRC"),
+                 ("BUF_D_TXD", "UART1_RX"), ("UART1_TX", "FTDI_D_RXD_SRC"),
+                 ("BUF_D_DBG", "FTDI_DBG_GPIO")):
+    r("33R", src, dst, description="FT4232H channel signal damping")
+
+# Active-serial flash and four compact Digilent-format PMOD connectors.
+add_ic("U26", "512-Mbit QSPI flash", "IS25WP512M-JLLE", "ISSI",
+       "Package_SON:WSON-8-1EP_6x5mm_P1.27mm_EP3.4x4.3mm", [
+           p(1, "CS_N", "QSPI_CS_N", "input"), p(2, "SO/IO1", "QSPI_IO1", "bidirectional"),
+           p(3, "WP_N/IO2", "QSPI_IO2", "bidirectional"), p(4, "GND", "GND", "power_in"),
+           p(5, "SI/IO0", "QSPI_IO0", "bidirectional"), p(6, "SCLK", "QSPI_SCLK", "input"),
+           p(7, "HOLD_N/IO3", "QSPI_IO3", "bidirectional"), p(8, "VCC", "VCC1V8", "power_in"),
+           p(9, "EP", "GND", "power_in")],
+       "1.8-V 512-Mbit FPGA active-serial configuration flash")
+r("10K", "VCC1V8", "QSPI_CS_N", description="Configuration flash CS pull-up")
+r("10K", "VCC1V8", "FPGA_TEST_N", description="Efinix mandatory TEST_N weak pull-up")
+r("10K", "VCC1V8", "FPGA_CSI", description="Efinix mandatory CSI weak pull-up")
+for net in ("QSPI_IO2", "QSPI_IO3"):
+    r("10K", "VCC1V8", net, description="Configuration flash hold/write-protect pull-up")
+c("100nF", "VCC1V8", "GND", description="Configuration flash bypass")
+c("1uF", "VCC1V8", "GND", description="Configuration flash local bulk")
+
+
+def add_pmod(ref: str, prefix: str, rail: str, voltage: str) -> None:
+    pins = [p(i, f"IO{i}", f"{prefix}_{i}") for i in (1, 2, 3, 4)]
+    pins += [p(5, "GND", "GND"), p(6, voltage, rail)]
+    pins += [p(i, f"IO{i}", f"{prefix}_{i}") for i in (7, 8, 9, 10)]
+    pins += [p(11, "GND", "GND"), p(12, voltage, rail)]
+    add_ic(ref, f"PMOD {voltage}", "67997-412HLF", "Amphenol ICC",
+           "board:Digilent_PMOD_2x6_P2.54mm", pins,
+           f"Digilent 2x6 PMOD: eight {voltage} GPIO, two GND, two {voltage}")
+    components[-1].assembly = "THT"
+
+
+add_pmod("JPMOD1", "PMOD1", "VCC3V3", "3.3 V")
+add_pmod("JPMOD2", "PMOD2", "VCC3V3", "3.3 V")
+add_pmod("JPMOD3", "PMOD3", "VCC1V8", "1.8 V")
+add_pmod("JPMOD4", "PMOD4", "VCC1V8", "1.8 V")
+
+for net, label in (("VBUS_RAW", "USB VBUS"), ("EXT5_RAW", "EXT 5V"), ("SYS5", "SYS 5V"),
+                   ("VCC3V3_AUX", "AUX 3V3"), ("VCC0V95", "CORE 0V95"),
+                   ("VCC1V8", "1V8"), ("VCC3V3", "3V3"), ("VCC3V0_RF", "RF 3V0"),
+                   ("VCC3V0_DIG", "DIG 3V0"), ("FPGA_CRESET_N", "CRESET_N"),
+                   ("FPGA_CDONE", "CDONE"), ("GND", "GND")):
+    tp(net, label)
+
+# Configuration/JTAG pulls are located on the FPGA side of the isolation
+# buffers and use the voltage of their respective I/O bank.
+r("10K", "VCC1V8", "FPGA_CDONE", description="Efinix-required CDONE open-drain pull-up")
+for net in ("HARD_TCK", "HARD_TDI", "HARD_TDO"):
+    r("10K", "VCC3V3", net, description="Efinix-required hard-JTAG weak pull-up")
+for net in ("RISCV_TCK", "RISCV_TMS", "RISCV_TDI", "RISCV_TDO"):
+    r("10K", "VCC3V3", net, description="RISC-V JTAG idle-state pull-up")
+
+# Supervisor support and reset-request fan-in.  FTDI BDBUS4 uses the
+# Efinix-compatible active-low convention.  Independent open-drain paths avoid
+# output contention and allow JTAG to remain live while CRESET_N is asserted.
+r("10K", "VCC3V3_AUX", "FTDI_B_RESET_N_SRC", description="FTDI FPGA-reset request default release")
+r("10K", "VCC3V3_AUX", "FPGA_POWER_OK_N", description="TPS3808 open-drain power-good pull-up")
+r("10K", "VCC3V3", "FTDI_FPGA_BUF_OE_N", description="Keep FTDI-to-FPGA buffers disabled until power-good")
+r("10K", "ALL_FPGA_POWER_OK", "FTDI_BUF_OE_BASE", description="All-rail-good inverter base-current limiter")
+r("100K", "FTDI_BUF_OE_BASE", "GND", description="Power-good inverter default-off base pull-down")
+r("10K", "VCC1V8", "EXT_RESET_FILTER_N", description="External/manual reset input pull-up")
+r("1K", "EXT_RESET_N", "EXT_RESET_FILTER_N", description="External-reset input current and ESD limiting")
+r("10K", "VCC3V3_AUX", "PWR_SEQ_OK", description="LM3880 final-flag pull-up for all-power logic")
+r("10K", "VCC3V3_AUX", "PWR_1V8_OK", description="1.8-V power-good pull-up for all-power logic")
+r("10K", "VCC3V3_AUX", "PWR_3V3_OK", description="3.3-V power-good pull-up for all-power logic")
+c("4.7nF", "VCC3V0_DIG", "GND", description="TPS3808 SENSE transient filter")
+c("4.7nF", "EXT_RESET_FILTER_N", "GND", description="Manual/external reset cable-noise filter")
+c("100nF", "VCC3V3_AUX", "GND", description="TPS3808 local bypass")
+c("100nF", "VCC3V3", "GND", description="SN74LVC244A local bypass")
+c("100nF", "VCC3V3", "GND", description="SN74LVC1G125 local bypass")
+c("100nF", "VCC3V3_AUX", "GND", description="SN74LVC1G07 local bypass")
+c("100nF", "VCC3V3_AUX", "GND", description="Power-good open-drain buffer local bypass")
+c("100nF", "VCC1V8", "GND", description="External-reset open-drain buffer local bypass")
+c("100nF", "VCC3V3_AUX", "GND", description="All-rail-valid logic local bypass")
+
+add_ic("J4", "EXT RESET_N", "SM02B-SRSS-TB(LF)(SN)", "JST",
+       "Connector_JST:JST_SH_SM02B-SRSS-TB_1x02-1MP_P1.00mm_Horizontal", [
+           p(1, "EXT_RESET_N", "EXT_RESET_N", "input"), p(2, "GND", "GND", "power_in")],
+       "External active-low open-drain reset input; JST-SH 1.0-mm")
+add_ic("SW1", "FPGA RESET", "B3U-1000P", "Omron",
+       "Button_Switch_SMD:SW_SPST_B3U-1000P", [
+           p(1, "RESET", "EXT_RESET_FILTER_N", "passive"), p(2, "GND", "GND", "passive")],
+       "User-accessible momentary FPGA configuration reset")
+add_ic("D2", "RESET ESD", "ESD5Z3.3T1G", "onsemi", "Diode_SMD:D_SOD-523", [
+           p(1, "K", "EXT_RESET_N", "passive"), p(2, "A", "GND", "passive")],
+       "External-reset connector ESD clamp")
+
+
+def validate() -> None:
+    refs = [x.ref for x in components]
+    assert len(refs) == len(set(refs))
+    u1 = next(x for x in components if x.ref == "U1")
+    assert len(u1.pins) == 529 and len({x.number for x in u1.pins}) == 529
+    assert next(x for x in u1.pins if x.number == "G10").net == "HARD_TCK"
+    assert {pin.number: pin.net for pin in u1.pins if pin.number in {
+        "G10", "G12", "G9", "G13", "F12", "V19", "P18", "T18"
+    }} == {
+        "G10": "HARD_TCK", "G12": "HARD_TMS", "G9": "HARD_TDI", "G13": "HARD_TDO",
+        "F12": "RISCV_TCK", "V19": "RISCV_TDI", "P18": "RISCV_TMS", "T18": "RISCV_TDO",
+    }
+    assert next(x for x in u1.pins if x.number == "B11").net == "MAX_CLKOUT"
+    maxic = next(x for x in components if x.ref == "U21")
+    assert next(x for x in maxic.pins if x.number == "25").net == "MAX_MIXIN_HI"
+    assert all(next(x for x in maxic.pins if x.number == n).net is None
+               for n in ("19", "20", "23", "24", "26"))
+    pmods = [next(x for x in components if x.ref == f"JPMOD{i}") for i in range(1, 5)]
+    assert all(len(x.pins) == 12 for x in pmods)
+    assert all(sum(pin.net == "GND" for pin in x.pins) == 2 for x in pmods)
+    assert all(sum((pin.net or "").startswith("PMOD") for pin in x.pins) == 8 for x in pmods)
+    assert all(sum(pin.net == "VCC3V3" for pin in x.pins) == 2 for x in pmods[:2])
+    assert all(sum(pin.net == "VCC1V8" for pin in x.pins) == 2 for x in pmods[2:])
+    assert not any((pin.net or "").startswith("EXP_") for pin in u1.pins)
+    u2 = next(x for x in components if x.ref == "U2")
+    assert {pin.number: pin.net for pin in u2.pins if pin.number in {
+        "12", "13", "14", "15", "22", "23", "24", "25"
+    }} == {
+        "12": "FTDI_A_TCK_SRC", "13": "FTDI_A_TDI_SRC",
+        "14": "FTDI_A_TDO_SRC", "15": "FTDI_A_TMS_SRC",
+        "22": "FTDI_B_TCK_SRC", "23": "FTDI_B_TDI_SRC",
+        "24": "FTDI_B_TDO_SRC", "25": "FTDI_B_TMS_SRC",
+    }
+    assert not any(c.ref in {"U4", "J6"} for c in components)
+    assert not any((pin.net or "").startswith("FTDI_HARD_") or pin.net == "JTAG_SW_OE_N"
+                   for c in components for pin in c.pins)
+
+    def has_link(net_a: str, net_b: str, value: str = "33R") -> bool:
+        return any(c.value == value and len(c.pins) == 2 and
+                   {c.pins[0].net, c.pins[1].net} == {net_a, net_b}
+                   for c in components)
+
+    for src, dst in (
+        ("BUF_A_TCK", "RISCV_TCK"), ("BUF_A_TMS", "RISCV_TMS"),
+        ("BUF_A_TDI", "RISCV_TDI"), ("FTDI_A_TDO_SRC", "RISCV_TDO"),
+        ("BUF_B_TCK", "HARD_TCK"), ("BUF_B_TMS", "HARD_TMS"),
+        ("BUF_B_TDI", "HARD_TDI"), ("FTDI_B_TDO_SRC", "HARD_TDO"),
+    ):
+        assert has_link(src, dst), (src, dst)
+    assert next(pin for pin in u2.pins if pin.number == "26").net == "FTDI_B_RESET_N_SRC"
+    u28 = next(x for x in components if x.ref == "U28")
+    assert {pin.name: pin.net for pin in u28.pins} == {
+        "RESET_N": "FPGA_POWER_OK_N", "GND": "GND", "MR_N": "VCC3V3_AUX",
+        "CT": None, "SENSE": "VCC3V0_DIG", "VDD": "VCC3V3_AUX"}
+    u34 = next(x for x in components if x.ref == "U34")
+    assert {pin.number: pin.net for pin in u34.pins if pin.number in {"1", "2", "4", "5", "12", "13"}} == {
+        "1": "CORE_PG", "2": "PWR_1V8_OK", "4": "PWR_3V3_OK",
+        "5": "FPGA_POWER_OK_N", "12": "PWR_OK_C", "13": "PWR_SEQ_OK"}
+    assert next(pin for pin in next(x for x in components if x.ref == "U32").pins
+                if pin.number == "2").net == "ALL_FPGA_POWER_OK"
+    assert not any(c.value == "0R" and "FPGA_CRESET_N" in {pin.net for pin in c.pins}
+                   for c in components)
+    for net, rail in (("FPGA_CDONE", "VCC1V8"), ("HARD_TCK", "VCC3V3"),
+                      ("HARD_TMS", "VCC3V3"), ("HARD_TDI", "VCC3V3"),
+                      ("HARD_TDO", "VCC3V3")):
+        assert has_link(net, rail, "10K"), (net, rail)
+    assert {pin.net for pin in next(x for x in components if x.ref == "J4").pins} == {
+        "EXT_RESET_N", "GND"}
+    assert [x.ref for x in components if x.ref.startswith("TP")] == [f"TP{i}" for i in range(1, 16)]
+    j5 = next(x for x in components if x.ref == "J5")
+    assert {x.net for x in j5.pins} == {"VCC3V3_ANT", "ANT_BIAS_SEL", "SYS5"}
+
+
+validate()
@@ -0,0 +1,52 @@
+#!/usr/bin/env python3
+"""Export a routing-stage DSN containing only selected net classes."""
+
+from __future__ import annotations
+
+import argparse
+from pathlib import Path
+
+import pcbnew
+
+
+def main() -> None:
+    parser = argparse.ArgumentParser()
+    parser.add_argument("board", type=Path)
+    parser.add_argument("dsn", type=Path)
+    parser.add_argument("--classes", required=True,
+                        help="Exact KiCad net-class names separated by ';' (or ',' for legacy single names)")
+    parser.add_argument("--preview", type=Path,
+                        help="Optional filtered KiCad board for inspection")
+    args = parser.parse_args()
+
+    # KiCad can report a compound effective class such as "CLOCK,POWER" when
+    # two pattern assignments match one net.  Semicolons let that exact class
+    # name pass through without being split.
+    separator = ";" if ";" in args.classes else ","
+    keep = {name.strip() for name in args.classes.split(separator) if name.strip()}
+    board = pcbnew.LoadBoard(str(args.board))
+    kept_pads = 0
+    omitted_pads = 0
+    kept_nets: set[str] = set()
+    for fp in board.GetFootprints():
+        for pad in fp.Pads():
+            if not pad.GetNetname():
+                continue
+            if pad.GetNetClassName() in keep:
+                kept_pads += 1
+                kept_nets.add(pad.GetNetname())
+            else:
+                pad.SetNetCode(0)
+                omitted_pads += 1
+    board.BuildListOfNets()
+    if args.preview:
+        pcbnew.SaveBoard(str(args.preview), board)
+    if not pcbnew.ExportSpecctraDSN(board, str(args.dsn)):
+        raise RuntimeError(f"Failed to export {args.dsn}")
+    print(f"Classes: {', '.join(sorted(keep))}")
+    print(f"Kept {kept_pads} pads on {len(kept_nets)} nets; omitted {omitted_pads} pads")
+    print(f"Saved {args.dsn}")
+
+
+if __name__ == "__main__":
+    main()
@@ -0,0 +1,129 @@
+#!/usr/bin/env python3
+"""Export the authoritative Ti375 C529 package map from Efinity.
+
+Run with Efinity's bundled Python because the resource pickle contains Efinity
+classes.  No pin name or ball assignment is embedded in this script.
+"""
+
+from __future__ import annotations
+
+import argparse
+import csv
+import gzip
+import hashlib
+import json
+import pickle
+import re
+from pathlib import Path
+
+
+HSIO_BANKS = {"2A", "2B", "2C", "2D", "2E", "4A_4B", "4C", "4D"}
+HVIO_BANKS = {"BL2_BL3", "BR0", "BR3_BR4", "TL1_TL5", "TR0", "TR1", "TR2"}
+
+
+def natural_ball(ball: str) -> tuple[str, int]:
+    match = re.fullmatch(r"([A-Z]+)([0-9]+)", ball)
+    if not match:
+        return ball, 0
+    return match.group(1), int(match.group(2))
+
+
+def main() -> None:
+    parser = argparse.ArgumentParser()
+    parser.add_argument(
+        "--db",
+        type=Path,
+        default=Path("/tools/efinix/efinity/2025.2/pt/db/resource/Ti375C529.db"),
+    )
+    parser.add_argument("--csv", type=Path, default=Path("docs/ti375_c529_package.csv"))
+    parser.add_argument("--meta", type=Path, default=Path("docs/ti375_c529_package.meta.json"))
+    args = parser.parse_args()
+
+    with gzip.open(args.db, "rb") as stream:
+        device = pickle.load(stream)
+
+    package = device.get_package()
+    io_db = device._PeripheryDevice__io_pad
+    io_by_pad = {
+        vars(item)["_IOPadInfo__pad_name"]: vars(item)
+        for item in io_db.get_all_io_pads()
+    }
+
+    rows: list[dict[str, str]] = []
+    for ball, mapping in sorted(package.get_package_pad_map().items(), key=lambda pair: natural_ball(pair[0])):
+        pad = mapping.get_pad_name()
+        info = io_by_pad.get(pad, {})
+        die_bank = info.get("_IOPadInfo__bank_name", "")
+        package_bank = info.get("_IOPadInfo__pkg_bank_name", "")
+        direction_obj = info.get("_IOPadInfo__direction")
+        direction = getattr(direction_obj, "name", "")
+        instances = info.get("_IOPadInfo__instances", [])
+
+        if package_bank in HSIO_BANKS:
+            bank_class = "HSIO"
+            allowed_vccio = "1.2;1.35;1.5;1.8"
+        elif package_bank in HVIO_BANKS:
+            bank_class = "HVIO"
+            allowed_vccio = "1.8;2.5;3.0;3.3"
+        else:
+            bank_class = "HARD/POWER"
+            allowed_vccio = ""
+
+        special: list[str] = []
+        upper_pad = pad.upper()
+        if "CLK" in upper_pad:
+            special.append("CLOCK_CAPABLE")
+        if "PLLIN" in upper_pad:
+            special.append("PLL_INPUT")
+        if "EXTFB" in upper_pad:
+            special.append("PLL_EXTFB")
+        if "CDI" in upper_pad:
+            special.append("CORE_DATA_INPUT")
+        if "EXTSPI" in upper_pad:
+            special.append("EXT_SPI")
+        if "CBSEL" in upper_pad:
+            special.append("CONFIG_BOOT_SELECT")
+        if re.search(r"_(P|N)(?:_|$)", upper_pad):
+            special.append("DIFFERENTIAL_MEMBER")
+
+        is_fabric_gpio = pad.startswith(("GPIOB_", "GPIOT_", "GPIOL_", "GPIOR_"))
+        rows.append(
+            {
+                "ball": ball,
+                "official_pad_name": pad,
+                "die_bank": die_bank,
+                "package_bank": package_bank,
+                "bank_class": bank_class,
+                "allowed_vccio_v": allowed_vccio,
+                "direction": direction,
+                "function": info.get("_IOPadInfo__function", ""),
+                "periphery_instances": ";".join(instances),
+                "instance_pin": info.get("_IOPadInfo__pin", "") or "",
+                "special_capability": ";".join(special),
+                "fabric_gpio": "yes" if is_fabric_gpio else "no",
+            }
+        )
+
+    args.csv.parent.mkdir(parents=True, exist_ok=True)
+    with args.csv.open("w", newline="", encoding="utf-8") as stream:
+        writer = csv.DictWriter(stream, fieldnames=list(rows[0]))
+        writer.writeheader()
+        writer.writerows(rows)
+
+    digest = hashlib.sha256(args.db.read_bytes()).hexdigest()
+    metadata = {
+        "device": device.get_device_name(),
+        "mapped_device": device.get_device_mapped_name(),
+        "package": package.get_package_name(),
+        "package_status": package.get_status_str(),
+        "source_database": str(args.db),
+        "source_sha256": digest,
+        "row_count": len(rows),
+        "fabric_gpio_count": sum(row["fabric_gpio"] == "yes" for row in rows),
+        "package_banks": package.get_package_bank_names(),
+    }
+    args.meta.write_text(json.dumps(metadata, indent=2, sort_keys=True) + "\n", encoding="utf-8")
+
+
+if __name__ == "__main__":
+    main()
@@ -0,0 +1,246 @@
+#!/usr/bin/env python3
+"""Import a Specctra session and install audited RF/USB copper.
+
+Freerouting is used only for the dense non-critical interconnect.  The GPS
+front end and USB2 pair are removed from that result and rebuilt here with
+deterministic geometry derived from the selected JLC08161H-3313 stackup.
+"""
+
+from __future__ import annotations
+
+import argparse
+import math
+import shutil
+from pathlib import Path
+
+import pcbnew
+
+ROOT = Path(__file__).resolve().parents[1]
+PLACED = ROOT / "hardware" / "board.kicad_pcb"
+ROUTED = ROOT / "hardware" / "board_routed.kicad_pcb"
+
+RF_NETS = {"RF_SMA", "RF_PRE_SAW", "RF_POST_SAW", "MAX_MIXIN_HI"}
+USB_NETS = {"USB_D_P", "USB_D_N", "FTDI_D_P", "FTDI_D_N"}
+CRITICAL_NETS = RF_NETS | USB_NETS
+
+
+def mm(value: float) -> int:
+    return pcbnew.FromMM(value)
+
+
+def point(x: float, y: float) -> pcbnew.VECTOR2I:
+    return pcbnew.VECTOR2I_MM(x, y)
+
+
+def footprint(board: pcbnew.BOARD, ref: str) -> pcbnew.FOOTPRINT:
+    item = board.FindFootprintByReference(ref)
+    if item is None:
+        raise RuntimeError(f"Missing footprint {ref}")
+    return item
+
+
+def pads(board: pcbnew.BOARD, ref: str, number: str) -> list[pcbnew.PAD]:
+    result = [pad for pad in footprint(board, ref).Pads() if pad.GetNumber() == str(number)]
+    if not result:
+        raise RuntimeError(f"Missing pad {ref}.{number}")
+    return result
+
+
+def pad_xy(board: pcbnew.BOARD, ref: str, number: str, index: int = 0) -> tuple[float, float]:
+    position = pads(board, ref, number)[index].GetPosition()
+    return pcbnew.ToMM(position.x), pcbnew.ToMM(position.y)
+
+
+def assert_ref_nets(board: pcbnew.BOARD, ref: str, expected: set[str]) -> None:
+    actual = {pad.GetNetname() for pad in footprint(board, ref).Pads() if pad.GetNetname()}
+    if actual != expected:
+        raise RuntimeError(f"{ref} net mismatch: expected {sorted(expected)}, got {sorted(actual)}")
+
+
+def add_segment(board: pcbnew.BOARD, net_name: str,
+                start: tuple[float, float], end: tuple[float, float],
+                width: float, layer: int = pcbnew.F_Cu, locked: bool = True) -> None:
+    if start == end:
+        return
+    track = pcbnew.PCB_TRACK(board)
+    track.SetStart(point(*start))
+    track.SetEnd(point(*end))
+    track.SetWidth(mm(width))
+    track.SetLayer(layer)
+    track.SetNet(board.FindNet(net_name))
+    track.SetLocked(locked)
+    board.Add(track)
+
+
+def add_polyline(board: pcbnew.BOARD, net_name: str,
+                 vertices: list[tuple[float, float]], width: float,
+                 layer: int = pcbnew.F_Cu) -> None:
+    for start, end in zip(vertices, vertices[1:]):
+        add_segment(board, net_name, start, end, width, layer)
+
+
+def add_via(board: pcbnew.BOARD, net_name: str, position: tuple[float, float],
+            diameter: float = 0.45, drill: float = 0.225) -> None:
+    via = pcbnew.PCB_VIA(board)
+    via.SetPosition(point(*position))
+    via.SetWidth(mm(diameter))
+    via.SetDrill(mm(drill))
+    via.SetLayerPair(pcbnew.F_Cu, pcbnew.B_Cu)
+    via.SetNet(board.FindNet(net_name))
+    via.SetLocked(True)
+    board.Add(via)
+
+
+def remove_critical_routes(board: pcbnew.BOARD) -> int:
+    doomed = [item for item in board.GetTracks() if item.GetNetname() in CRITICAL_NETS]
+    for item in doomed:
+        board.Remove(item)
+    return len(doomed)
+
+
+def remove_temporary_keepouts(board: pcbnew.BOARD) -> int:
+    doomed = [zone for zone in board.Zones()
+              if zone.GetIsRuleArea() and zone.GetZoneName().startswith("TEMP_")]
+    for zone in doomed:
+        board.Remove(zone)
+    return len(doomed)
+
+
+def route_rf(board: pcbnew.BOARD) -> None:
+    # 0.164-mm L1 CPWG with 0.200-mm ground gap: 49.65 ohms on the exact
+    # JLC08161H-3313 L1/L2 dielectric construction.
+    for ref, expected in {
+        "C83": {"RF_SMA", "RF_PRE_SAW"},
+        "C84": {"RF_POST_SAW", "GND"},
+        "R39": {"RF_POST_SAW", "MAX_MIXIN_HI"},
+        "C85": {"MAX_MIXIN_HI", "GND"},
+    }.items():
+        assert_ref_nets(board, ref, expected)
+
+    w = 0.164
+    j2 = pad_xy(board, "J2", "1")
+    dc_block_1 = pad_xy(board, "C83", "1")
+    l4_2 = pad_xy(board, "L4", "2")
+    add_polyline(board, "RF_SMA", [j2, l4_2, dc_block_1], w)
+    d1 = pad_xy(board, "D1", "1")
+    add_polyline(board, "RF_SMA", [d1, (d1[0], 45.07)], w)
+
+    add_polyline(board, "RF_PRE_SAW",
+                 [pad_xy(board, "C83", "2"), pad_xy(board, "FL1", "1")], w)
+
+    fl_out = pad_xy(board, "FL1", "4")
+    tune1 = pad_xy(board, "C84", "1")
+    series_1 = pad_xy(board, "R39", "1")
+    add_polyline(board, "RF_POST_SAW", [fl_out, tune1, series_1], w)
+
+    series_2 = pad_xy(board, "R39", "2")
+    mixin = pad_xy(board, "U21", "25")
+    add_polyline(board, "MAX_MIXIN_HI",
+                 [series_2, (159.69, 41.80), (mixin[0], 41.80), mixin], w)
+    tune2 = pad_xy(board, "C85", "1")
+    add_polyline(board, "MAX_MIXIN_HI", [tune2, (tune2[0], 41.80)], w)
+
+
+def route_usb(board: pcbnew.BOARD) -> None:
+    # Main device-side pair uses the upper receptacle contact pair.  The two
+    # mirrored USB-C contacts join through a sub-1.5-mm L3 crossover so neither
+    # polarity creates a same-layer crossing at the receptacle.
+    w = 0.135
+    dm_main = pad_xy(board, "J1", "B7")
+    dp_main = pad_xy(board, "J1", "A6")
+    dm_mirror = pad_xy(board, "J1", "A7")
+    dp_mirror = pad_xy(board, "J1", "B6")
+    dm_join, dp_join = (28.30, 47.25), (28.80, 47.75)
+    dm_aux, dp_aux = (27.30, 48.25), (27.80, 48.75)
+
+    add_polyline(board, "USB_D_N", [dm_main, dm_join], w)
+    add_polyline(board, "USB_D_P", [dp_main, dp_join], w)
+    add_polyline(board, "USB_D_N", [dm_mirror, dm_aux], w)
+    add_polyline(board, "USB_D_P", [dp_mirror, dp_aux], w)
+    for net, location in (("USB_D_N", dm_join), ("USB_D_P", dp_join),
+                          ("USB_D_N", dm_aux), ("USB_D_P", dp_aux)):
+        add_via(board, net, location)
+    add_polyline(board, "USB_D_N", [dm_aux, dm_join], w, pcbnew.In2_Cu)
+    add_polyline(board, "USB_D_P", [dp_aux, dp_join], w, pcbnew.In2_Cu)
+
+    dm_esd = pad_xy(board, "U6", "3")
+    dp_esd = pad_xy(board, "U6", "1")
+    add_polyline(board, "USB_D_N", [dm_join, (30.00, 49.00), (30.00, 50.70), dm_esd], w)
+    add_polyline(board, "USB_D_P", [dp_join, (30.285, 49.285), (30.285, 51.64), dp_esd], w)
+
+    dm_r = pad_xy(board, "R64", "1")
+    dp_r = pad_xy(board, "R63", "1")
+    add_polyline(board, "USB_D_N",
+                 [dm_esd, (31.00, 51.40), (34.00, 54.40), (35.80, 54.40), dm_r], w)
+    add_polyline(board, "USB_D_P",
+                 [dp_esd, (30.715, 51.685), (33.715, 54.685), (35.80, 54.685), dp_r], w)
+
+    # Equal 1.511-mm post-termination legs into the FT4232H USB PHY.
+    add_polyline(board, "FTDI_D_N", [pad_xy(board, "R64", "2"), pad_xy(board, "U2", "7")], w)
+    add_polyline(board, "FTDI_D_P", [pad_xy(board, "R63", "2"), pad_xy(board, "U2", "8")], w)
+
+
+def add_rf_ground(board: pcbnew.BOARD) -> None:
+    zone = pcbnew.ZONE(board)
+    zone.SetLayer(pcbnew.F_Cu)
+    zone.SetNet(board.FindNet("GND"))
+    zone.SetLocalClearance(mm(0.20))
+    zone.SetMinThickness(mm(0.10))
+    zone.SetPadConnection(pcbnew.ZONE_CONNECTION_FULL)
+    zone.SetIslandRemovalMode(pcbnew.ISLAND_REMOVAL_MODE_NEVER)
+    zone.SetAssignedPriority(100)
+    outline = zone.Outline()
+    outline.NewOutline()
+    for x, y in ((152.0, 36.0), (174.5, 36.0), (174.5, 49.5), (152.0, 49.5)):
+        outline.Append(point(x, y))
+    board.Add(zone)
+
+    # Lambda/20 is about 9.5 mm at GPS L1 in FR-4.  This 2-mm fence is much
+    # tighter and also gives every local shunt/EP a short plane connection.
+    fence = [(x, 38.7) for x in range(153, 174, 2)]
+    fence += [(x, 45.0) for x in range(161, 174, 2)]
+    for location in fence:
+        add_via(board, "GND", location, 0.45, 0.225)
+
+
+def routed_lengths(board: pcbnew.BOARD) -> dict[str, float]:
+    totals = {net: 0.0 for net in CRITICAL_NETS}
+    for item in board.GetTracks():
+        net = item.GetNetname()
+        if net not in totals or isinstance(item, pcbnew.PCB_VIA):
+            continue
+        start, end = item.GetStart(), item.GetEnd()
+        totals[net] += math.hypot(pcbnew.ToMM(end.x - start.x), pcbnew.ToMM(end.y - start.y))
+    return totals
+
+
+def main() -> None:
+    parser = argparse.ArgumentParser()
+    parser.add_argument("session", type=Path, help="Freerouting .ses file")
+    parser.add_argument("--output", type=Path, default=ROUTED)
+    args = parser.parse_args()
+
+    board = pcbnew.LoadBoard(str(PLACED))
+    if not pcbnew.ImportSpecctraSES(board, str(args.session)):
+        raise RuntimeError(f"Could not import {args.session}")
+    removed = remove_critical_routes(board)
+    removed_keepouts = remove_temporary_keepouts(board)
+    route_rf(board)
+    route_usb(board)
+    add_rf_ground(board)
+    if not pcbnew.ZONE_FILLER(board).Fill(board.Zones()):
+        raise RuntimeError("Final zone fill failed")
+    pcbnew.SaveBoard(str(args.output), board)
+    for suffix in (".kicad_pro", ".kicad_dru"):
+        source = PLACED.with_suffix(suffix)
+        if source.exists():
+            shutil.copyfile(source, args.output.with_suffix(suffix))
+    print(f"Removed {removed} autorouted critical-net items")
+    print(f"Removed {removed_keepouts} temporary critical-route keepouts")
+    print(f"Saved {args.output}")
+    for net, length in sorted(routed_lengths(board).items()):
+        print(f"{net:16s} {length:8.3f} mm")
+
+
+if __name__ == "__main__":
+    main()
@@ -0,0 +1,258 @@
+#!/usr/bin/env python3
+"""Generate the authoritative Ti375 pin tables and MAX2771 register image.
+
+The package source is exported directly from Efinity 2025.2's Ti375C529
+resource database by export_ti375_package.py.  This script deliberately fails
+if a named ball, bank, voltage, or clock capability does not match that source.
+"""
+
+from __future__ import annotations
+
+import csv
+from pathlib import Path
+
+
+ROOT = Path(__file__).resolve().parents[1]
+PACKAGE_CSV = ROOT / "docs" / "ti375_c529_package.csv"
+
+
+# signal, ball, direction, subsystem, selected I/O standard, design note
+ASSIGNMENTS = [
+    ("HARD_TCK", "G10", "input", "hard_jtag", "3.3 V LVCMOS", "Dedicated hard TAP TCK; FT4232H interface 1 BDBUS0 through power-domain isolation"),
+    ("HARD_TMS", "G12", "input", "hard_jtag", "3.3 V LVCMOS", "Dedicated hard TAP TMS; FT4232H interface 1 BDBUS3 through power-domain isolation"),
+    ("HARD_TDI", "G9", "input", "hard_jtag", "3.3 V LVCMOS", "Dedicated hard TAP TDI; FT4232H interface 1 BDBUS1 through power-domain isolation"),
+    ("HARD_TDO", "G13", "output", "hard_jtag", "3.3 V LVCMOS", "Dedicated hard TAP TDO; FT4232H interface 1 BDBUS2 through power-domain isolation"),
+    ("FPGA_CRESET_N", "F9", "input", "configuration", "1.8 V LVCMOS", "Open-drain fan-in of all-rail-valid, FTDI, and filtered external/manual reset requests"),
+    ("FPGA_CDONE", "F8", "output", "configuration", "1.8 V LVCMOS", "Configuration status test point"),
+    ("QSPI_CS_N", "A7", "output", "configuration", "1.8 V LVCMOS", "SPI-active SSL_N"),
+    ("QSPI_SCLK", "G6", "output", "configuration", "1.8 V LVCMOS", "SPI-active CCK; official CCK_PLLIN0 pin"),
+    ("QSPI_IO0", "H4", "bidirectional", "configuration", "1.8 V LVCMOS", "SPI-active CDI0"),
+    ("QSPI_IO1", "H5", "bidirectional", "configuration", "1.8 V LVCMOS", "SPI-active CDI1"),
+    ("QSPI_IO2", "G5", "bidirectional", "configuration", "1.8 V LVCMOS", "SPI-active CDI2"),
+    ("QSPI_IO3", "B7", "bidirectional", "configuration", "1.8 V LVCMOS", "SPI-active CDI3"),
+    ("FPGA_TEST_N", "J2", "input", "configuration", "1.8 V LVCMOS", "Mandatory external weak pull-up disables test mode during configuration"),
+    ("FPGA_CSI", "J5", "input", "configuration", "1.8 V LVCMOS", "Mandatory external weak pull-up selects this FPGA throughout configuration"),
+    ("RISCV_TCK", "F12", "input", "secondary_jtag", "3.3 V LVCMOS", "Fabric RISC-V JTAG clock moved off the plain-GPIO PMOD allocation"),
+    ("RISCV_TDI", "V19", "input", "secondary_jtag", "3.3 V LVCMOS", "Official development-kit hardened RISC-V JTAG assignment"),
+    ("RISCV_TMS", "P18", "input", "secondary_jtag", "3.3 V LVCMOS", "Clock-capable fabric pin; official development-kit assignment"),
+    ("RISCV_TDO", "T18", "output", "secondary_jtag", "3.3 V LVCMOS", "Official development-kit hardened RISC-V JTAG assignment"),
+    ("MAX_CLKOUT", "B11", "input", "max2771", "3.0 V LVCMOS", "Source-synchronous ADC capture clock on dedicated clock-capable input"),
+    ("MAX_I0", "D10", "input", "max2771", "3.0 V LVCMOS", "ADC I bit 0"),
+    ("MAX_I1", "D11", "input", "max2771", "3.0 V LVCMOS", "ADC I bit 1; clock-capable pad retained in same BR0 bank"),
+    ("MAX_Q0", "E10", "input", "max2771", "3.0 V LVCMOS", "ADC Q bit 0; PLL-capable pad in same BR0 bank"),
+    ("MAX_Q1", "E11", "input", "max2771", "3.0 V LVCMOS", "ADC Q bit 1; PLL-capable pad in same BR0 bank"),
+    ("MAX_LD", "F11", "input", "max2771", "3.0 V LVCMOS", "PLL lock status"),
+    ("MAX_SCLK", "F16", "output", "max2771", "3.0 V LVCMOS", "Three-wire serial clock"),
+    ("MAX_CSN", "F17", "output", "max2771", "3.0 V LVCMOS", "Three-wire active-low chip select"),
+    ("MAX_SDATA", "G16", "bidirectional", "max2771", "3.0 V LVCMOS", "Single bidirectional three-wire serial data; not split MOSI/MISO"),
+    ("MAX_SHDN", "G17", "output", "max2771", "3.0 V LVCMOS", "MAX2771 hardware shutdown control"),
+    ("IMU_SCK", "A8", "output", "sch16t", "3.3 V LVCMOS", "SafeSPI mode-0 clock"),
+    ("IMU_MOSI", "A9", "output", "sch16t", "3.3 V LVCMOS", "SafeSPI controller-to-sensor data"),
+    ("IMU_MISO", "B9", "input", "sch16t", "3.3 V LVCMOS", "SafeSPI sensor-to-controller data"),
+    ("IMU_CS", "B10", "output", "sch16t", "3.3 V LVCMOS", "SafeSPI active-low chip select"),
+    ("IMU_DRY_SYNC", "A11", "bidirectional", "sch16t", "3.3 V LVCMOS", "Murata multiplexed Data Ready output / SYNC input"),
+    ("IMU_EXTRESN", "C10", "output", "sch16t", "3.3 V LVCMOS", "External active-low reset"),
+    ("CLK_40M_FPGA", "U17", "input", "clock", "3.3 V LVCMOS", "40 MHz oscillator branch on clock-capable pin"),
+    ("UART0_RX", "P17", "input", "ft4232", "3.3 V LVCMOS", "FT4232H channel C TXD to FPGA RX"),
+    ("UART0_TX", "R17", "output", "ft4232", "3.3 V LVCMOS", "FPGA TX to FT4232H channel C RXD"),
+    ("UART1_RX", "R18", "input", "ft4232", "3.3 V LVCMOS", "FT4232H channel D TXD to FPGA RX"),
+    ("UART1_TX", "T19", "output", "ft4232", "3.3 V LVCMOS", "FPGA TX to FT4232H channel D RXD"),
+    ("FTDI_DBG_GPIO", "U19", "bidirectional", "ft4232", "3.3 V LVCMOS", "Channel D debug GPIO/test point; PLL-capable"),
+    ("PMOD1_1", "U6", "bidirectional", "pmod_3v3", "3.3 V LVCMOS", "PMOD 1 pin 1; plain HVIO GPIO"),
+    ("PMOD1_2", "V4", "bidirectional", "pmod_3v3", "3.3 V LVCMOS", "PMOD 1 pin 2; plain HVIO GPIO"),
+    ("PMOD1_3", "A13", "bidirectional", "pmod_tr1", "3.3 V LVCMOS", "PMOD 1 pin 3"),
+    ("PMOD1_4", "C9", "bidirectional", "pmod_3v3", "3.3 V LVCMOS", "PMOD 1 pin 4; plain HVIO GPIO"),
+    ("PMOD1_7", "C12", "bidirectional", "pmod_tr1", "3.3 V LVCMOS", "PMOD 1 pin 7"),
+    ("PMOD1_8", "C13", "bidirectional", "pmod_tr1", "3.3 V LVCMOS", "PMOD 1 pin 8"),
+    ("PMOD1_9", "C14", "bidirectional", "pmod_tr1", "3.3 V LVCMOS", "PMOD 1 pin 9"),
+    ("PMOD1_10", "D12", "bidirectional", "pmod_tr1", "3.3 V LVCMOS", "PMOD 1 pin 10"),
+    ("PMOD2_1", "V20", "bidirectional", "pmod_3v3", "3.3 V LVCMOS", "PMOD 2 pin 1; plain HVIO GPIO"),
+    ("PMOD2_2", "D13", "bidirectional", "pmod_tr2", "3.3 V LVCMOS", "PMOD 2 pin 2"),
+    ("PMOD2_3", "E13", "bidirectional", "pmod_tr2", "3.3 V LVCMOS", "PMOD 2 pin 3"),
+    ("PMOD2_4", "E14", "bidirectional", "pmod_tr2", "3.3 V LVCMOS", "PMOD 2 pin 4"),
+    ("PMOD2_7", "E16", "bidirectional", "pmod_tr2", "3.3 V LVCMOS", "PMOD 2 pin 7"),
+    ("PMOD2_8", "F13", "bidirectional", "pmod_tr2", "3.3 V LVCMOS", "PMOD 2 pin 8"),
+    ("PMOD2_9", "E15", "bidirectional", "pmod_tr2", "3.3 V LVCMOS", "PMOD 2 pin 9"),
+    ("PMOD2_10", "F14", "bidirectional", "pmod_tr2", "3.3 V LVCMOS", "PMOD 2 pin 10"),
+    # The two 1.8-V PMODs use plain HSIO pairs only.  None of these pads has
+    # a configuration, clock, PLL, or external-feedback alternate function.
+    ("PMOD3_1", "C20", "bidirectional", "pmod_2e", "1.8 V LVCMOS", "PMOD 3 pin 1; HSIO pair 51 P"),
+    ("PMOD3_2", "B20", "bidirectional", "pmod_2e", "1.8 V LVCMOS", "PMOD 3 pin 2; HSIO pair 51 N"),
+    ("PMOD3_3", "C17", "bidirectional", "pmod_2e", "1.8 V LVCMOS", "PMOD 3 pin 3; HSIO pair 52 P"),
+    ("PMOD3_4", "B17", "bidirectional", "pmod_2e", "1.8 V LVCMOS", "PMOD 3 pin 4; HSIO pair 52 N"),
+    ("PMOD3_7", "A16", "bidirectional", "pmod_2e", "1.8 V LVCMOS", "PMOD 3 pin 7; HSIO pair 53 P"),
+    ("PMOD3_8", "A17", "bidirectional", "pmod_2e", "1.8 V LVCMOS", "PMOD 3 pin 8; HSIO pair 53 N"),
+    ("PMOD3_9", "C19", "bidirectional", "pmod_2e", "1.8 V LVCMOS", "PMOD 3 pin 9; HSIO pair 54 P"),
+    ("PMOD3_10", "B19", "bidirectional", "pmod_2e", "1.8 V LVCMOS", "PMOD 3 pin 10; HSIO pair 54 N"),
+    ("PMOD4_1", "B14", "bidirectional", "pmod_2e", "1.8 V LVCMOS", "PMOD 4 pin 1; HSIO pair 55 P"),
+    ("PMOD4_2", "A14", "bidirectional", "pmod_2e", "1.8 V LVCMOS", "PMOD 4 pin 2; HSIO pair 55 N"),
+    ("PMOD4_3", "J18", "bidirectional", "pmod_2e", "1.8 V LVCMOS", "PMOD 4 pin 3; HSIO pair 56 P"),
+    ("PMOD4_4", "H18", "bidirectional", "pmod_2e", "1.8 V LVCMOS", "PMOD 4 pin 4; HSIO pair 56 N"),
+    ("PMOD4_7", "A18", "bidirectional", "pmod_2e", "1.8 V LVCMOS", "PMOD 4 pin 7; HSIO pair 57 P"),
+    ("PMOD4_8", "A19", "bidirectional", "pmod_2e", "1.8 V LVCMOS", "PMOD 4 pin 8; HSIO pair 57 N"),
+    ("PMOD4_9", "D16", "bidirectional", "pmod_2e", "1.8 V LVCMOS", "PMOD 4 pin 9; HSIO pair 58 P"),
+    ("PMOD4_10", "D17", "bidirectional", "pmod_2e", "1.8 V LVCMOS", "PMOD 4 pin 10; HSIO pair 58 N"),
+]
+
+
+EXPECTED_HARD_NAMES = {
+    "G10": "TCK", "G12": "TMS", "G9": "TDI", "G13": "TDO",
+    "F9": "CRESET_N", "F8": "CDONE", "C8": "JTAG_VCCIO_SEL",
+}
+
+
+def load_package() -> tuple[list[dict[str, str]], dict[str, dict[str, str]]]:
+    with PACKAGE_CSV.open(newline="") as f:
+        rows = list(csv.DictReader(f))
+    assert len(rows) == 529, f"C529 package source has {len(rows)} rows, expected 529"
+    by_ball = {r["ball"]: r for r in rows}
+    assert len(by_ball) == 529
+    for ball, name in EXPECTED_HARD_NAMES.items():
+        assert by_ball[ball]["official_pad_name"] == name, (ball, by_ball[ball], name)
+    return rows, by_ball
+
+
+def output_pin_tables(rows: list[dict[str, str]], by_ball: dict[str, dict[str, str]]) -> None:
+    assigned: dict[str, dict[str, str]] = {}
+    out_rows: list[dict[str, str]] = []
+    for signal, ball, direction, subsystem, standard, note in ASSIGNMENTS:
+        assert ball not in assigned, f"duplicate assignment at {ball}"
+        pkg = by_ball[ball]
+        if "clock" in note.lower() and "clock-capable" in note.lower():
+            assert "CLOCK_CAPABLE" in pkg["special_capability"], (signal, ball, pkg)
+        if standard.startswith("3.3"):
+            assert "3.3" in pkg["allowed_vccio_v"], (signal, ball, pkg)
+        if standard.startswith("3.0"):
+            assert "3.0" in pkg["allowed_vccio_v"], (signal, ball, pkg)
+        if standard.startswith("1.8"):
+            assert "1.8" in pkg["allowed_vccio_v"], (signal, ball, pkg)
+        item = {
+            "signal": signal,
+            "ball": ball,
+            "official_pin_name": pkg["official_pad_name"],
+            "die_bank": pkg["die_bank"],
+            "package_bank": pkg["package_bank"],
+            "vccio": standard.split()[0] + " V",
+            "io_standard": standard,
+            "direction": direction,
+            "clock_capability": "yes" if "CLOCK_CAPABLE" in pkg["special_capability"] else "no",
+            "special_function": pkg["special_capability"],
+            "subsystem": subsystem,
+            "connector": "on-board",
+            "connector_pin": "",
+            "note": note,
+        }
+        if subsystem.startswith("pmod_"):
+            pmod_number = signal.removeprefix("PMOD").split("_", 1)[0]
+            item["connector"] = f"JPMOD{pmod_number}"
+            item["connector_pin"] = signal.rsplit("_", 1)[1]
+        assigned[ball] = item
+        out_rows.append(item)
+
+    # Only the four PMODs are exposed.  All other fabric GPIOs remain physically
+    # unconnected, reducing connector count, board area, and escape-routing load.
+    inventory: list[dict[str, str]] = []
+    for pkg in rows:
+        if pkg["fabric_gpio"] != "yes":
+            continue
+        ball = pkg["ball"]
+        if ball in assigned:
+            a = assigned[ball]
+            inventory.append({
+                "ball": ball, "official_pin_name": pkg["official_pad_name"],
+                "package_bank": pkg["package_bank"], "bank_class": pkg["bank_class"],
+                "selected_vccio": a["vccio"], "io_standard": a["io_standard"],
+                "clock_capability": a["clock_capability"], "special_function": pkg["special_capability"],
+                "status": "used", "signal": a["signal"], "connector": a["connector"],
+                "connector_pin": a["connector_pin"], "note": a["note"],
+            })
+            continue
+        voltage = "3.3 V" if pkg["bank_class"] == "HVIO" else "1.8 V"
+        standard = "3.3 V LVCMOS" if pkg["bank_class"] == "HVIO" else "1.8 V LVCMOS"
+        inventory.append({
+            "ball": ball, "official_pin_name": pkg["official_pad_name"],
+            "package_bank": pkg["package_bank"], "bank_class": pkg["bank_class"],
+            "selected_vccio": voltage, "io_standard": standard,
+            "clock_capability": "yes" if "CLOCK_CAPABLE" in pkg["special_capability"] else "no",
+            "special_function": pkg["special_capability"],
+            "status": "unused", "signal": "", "connector": "",
+            "connector_pin": "", "note": "Unused fabric GPIO; left unconnected at the BGA",
+        })
+
+    all_gpio = {r["ball"] for r in rows if r["fabric_gpio"] == "yes"}
+    assert len(all_gpio) == 227
+    used_gpio = set(assigned) & all_gpio
+    # Two former stand-alone auxiliary probes were deliberately released when
+    # the connector-like test-point bank was removed.
+    assert len(used_gpio) == 66
+    assert len(all_gpio - used_gpio) == 161
+
+    fieldnames = list(out_rows[0])
+    with (ROOT / "docs" / "ti375_pinout.csv").open("w", newline="") as f:
+        w = csv.DictWriter(f, fieldnames=fieldnames)
+        w.writeheader()
+        w.writerows(sorted(out_rows, key=lambda r: r["ball"]))
+    with (ROOT / "docs" / "unused_gpio_inventory.csv").open("w", newline="") as f:
+        w = csv.DictWriter(f, fieldnames=list(inventory[0]))
+        w.writeheader()
+        w.writerows(sorted(inventory, key=lambda r: r["ball"]))
+
+    with (ROOT / "docs" / "ti375_pin_constraints.isf").open("w") as f:
+        f.write("# Efinity interface constraints generated from the official Ti375C529 database.\n")
+        f.write("# Verify port names against the final RTL top level before importing.\n")
+        for a in sorted(out_rows, key=lambda r: r["signal"]):
+            f.write(f'set_pin_assignment -pin_name {a["ball"]} -port_name {a["signal"]}\n')
+
+
+def output_max2771_registers() -> None:
+    defaults = {
+        0x0: 0xBEA41603, 0x1: 0x20550288, 0x2: 0x0EAFA1DC,
+        0x3: 0x698C0008, 0x4: 0x00C00080, 0x5: 0x08000070,
+        0x6: 0x08000000, 0x7: 0x010061B2, 0x8: 0x01E0F401,
+        0x9: 0x00C00002, 0xA: 0x010061B0,
+    }
+    regs = dict(defaults)
+    # GPS L1/L1C wideband example from MAX2771 Rev 2 Applications Information.
+    regs[0x0] = (regs[0x0] & ~(1 << 17)) | (1 << 17)  # MIXPOLE=36 MHz
+    regs[0x0] = (regs[0x0] & ~(0x3 << 15)) | (0x2 << 15)  # both LNAs disabled
+    regs[0x0] = (regs[0x0] & ~(0x3 << 13)) | (0x0 << 13)  # high-band mixer
+    regs[0x0] = (regs[0x0] & ~(0x7 << 3)) | (0x3 << 3)  # 23.4 MHz LPF
+    regs[0x0] &= ~(1 << 2)  # 5th order
+    regs[0x0] &= ~(1 << 1)  # low-pass, not polyphase
+    regs[0x3] |= 1 << 3  # integer-N PLL
+    regs[0x4] = (regs[0x4] & ~((0x7FFF << 13) | (0x3FF << 3))) | (1540 << 13) | (16 << 3)
+    regs[0x7] |= 1 << 28  # external ADC clock on ADC_CLKIN
+    regs[0xA] |= 1 << 2  # CLKOUT outputs ADC sampling clock
+    assert (regs[0] >> 22) & 0xFF == 0xFA  # required reserved field
+    assert (regs[9] >> 22) & 0x7 == 0x3  # required reserved field
+    assert regs[4] == 0x00C08080
+    assert abs(16.368 / 16 * 1540 - 1575.42) < 1e-9
+
+    with (ROOT / "docs" / "max2771_registers.csv").open("w", newline="") as f:
+        fieldnames = ["address", "value_hex", "default_hex", "changed", "purpose"]
+        w = csv.DictWriter(f, fieldnames=fieldnames)
+        w.writeheader()
+        purposes = {
+            0: "MIXIN_HI, both LNAs disabled, 23.4 MHz 5th-order LPF, 36 MHz mixer pole",
+            3: "Integer-N L1 PLL",
+            4: "NDIV=1540, RDIV=16: 16.368 MHz / 16 * 1540 = 1575.42 MHz",
+            7: "External 40 MHz ADC sampling clock on ADC_CLKIN",
+            10: "Route ADC sampling clock to CLKOUT for source-synchronous FPGA capture",
+        }
+        for addr in range(11):
+            w.writerow({
+                "address": f"0x{addr:X}", "value_hex": f"0x{regs[addr]:08X}",
+                "default_hex": f"0x{defaults[addr]:08X}",
+                "changed": "yes" if regs[addr] != defaults[addr] else "no",
+                "purpose": purposes.get(addr, "Preserve MAX2771 documented reset/default value"),
+            })
+
+
+def main() -> None:
+    rows, by_ball = load_package()
+    output_pin_tables(rows, by_ball)
+    output_max2771_registers()
+
+
+if __name__ == "__main__":
+    main()
@@ -0,0 +1,300 @@
+#!/usr/bin/env python3
+"""Generate manufacturer-recommended custom footprints used by board.kicad_sch.
+
+Dimensions are in millimetres and come from the package/land-pattern drawings
+listed in docs/reference_manifest.md.  No generic IPC generator is used for
+the irregular high-current and sensor packages.
+"""
+
+from __future__ import annotations
+
+from pathlib import Path
+
+
+ROOT = Path(__file__).resolve().parents[1]
+OUT = ROOT / "hardware" / "board.pretty"
+OUT.mkdir(parents=True, exist_ok=True)
+
+
+def fmt(value: float) -> str:
+    return f"{value:.4f}".rstrip("0").rstrip(".") or "0"
+
+
+def header(name: str, description: str, courtyard: tuple[float, float], body: tuple[float, float]) -> list[str]:
+    cw, ch = courtyard
+    bw, bh = body
+    return [
+        f'(footprint "{name}"',
+        '  (version 20240108)',
+        '  (generator "board-footprints")',
+        '  (layer "F.Cu")',
+        f'  (descr "{description}")',
+        '  (attr smd)',
+        '  (property "Reference" "REF**" (at 0 -5 0) (layer "F.SilkS")',
+        '    (effects (font (size 1 1) (thickness 0.15))))',
+        '  (property "Value" "" (at 0 5 0) (layer "F.Fab") hide',
+        '    (effects (font (size 1 1) (thickness 0.15))))',
+        f'  (fp_rect (start {fmt(-bw/2)} {fmt(-bh/2)}) (end {fmt(bw/2)} {fmt(bh/2)})',
+        '    (stroke (width 0.1) (type default)) (fill none) (layer "F.Fab"))',
+        f'  (fp_rect (start {fmt(-cw/2)} {fmt(-ch/2)}) (end {fmt(cw/2)} {fmt(ch/2)})',
+        '    (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))',
+    ]
+
+
+def silk_box(lines: list[str], width: float, height: float, mark: tuple[float, float] | None = None) -> None:
+    x, y = width / 2, height / 2
+    for x1, y1, x2, y2 in ((-x, -y, x, -y), (x, -y, x, y), (x, y, -x, y), (-x, y, -x, -y)):
+        lines.append(
+            f'  (fp_line (start {fmt(x1)} {fmt(y1)}) (end {fmt(x2)} {fmt(y2)}) '
+            '(stroke (width 0.15) (type default)) (layer "F.SilkS"))'
+        )
+    if mark:
+        lines.append(
+            f'  (fp_circle (center {fmt(mark[0])} {fmt(mark[1])}) (end {fmt(mark[0]+0.25)} {fmt(mark[1])}) '
+            '(stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))'
+        )
+
+
+def pad(lines: list[str], number: str, x: float, y: float, sx: float, sy: float,
+        shape: str = "roundrect", layers: str = '"F.Cu" "F.Paste" "F.Mask"',
+        rotation: float = 0.0) -> None:
+    rot = f" {fmt(rotation)}" if rotation else ""
+    lines.append(
+        f'  (pad "{number}" smd {shape} (at {fmt(x)} {fmt(y)}{rot}) '
+        f'(size {fmt(sx)} {fmt(sy)}) (layers {layers})'
+        + (' (roundrect_rratio 0.15)' if shape == "roundrect" else '') + ')'
+    )
+
+
+def finish(name: str, lines: list[str]) -> None:
+    lines.append('  (embedded_fonts no)')
+    lines.append(')')
+    (OUT / f"{name}.kicad_mod").write_text("\n".join(lines) + "\n")
+
+
+def texas_rpw0010a() -> None:
+    name = "Texas_RPW0010A_QFN10"
+    l = header(name, "TI RPW0010A VQFN-HR; TI land pattern 4225183/A", (3.0, 3.0), (2.0, 2.0))
+    silk_box(l, 2.35, 2.35, (-1.45, -1.15))
+    # Corner lands are the union of a 0.25 x 0.60 vertical land and a
+    # 0.60 x 0.30 horizontal land, exactly matching TI's L-shaped examples.
+    for number, sx, sy in (("1", -1, -1), ("4", -1, 1), ("7", 1, 1), ("10", 1, -1)):
+        pad(l, number, sx * 0.725, sy * 0.9, 0.25, 0.60)
+        pad(l, number, sx * 0.9, sy * 0.75, 0.60, 0.30)
+    pad(l, "2", -0.9, -0.225, 0.60, 0.25)
+    pad(l, "3", -0.9, 0.225, 0.60, 0.25)
+    pad(l, "5", -0.25, 0, 0.30, 2.40)
+    pad(l, "6", 0.25, 0, 0.30, 2.40)
+    pad(l, "8", 0.9, 0.225, 0.60, 0.25)
+    pad(l, "9", 0.9, -0.225, 0.60, 0.25)
+    finish(name, l)
+
+
+def texas_rux0012a() -> None:
+    name = "Texas_RUX0012A_VQFN12"
+    l = header(name, "TI RUX0012A VQFN-HR; TI land pattern 4224010/A", (3.4, 3.4), (2.5, 2.5))
+    silk_box(l, 2.65, 2.65, (-1.45, -1.2))
+    # Large current pads, left pins 1/2 and right pins 8/7.
+    for number, x, y in (("1", -0.675, -0.35), ("2", -0.675, 0.35),
+                         ("8", 0.675, -0.35), ("7", 0.675, 0.35)):
+        pad(l, number, x, y, 1.05, 0.40)
+    for number, x in zip(("12", "11", "10", "9"), (-0.75, -0.25, 0.25, 0.75)):
+        pad(l, number, x, -1.15, 0.20, 0.60)
+    for number, x in zip(("3", "4", "5", "6"), (-0.75, -0.25, 0.25, 0.75)):
+        pad(l, number, x, 1.15, 0.20, 0.60)
+    finish(name, l)
+
+
+def texas_rqy0009a() -> None:
+    name = "Texas_RQY0009A_VQFN9"
+    l = header(name, "TI RQY0009A VQFN-HR; TI land pattern 4225639/A", (2.8, 3.2), (1.5, 2.0))
+    silk_box(l, 1.75, 2.45, (-1.05, -1.25))
+    for number, x in zip(("1", "9", "8"), (-0.5, 0, 0.5)):
+        pad(l, number, x, -1.175, 0.25, 0.55)
+    for number, x in zip(("4", "5", "6"), (-0.5, 0, 0.5)):
+        pad(l, number, x, 1.175, 0.25, 0.55)
+    pad(l, "2", -0.475, -0.40, 0.95, 0.20)
+    pad(l, "3", -0.475, 0.40, 0.95, 0.20)
+    pad(l, "7", 0.475, 0, 0.95, 0.20)
+    finish(name, l)
+
+
+def texas_rzv0024a() -> None:
+    name = "Texas_RZV0024A_WQFN24"
+    l = header(name, "TI RZV0024A WQFN-FCRLF; TI land pattern 4228538/A", (3.5, 4.5), (3.05, 4.05))
+    silk_box(l, 3.15, 4.15, (-1.75, -2.1))
+    # Left pins 1..8 and right pins 20..13.  The four corner pins use TI's
+    # L-shaped lands; repeated pad numbers create one electrical pad in KiCad.
+    for number, sx, sy in (("1", -1, -1), ("8", -1, 1), ("13", 1, 1), ("20", 1, -1)):
+        # Trim only the two inward tips from the TI nominal 0.60-mm L shape.
+        # This keeps the outer solder fillet while meeting JLC's 0.10-mm
+        # copper web to the two adjacent lands.
+        pad(l, number, sx * 1.25, sy * 1.825, 0.25, 0.45)
+        pad(l, number, sx * 1.325, sy * 1.75, 0.45, 0.25)
+    for number, y in zip(("2", "3", "4", "5", "6", "7"), (-1.25, -0.75, -0.25, 0.25, 0.75, 1.25)):
+        pad(l, number, -1.25, y, 0.60, 0.25)
+    for number, y in zip(("19", "18", "17", "16", "15", "14"), (-1.25, -0.75, -0.25, 0.25, 0.75, 1.25)):
+        pad(l, number, 1.25, y, 0.60, 0.25)
+    for number, x in zip(("24", "23", "22", "21"), (-0.75, -0.25, 0.25, 0.75)):
+        pad(l, number, x, -1.75, 0.25, 0.60)
+    for number, x in zip(("9", "10", "11", "12"), (-0.75, -0.25, 0.25, 0.75)):
+        pad(l, number, x, 1.75, 0.25, 0.60)
+    # TI calls out three separate exposed-metal zones, all connected to GND.
+    # Leave a JLC-process-compatible 0.10-mm minimum copper gap to the
+    # perimeter lands while retaining the package's three-zone topology.
+    zones = ((-0.425, -0.65, 0.60, 1.10), (0.425, -0.65, 0.60, 1.10), (0, 0.65, 1.45, 1.10))
+    for x, y, sx, sy in zones:
+        pad(l, "25", x, y, sx, sy, "rect", '"F.Cu" "F.Mask"')
+        # 70-75% paste coverage, split so there are no large paste deposits.
+        nx = 2 if sx > 1.0 else 1
+        for ix in range(nx):
+            px = x + (ix - (nx - 1) / 2) * (sx / nx)
+            pad(l, "", px, y, sx / nx - 0.12, sy - 0.18, "roundrect", '"F.Paste"')
+    finish(name, l)
+
+
+def simple_two_pad(name: str, description: str, body: tuple[float, float],
+                   centres: float, size: tuple[float, float], courtyard: tuple[float, float]) -> None:
+    l = header(name, description, courtyard, body)
+    silk_box(l, body[0] + 0.15, body[1] + 0.15, (-body[0] / 2 - 0.2, -body[1] / 2))
+    pad(l, "1", -centres, 0, *size)
+    pad(l, "2", centres, 0, *size)
+    finish(name, l)
+
+
+def texas_dpy0002a() -> None:
+    simple_two_pad("Texas_DPY0002A_X1SON", "TI DPY0002A X1SON; ESD501 official land", (1.0, 0.6),
+                   0.35, (0.30, 0.50), (1.4, 1.0))
+
+
+def murata_dfe201612e() -> None:
+    simple_two_pad("Murata_DFE201612E", "Murata DFE201612E recommended land J(E)TE243A-0006", (2.0, 1.6),
+                   0.8, (0.80, 1.80), (2.8, 2.4))
+
+
+def coilcraft_xel4030() -> None:
+    simple_two_pad("Coilcraft_XEL4030", "Coilcraft XEL4030 recommended land, March 2026", (4.0, 4.0),
+                   1.675, (0.98, 3.40), (5.0, 4.8))
+
+
+def kyocera_600l() -> None:
+    simple_two_pad("Kyocera_600L_0402", "KYOCERA AVX 600L 0402 recommended land", (1.0, 0.5),
+                   0.65, (0.90, 0.70), (2.2, 1.2))
+
+
+def kyocera_sf14() -> None:
+    name = "Kyocera_SF14_5pad"
+    l = header(name, "KYOCERA SF14-1582M5UUS2 SAW; official five-pad land", (1.8, 1.5), (1.1, 0.9))
+    silk_box(l, 1.2, 1.0, (-0.8, 0))
+    for number, x, y in (("1", -0.5, 0), ("2", 0, 0.2875), ("3", 0.5, 0.2875),
+                         ("4", 0.5, -0.2875), ("5", 0, -0.2875)):
+        pad(l, number, x, y, 0.25, 0.325)
+    finish(name, l)
+
+
+def epson_tg2016smn() -> None:
+    name = "Epson_TG2016SMN"
+    l = header(name, "Epson TG2016SMN official 2.0 x 1.6 mm land", (3.0, 2.6), (2.0, 1.6))
+    silk_box(l, 2.15, 1.75, (-1.35, -0.85))
+    for number, x, y in (("1", -0.825, -0.565), ("2", -0.825, 0.565),
+                         ("3", 0.825, 0.565), ("4", 0.825, -0.565)):
+        pad(l, number, x, y, 0.60, 0.75)
+    finish(name, l)
+
+
+def murata_sch16t() -> None:
+    name = "Murata_SCH16T_K01"
+    l = header(name, "Murata SCH16T-K01-1 official PCB land pattern", (15.2, 12.8), (13.4, 11.8))
+    silk_box(l, 13.55, 11.95, (-7.15, -5.45))
+    ys = [-4.4 + 0.8 * i for i in range(12)]
+    for number, y in zip(range(1, 13), ys):
+        pad(l, str(number), -6.165, y, 1.87, 0.50)
+    for number, y in zip(range(24, 12, -1), ys):
+        pad(l, str(number), 6.165, y, 1.87, 0.50)
+    # Assembly-critical inertial orientation marking.
+    l += [
+        '  (fp_text user "X+ ->" (at 0 -2) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.14))))',
+        '  (fp_text user "Y+ ^" (at 0 0) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.14))))',
+    ]
+    finish(name, l)
+
+
+def ftdi_vqfn56() -> None:
+    name = "FTDI_VQFN56_EP5p9"
+    l = header(name, "FTDI FT4232H-56Q VQFN56 land from TN_166; 5.9-mm EP", (9.2, 9.2), (8.0, 8.0))
+    silk_box(l, 8.15, 8.15, (-4.4, -3.85))
+    coords = [-3.25 + 0.5 * i for i in range(14)]
+    for number, y in zip(range(1, 15), coords):
+        pad(l, str(number), -4.00, y, 0.80, 0.25)
+    for number, x in zip(range(15, 29), coords):
+        pad(l, str(number), x, 4.00, 0.25, 0.80)
+    for number, y in zip(range(29, 43), reversed(coords)):
+        pad(l, str(number), 4.00, y, 0.80, 0.25)
+    for number, x in zip(range(43, 57), reversed(coords)):
+        pad(l, str(number), x, -4.00, 0.25, 0.80)
+    pad(l, "57", 0, 0, 5.90, 5.90, "rect", '"F.Cu" "F.Mask"')
+    for x in (-2.22, -0.74, 0.74, 2.22):
+        for y in (-2.22, -0.74, 0.74, 2.22):
+            pad(l, "", x, y, 1.20, 1.20, "roundrect", '"F.Paste"')
+    finish(name, l)
+
+
+def amphenol_jtag() -> None:
+    name = "Amphenol_20021121_00010C4LF"
+    l = header(name, "Amphenol Minitek127 20021121-00010C4LF vertical SMT 2x5", (7.4, 6.0), (7.0, 4.6))
+    silk_box(l, 7.0, 4.7, (-3.8, 2.3))
+    xs = (-2.54, -1.27, 0, 1.27, 2.54)
+    for col, x in enumerate(xs):
+        pad(l, str(1 + col * 2), x, 1.95, 0.76, 2.40)
+        pad(l, str(2 + col * 2), x, -1.95, 0.76, 2.40)
+    finish(name, l)
+
+
+def digilent_pmod_2x6() -> None:
+    """2.54-mm dual-row PMOD with Digilent's row-wise pin numbering.
+
+    Generic KiCad 2xN headers use IDC odd/even numbering.  A PMOD instead has
+    pins 1..6 on one physical row and 7..12 on the other, so a dedicated
+    footprint prevents a silent GND/VCC and signal-position mismatch.
+    """
+    name = "Digilent_PMOD_2x6_P2.54mm"
+    l = [
+        f'(footprint "{name}"',
+        '  (version 20240108)',
+        '  (generator "board-footprints")',
+        '  (layer "F.Cu")',
+        '  (descr "Digilent PMOD 2x6, 2.54-mm pitch, row-wise pins 1-6 and 7-12")',
+        '  (attr through_hole)',
+        '  (property "Reference" "REF**" (at 6.35 -2.5 0) (layer "F.SilkS")',
+        '    (effects (font (size 1 1) (thickness 0.15))))',
+        '  (property "Value" "" (at 6.35 5 0) (layer "F.Fab") hide',
+        '    (effects (font (size 1 1) (thickness 0.15))))',
+        '  (fp_rect (start -1.27 -1.27) (end 13.97 3.81)',
+        '    (stroke (width 0.15) (type default)) (fill none) (layer "F.SilkS"))',
+        '  (fp_rect (start -1.5 -1.5) (end 14.2 4.04)',
+        '    (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd"))',
+        '  (fp_circle (center -0.8 -0.8) (end -0.5 -0.8)',
+        '    (stroke (width 0.15) (type default)) (fill solid) (layer "F.SilkS"))',
+    ]
+    for number in range(1, 13):
+        row = 0 if number <= 6 else 1
+        column = number - 1 if number <= 6 else number - 7
+        shape = "rect" if number == 1 else "circle"
+        l.append(
+            f'  (pad "{number}" thru_hole {shape} (at {fmt(column * 2.54)} {fmt(row * 2.54)}) '
+            '(size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask"))'
+        )
+    finish(name, l)
+
+
+def main() -> None:
+    for generator in (texas_rpw0010a, texas_rux0012a, texas_rzv0024a, texas_rqy0009a,
+                      murata_dfe201612e, texas_dpy0002a, kyocera_600l, kyocera_sf14,
+                      epson_tg2016smn, murata_sch16t, ftdi_vqfn56,
+                      coilcraft_xel4030, amphenol_jtag, digilent_pmod_2x6):
+        generator()
+    print(f"Generated {len(list(OUT.glob('*.kicad_mod')))} custom footprints in {OUT}")
+
+
+if __name__ == "__main__":
+    main()
@@ -0,0 +1,460 @@
+#!/usr/bin/env python3
+"""Generate the KiCad schematic hierarchy and BOM tables from design_data."""
+
+from __future__ import annotations
+
+import csv
+import copy
+import math
+import re
+import sys
+import uuid
+from collections import defaultdict
+from pathlib import Path
+
+ROOT = Path(__file__).resolve().parents[1]
+sys.path.insert(0, str(ROOT / "scripts"))
+from design_data import Component, Pin, components  # noqa: E402
+
+HW = ROOT / "hardware"
+DOCS = ROOT / "docs"
+OUT = ROOT / "outputs"
+HW.mkdir(exist_ok=True)
+DOCS.mkdir(exist_ok=True)
+OUT.mkdir(exist_ok=True)
+
+
+def q(text: str) -> str:
+    return text.replace("\\", "\\\\").replace('"', '\\"')
+
+
+def safe(text: str) -> str:
+    value = re.sub(r"[^A-Za-z0-9_]+", "_", text)
+    return value.strip("_") or "PIN"
+
+
+def category(comp: Component) -> str:
+    nets = {pin.net or "" for pin in comp.pins}
+    if comp.ref == "U1" or any(n.startswith("REF_RES") for n in nets):
+        return "fpga"
+    if comp.ref in {"J2", "J5", "D1", "FL1", "U21", "U23", "U24", "U27"} or any(
+            n.startswith(("RF_", "MAX_", "ANT_", "TCXO", "OSC40")) for n in nets):
+        return "rf_clock"
+    if comp.ref == "U22" or any(n.startswith("IMU_") for n in nets):
+        return "imu"
+    if comp.ref in {"U2", "U3", "U25"} or any(
+            n.startswith(("FTDI_", "HARD_", "RISCV_", "UART")) for n in nets):
+        return "usb_debug"
+    if comp.ref == "U26" or comp.ref.startswith(("JPMOD", "JH", "JHV")) or any(
+            n.startswith(("QSPI_", "EXP_", "PMOD")) for n in nets):
+        return "configuration_expansion"
+    return "power_usb"
+
+
+SHEETS = ["power_usb", "rf_clock", "imu", "usb_debug", "configuration_expansion", "fpga"]
+
+
+def chunks(comp: Component) -> list[list[Pin]]:
+    if comp.ref == "U1":
+        # Fourteen units keeps every unit below 40 balls and the complete 529-ball
+        # package readable without losing the common U1 reference.
+        size = math.ceil(len(comp.pins) / 14)
+        return [comp.pins[i:i + size] for i in range(0, len(comp.pins), size)]
+    return [comp.pins]
+
+
+def geometry(pins: list[Pin]) -> tuple[int, int, dict[str, tuple[int, int, str]]]:
+    left = pins[::2]
+    right = pins[1::2]
+    rows = max(len(left), len(right), 2)
+    half_h = max(150, (rows - 1) * 50 + 100)
+    endpoints: dict[str, tuple[int, int, str]] = {}
+    start_y = (len(left) - 1) * 50
+    for idx, pin in enumerate(left):
+        endpoints[pin.number] = (-700, start_y - idx * 100, "R")
+    start_y = (len(right) - 1) * 50
+    for idx, pin in enumerate(right):
+        endpoints[pin.number] = (700, start_y - idx * 100, "L")
+    return 500, half_h, endpoints
+
+
+def symbol_library() -> str:
+    lines = ["EESchema-LIBRARY Version 2.4", "#encoding utf-8"]
+    etypes = {
+        "input": "I", "output": "O", "bidirectional": "B", "power_in": "W",
+        "power_out": "w", "open_collector": "C", "passive": "P",
+    }
+    for comp in components:
+        name = f"BOARD_{safe(comp.ref)}"
+        units = chunks(comp)
+        lines += ["#", f"# {name}", "#",
+                  f"DEF {name} {comp.ref[0]} 0 30 Y Y {len(units)} L N",
+                  f'F0 "{q(comp.ref)}" 0 200 50 H V C CNN',
+                  f'F1 "{q(comp.value)}" 0 100 50 H V C CNN',
+                  f'F2 "{q(comp.footprint)}" 0 -100 50 H I C CNN',
+                  f'F3 "" 0 0 50 H I C CNN', "DRAW"]
+        for unit, pins in enumerate(units, 1):
+            half_w, half_h, endpoints = geometry(pins)
+            lines.append(f"S {-half_w} {half_h} {half_w} {-half_h} {unit} 1 10 f")
+            for pin in pins:
+                x, y, orient = endpoints[pin.number]
+                lines.append(
+                    f"X {safe(pin.name)} {pin.number} {x} {y} 200 {orient} 30 30 {unit} 1 "
+                    f"{etypes.get(pin.etype, 'P')}"
+                )
+        lines += ["ENDDRAW", "ENDDEF"]
+    lines += ["#", "#End Library"]
+    return "\n".join(lines) + "\n"
+
+
+def component_block(comp: Component, unit: int, x: int, y: int, stamp: int) -> list[str]:
+    name = f"BOARD_{safe(comp.ref)}"
+    f0y = y - 100
+    return [
+        "$Comp", f"L {name} {comp.ref}", f"U {unit} 1 {stamp:08X}", f"P {x} {y}",
+        f'F 0 "{q(comp.ref)}" H {x} {f0y} 50  0000 C CNN',
+        f'F 1 "{q(comp.value)}" H {x} {y + 100} 50  0000 C CNN',
+        f'F 2 "{q(comp.footprint)}" H {x} {y - 200} 50  0001 C CNN',
+        f'F 3 "" H {x} {y} 50  0001 C CNN',
+        f'F 4 "{q(comp.mpn)}" H {x} {y} 50  0001 C CNN "MPN"',
+        f'F 5 "{q(comp.manufacturer)}" H {x} {y} 50  0001 C CNN "Manufacturer"',
+        f"\t{unit}    {x} {y}", "\t1    0    0    -1", "$EndComp",
+    ]
+
+
+def add_pin_connections(lines: list[str], pins: list[Pin], x: int, y: int) -> None:
+    _, _, endpoints = geometry(pins)
+    for pin in pins:
+        px, py, side = endpoints[pin.number]
+        px += x
+        py += y
+        if pin.net is None:
+            lines.append(f"NoConn ~ {px} {py}")
+            continue
+        wire_end = px - 150 if side == "R" else px + 150
+        lines.append(f"Wire Wire Line\n\t{px} {py} {wire_end} {py}")
+        orient = 2 if side == "R" else 0
+        lines.append(f"Text GLabel {wire_end} {py} {orient}    30   BiDi ~ 0\n{pin.net}")
+
+
+def sheet_file(sheet: str, comps: list[Component], sheet_index: int) -> str:
+    lines = [
+        "EESchema Schematic File Version 4", "LIBS:board-cache", "EELAYER 29 0",
+        "EELAYER END", "$Descr A0 46811 33110", "encoding utf-8", "Sheet 1 1",
+        f'Title "Ti375 GNSS/IMU board - {sheet.replace("_", " ").title()}"',
+        'Date "2026-08-15"', 'Rev "A0"', 'Comp "Open hardware design for JLCPCB"',
+        'Comment1 "Generated from scripts/design_data.py; do not hand-edit"',
+        'Comment2 "No LEDs, no push buttons"', 'Comment3 "Ti375C529C3 / MAX2771 / SCH16T-K01-1"',
+        'Comment4 "JLC08161H-3313 eight-layer stack"', "$EndDescr",
+    ]
+    x, y = 1800, 1800
+    column_width = 3000
+    bottom = 31600
+    stamp = 0x65000000 + sheet_index * 0x10000
+    for comp in comps:
+        for unit, pins in enumerate(chunks(comp), 1):
+            _, half_h, _ = geometry(pins)
+            height = 2 * half_h + 500
+            if y + half_h > bottom:
+                x += column_width
+                y = 1800
+            if x > 45000:
+                raise RuntimeError(f"{sheet} overflow at {comp.ref}")
+            stamp += 1
+            lines += component_block(comp, unit, x, y, stamp)
+            add_pin_connections(lines, pins, x, y)
+            y += height
+    lines += ["$EndSCHEMATC"]
+    return "\n".join(lines) + "\n"
+
+
+def root_file() -> str:
+    lines = [
+        "EESchema Schematic File Version 4", "LIBS:board-cache", "EELAYER 29 0", "EELAYER END",
+        "$Descr A4 11693 8268", "encoding utf-8", "Sheet 1 7",
+        'Title "Ti375 C529 GNSS/IMU acquisition board"', 'Date "2026-08-15"', 'Rev "A0"',
+        'Comp "JLCPCB manufacture/assembly package"',
+        'Comment1 "USB-C 5 V primary; protected external 5 V; no back-feed"',
+        'Comment2 "GPS L1/L1C direct MAX2771 MIXIN_HI; selectable active-antenna bias"',
+        'Comment3 "Every Ti375 programmable GPIO has a documented disposition"',
+        'Comment4 "Generated source - see docs/design_audit.md"', "$EndDescr",
+    ]
+    for idx, sheet in enumerate(SHEETS, 1):
+        x = 1400 + ((idx - 1) % 2) * 4800
+        y = 1000 + ((idx - 1) // 2) * 1900
+        lines += [
+            "$Sheet", f"S {x} {y} 3600 1200", f"U {0x66000000 + idx:08X}",
+            f'F0 "{sheet.replace("_", " ").upper()}" 60', f'F1 "{sheet}.sch" 60', "$EndSheet",
+        ]
+    lines += ["$EndSCHEMATC"]
+    return "\n".join(lines) + "\n"
+
+
+def write_boms() -> None:
+    fields = ["Reference", "Qty", "Value", "Manufacturer", "MPN", "Footprint",
+              "Assembly", "DNP", "Description"]
+    grouped: dict[tuple[str, ...], list[str]] = defaultdict(list)
+    for comp in components:
+        key = (comp.value, comp.manufacturer, comp.mpn, comp.footprint,
+               comp.assembly, "yes" if comp.dnp else "no", comp.description)
+        grouped[key].append(comp.ref)
+    with (OUT / "bom.csv").open("w", newline="") as f:
+        w = csv.DictWriter(f, fieldnames=fields)
+        w.writeheader()
+        for key, refs in sorted(grouped.items(), key=lambda item: item[1][0]):
+            value, manufacturer, mpn, footprint, assembly, dnp, desc = key
+            w.writerow(dict(zip(fields, [",".join(refs), len(refs), value, manufacturer,
+                                         mpn, footprint, assembly, dnp, desc])))
+
+    jlc_fields = ["Comment", "Designator", "Footprint", "LCSC Part #", "Manufacturer",
+                  "Manufacturer Part Number", "Quantity", "Assembly Type", "DNP"]
+    with (OUT / "jlcpcb_bom.csv").open("w", newline="") as f:
+        w = csv.DictWriter(f, fieldnames=jlc_fields)
+        w.writeheader()
+        for key, refs in sorted(grouped.items(), key=lambda item: item[1][0]):
+            value, manufacturer, mpn, footprint, assembly, dnp, _ = key
+            w.writerow({"Comment": value, "Designator": ",".join(refs), "Footprint": footprint,
+                        "LCSC Part #": "", "Manufacturer": manufacturer,
+                        "Manufacturer Part Number": mpn, "Quantity": len(refs),
+                        "Assembly Type": assembly if not dnp == "yes" else "DNP", "DNP": dnp})
+
+
+def duid(text: str) -> str:
+    """Stable UUIDs keep generated KiCad diffs reproducible."""
+    return str(uuid.uuid5(uuid.UUID("830005da-d201-4458-b73e-8946620d7012"), text))
+
+
+def write_native_schematic() -> None:
+    """Write a flat, native KiCad schematic using kiutils' format model.
+
+    Flat global-label connectivity is deliberate: it keeps 529 FPGA balls and
+    273 physical components machine-auditable without hidden hierarchical pins.
+    """
+    try:
+        from kiutils.schematic import Schematic
+        from kiutils.symbol import Symbol, SymbolLib, SymbolPin
+        from kiutils.items.common import (Effects, Fill, Font, PageSettings,
+                                          Position, Property, Stroke, TitleBlock)
+        from kiutils.items.schitems import (GlobalLabel, HierarchicalSheetInstance,
+                                            NoConnect, SchematicSymbol, SymbolInstance)
+        from kiutils.items.syitems import SyRect
+    except ImportError as exc:
+        raise SystemExit("Install the pinned generator dependency: python3 -m pip install -r requirements.txt") from exc
+
+    sch = Schematic.create_new()
+    sch.version = "20231120"
+    sch.generator = "board_generator"
+    sch.uuid = duid("schematic-root")
+    sch.paper = PageSettings(paperSize="A0")
+    sch.titleBlock = TitleBlock(
+        title="Ti375 C529 GPS L1/L1C + SCH16T acquisition board",
+        date="2026-08-15", revision="A0", company="JLCPCB manufacturing design",
+        comments={1: "Generated from official-package connectivity in scripts/design_data.py",
+                  2: "USB-C 5 V primary / protected EXT_5V / no source back-feed",
+                  3: "MAX2771 RF connects only to MIXIN_HI; internal LNAs unused",
+                  4: "No LEDs and no push buttons"})
+    # create_new supplies the root instance; make the path explicit and stable.
+    sch.sheetInstances = [HierarchicalSheetInstance(instancePath="/", page="1")]
+
+    font = Font(width=0.8, height=0.8)
+    hidden = Effects(font=font, hide=True)
+    shown = Effects(font=font)
+    etypes = {
+        "input": "input", "output": "output", "bidirectional": "bidirectional",
+        "power_in": "power_in", "power_out": "power_out",
+        "open_collector": "open_collector", "passive": "passive",
+    }
+
+    def ngeom(pins: list[Pin]):
+        left, right = pins[::2], pins[1::2]
+        rows = max(len(left), len(right), 2)
+        half_h = max(3.81, (rows - 1) * 1.27 + 2.54)
+        endpoints = {}
+        for side_pins, x, angle in ((left, -17.78, 0), (right, 17.78, 180)):
+            start_y = -(len(side_pins) - 1) * 1.27
+            for idx, pin in enumerate(side_pins):
+                endpoints[pin.number] = (x, start_y + idx * 2.54, angle)
+        return 12.7, half_h, endpoints
+
+    lib_by_ref = {}
+    for comp in components:
+        symbol_name = f"BOARD_{safe(comp.ref)}"
+        parent = Symbol.create_new(f"board:{symbol_name}", comp.ref[0], comp.value, comp.footprint)
+        parent.pinNames = True
+        parent.pinNamesOffset = 0.508
+        parent.properties.extend([
+            Property(key="MPN", value=comp.mpn, id=4, effects=hidden),
+            Property(key="Manufacturer", value=comp.manufacturer, id=5, effects=hidden),
+            Property(key="Description", value=comp.description, id=6, effects=hidden),
+        ])
+        seen_power_out_nets: set[str] = set()
+        for unit_idx, pins in enumerate(chunks(comp), 1):
+            unit = Symbol()
+            unit.libId = f"{symbol_name}_{unit_idx}_1"
+            half_w, half_h, endpoints = ngeom(pins)
+            unit.graphicItems.append(SyRect(start=Position(-half_w, -half_h),
+                                            end=Position(half_w, half_h),
+                                            stroke=Stroke(width=0.254, type="default"),
+                                            fill=Fill(type="background")))
+            for pin in pins:
+                x, y, angle = endpoints[pin.number]
+                electrical_type = etypes.get(pin.etype, "passive")
+                if pin.net == "GND" and electrical_type == "bidirectional":
+                    # Deliberately strapped bidirectional configuration pins
+                    # (for example unused TPS6287B I2C) are passive straps in
+                    # this design, not active bus drivers.
+                    electrical_type = "passive"
+                if electrical_type == "power_out" and pin.net in seen_power_out_nets:
+                    electrical_type = "passive"
+                elif electrical_type == "power_out" and pin.net is not None:
+                    seen_power_out_nets.add(pin.net)
+                unit.pins.append(SymbolPin(
+                    electricalType=electrical_type, graphicalStyle="line",
+                    position=Position(x, y, angle), length=5.08,
+                    name=pin.name, number=pin.number,
+                    nameEffects=Effects(font=Font(width=0.65, height=0.65)),
+                    numberEffects=Effects(font=Font(width=0.65, height=0.65))))
+            parent.units.append(unit)
+        sch.libSymbols.append(parent)
+        lib_by_ref[comp.ref] = parent
+
+    # Pack tallest symbols first within functional groups, using generous label clearance.
+    ordered = sorted(components, key=lambda comp: (SHEETS.index(category(comp)),
+                                                    -max(len(x) for x in chunks(comp)), comp.ref))
+    # All origins and margins are exact multiples of KiCad's 1.27-mm
+    # connection grid. Symbol-library Y coordinates are Cartesian (positive
+    # up), whereas schematic sheet Y coordinates grow downward.
+    x, y = 50.8, 38.1
+    column_width, bottom = 127.0, 800.1
+    for comp in ordered:
+        for unit_idx, pins in enumerate(chunks(comp), 1):
+            _, half_h, endpoints = ngeom(pins)
+            height = 2 * half_h + 10.16
+            if y + half_h > bottom:
+                x += column_width
+                y = 38.1
+            if x > 1150.0:
+                raise RuntimeError(f"native A0 sheet overflow at {comp.ref}")
+            origin_y = y + half_h
+            inst_uuid = duid(f"symbol:{comp.ref}:{unit_idx}")
+            inst = SchematicSymbol()
+            inst.libId = f"board:BOARD_{safe(comp.ref)}"
+            inst.position = Position(x, origin_y, 0)
+            inst.unit = unit_idx
+            inst.inBom = not comp.dnp
+            inst.onBoard = True
+            inst.dnp = comp.dnp
+            inst.uuid = inst_uuid
+            inst.properties = [
+                Property(key="Reference", value=comp.ref, id=0,
+                         position=Position(x, origin_y - half_h - 2.0, 0), effects=shown),
+                Property(key="Value", value=comp.value, id=1,
+                         position=Position(x, origin_y + half_h + 2.0, 0), effects=shown),
+                Property(key="Footprint", value=comp.footprint, id=2,
+                         position=Position(x, origin_y, 0), effects=hidden),
+                Property(key="Datasheet", value="", id=3,
+                         position=Position(x, origin_y, 0), effects=hidden),
+                Property(key="MPN", value=comp.mpn, id=4,
+                         position=Position(x, origin_y, 0), effects=hidden),
+                Property(key="Manufacturer", value=comp.manufacturer, id=5,
+                         position=Position(x, origin_y, 0), effects=hidden),
+            ]
+            for pin in pins:
+                inst.pins[pin.number] = duid(f"pin:{comp.ref}:{unit_idx}:{pin.number}")
+                px, py, angle = endpoints[pin.number]
+                pos = Position(x + px, origin_y - py, angle)
+                if pin.net is None:
+                    sch.noConnects.append(NoConnect(position=pos,
+                                                    uuid=duid(f"nc:{comp.ref}:{unit_idx}:{pin.number}")))
+                else:
+                    sch.globalLabels.append(GlobalLabel(
+                        text=pin.net, shape="bidirectional", position=pos, effects=shown,
+                        uuid=duid(f"label:{comp.ref}:{unit_idx}:{pin.number}")))
+            sch.schematicSymbols.append(inst)
+            sch.symbolInstances.append(SymbolInstance(
+                path=f"/{inst_uuid}", reference=comp.ref, unit=unit_idx,
+                value=comp.value, footprint=comp.footprint))
+            y += height
+
+    # ERC power flags are schematic-only assertions. They are generated only
+    # for nets containing power-input pins but no direct power-output pin (for
+    # example GND, external connector feeds, and ferrite-isolated subrails).
+    power_inputs = {pin.net for comp in components for pin in comp.pins
+                    if pin.etype == "power_in" and pin.net is not None}
+    power_outputs = {pin.net for comp in components for pin in comp.pins
+                     if pin.etype == "power_out" and pin.net is not None}
+    flag_nets = sorted(power_inputs - power_outputs)
+    flag_lib = Symbol.create_new("board:PWR_FLAG", "#FLG", "PWR_FLAG")
+    flag_lib.inBom = False
+    flag_lib.onBoard = False
+    flag_lib.isPower = True
+    flag_unit = Symbol()
+    flag_unit.libId = "PWR_FLAG_1_1"
+    flag_unit.pins.append(SymbolPin(
+        electricalType="power_out", graphicalStyle="line",
+        position=Position(0, 0, 0), length=0, name="~", number="1",
+        nameEffects=shown, numberEffects=shown))
+    flag_lib.units.append(flag_unit)
+    sch.libSymbols.append(flag_lib)
+    for idx, net in enumerate(flag_nets, 1):
+        fx = 1117.6 if idx <= 24 else 1168.4
+        fy = 304.8 + ((idx - 1) % 24) * 12.7
+        flag_uuid = duid(f"power-flag:{net}")
+        flag = SchematicSymbol()
+        flag.libId = "board:PWR_FLAG"
+        flag.position = Position(fx, fy, 0)
+        flag.unit = 1
+        flag.inBom = False
+        flag.onBoard = False
+        flag.uuid = flag_uuid
+        ref = f"#FLG{idx:03d}"
+        flag.properties = [
+            Property(key="Reference", value=ref, id=0,
+                     position=Position(fx, fy, 0), effects=hidden),
+            Property(key="Value", value="PWR_FLAG", id=1,
+                     position=Position(fx, fy, 0), effects=hidden),
+            Property(key="Footprint", value="", id=2,
+                     position=Position(fx, fy, 0), effects=hidden),
+            Property(key="Datasheet", value="", id=3,
+                     position=Position(fx, fy, 0), effects=hidden),
+        ]
+        flag.pins["1"] = duid(f"power-flag-pin:{net}")
+        sch.schematicSymbols.append(flag)
+        sch.globalLabels.append(GlobalLabel(
+            text=net, shape="bidirectional", position=Position(fx, fy, 0), effects=shown,
+            uuid=duid(f"power-flag-label:{net}")))
+        sch.symbolInstances.append(SymbolInstance(
+            path=f"/{flag_uuid}", reference=ref, unit=1, value="PWR_FLAG", footprint=""))
+    sch.to_file(str(HW / "board.kicad_sch"))
+
+    external_symbols = copy.deepcopy(sch.libSymbols)
+    for symbol in external_symbols:
+        symbol.libraryNickname = None
+    SymbolLib(version="20231120", generator="board_generator",
+              symbols=external_symbols).to_file(str(HW / "board.kicad_sym"))
+    (HW / "sym-lib-table").write_text(
+        '(sym_lib_table\n  (version 7)\n'
+        '  (lib (name "board")(type "KiCad")(uri "${KIPRJMOD}/board.kicad_sym")(options "")(descr "Generated board symbols"))\n)\n')
+    (HW / "fp-lib-table").write_text(
+        '(fp_lib_table\n  (version 7)\n'
+        '  (lib (name "board")(type "KiCad")(uri "${KIPRJMOD}/board.pretty")(options "")(descr "Official-land-pattern custom footprints"))\n)\n')
+
+
+def main() -> None:
+    (HW / "board-cache.lib").write_text(symbol_library())
+    assignments = {sheet: [] for sheet in SHEETS}
+    for comp in components:
+        assignments[category(comp)].append(comp)
+    for idx, sheet in enumerate(SHEETS, 1):
+        (HW / f"{sheet}.sch").write_text(sheet_file(sheet, assignments[sheet], idx))
+    (HW / "board.sch").write_text(root_file())
+    write_boms()
+    write_native_schematic()
+    (HW / "board.kicad_pro").write_text(
+        '{\n  "meta": { "filename": "board.kicad_pro", "version": 1 },\n'
+        '  "erc": {}, "net_settings": {}, "text_variables": {}\n}\n')
+    print(f"generated {len(components)} components on {len(SHEETS)} hierarchical sheets")
+
+
+if __name__ == "__main__":
+    main()
@@ -0,0 +1,599 @@
+#!/usr/bin/env python3
+"""Create the placed eight-layer KiCad PCB from the audited design database.
+
+The script is deterministic so placement, net assignments, stackup, and rules
+can be regenerated and independently audited. Routing uses the staged
+BGA/plane/Freerouting flow in scripts/README.md; finalize_routing.py replaces
+autorouted RF/USB copper with audited deterministic geometry.
+"""
+
+from __future__ import annotations
+
+import math
+import re
+import sys
+from collections import defaultdict
+from pathlib import Path
+
+import pcbnew
+
+ROOT = Path(__file__).resolve().parents[1]
+sys.path.insert(0, str(ROOT / "scripts"))
+from design_data import components  # noqa: E402
+
+HW = ROOT / "hardware"
+BOARD_FILE = HW / "board.kicad_pcb"
+STOCK = Path("/usr/share/kicad/footprints")
+
+# The distributed SMT test pads and removal of the former bottom test-point
+# field allow a compact 155 x 90 mm outline.
+X0, Y0, X1, Y1 = 20.0, 20.0, 175.0, 110.0
+
+
+def mm(value: float) -> int:
+    return pcbnew.FromMM(value)
+
+
+def point(x: float, y: float) -> pcbnew.VECTOR2I:
+    return pcbnew.VECTOR2I_MM(x, y)
+
+
+def footprint_path(identifier: str) -> tuple[Path, str]:
+    library, name = identifier.split(":", 1)
+    if library == "board":
+        return HW / "board.pretty", name
+    return STOCK / f"{library}.pretty", name
+
+
+MAJOR = {
+    # FPGA/configuration.  All four PMODs are on the north edge, close to the
+    # BGA side carrying their I/O banks.  Rotation makes the connector field
+    # shallow and keeps all modules clear of the RF and IMU regions.
+    "U1": (108, 72, 0), "U26": (97, 54, 0),
+    "JPMOD1": (78, 24, 0), "JPMOD2": (96, 24, 0),
+    "JPMOD3": (114, 24, 0), "JPMOD4": (132, 24, 0),
+
+    # USB-C and debug block.
+    "J1": (23.1, 48, 270), "U5": (30.5, 44.5, 0), "U6": (30.5, 51.5, 0),
+    "U2": (43, 55, 0), "U25": (35, 62, 0), "U3": (51, 63, 0),
+    "U29": (60, 54.5, 0), "U30": (67, 58.5, 0), "U31": (62, 63.5, 0),
+
+    # Mechanically quiet IMU region.
+    "U22": (51, 84, 0),
+
+    # Protected input and switching-power block.
+    "J3": (24, 100, 90), "U7": (34, 96, 0), "U8": (42, 104, 0), "U9": (46, 96, 0),
+    "U10": (54, 104, 0), "U11": (59, 104, 0), "U12": (64, 94, 0),
+    # High-current FPGA rails sit directly south of the BGA.  This keeps the
+    # 15-A core path and both 6-A I/O-rail paths short enough to enter their
+    # local plane patches without long high-current traces.
+    "U13": (100, 93, 0), "U14": (115, 97, 0), "U15": (130, 97, 0), "U16": (90, 98, 0),
+    "U17": (143, 63, 0), "U18": (136, 67, 0), "U19": (152, 67, 0), "U20": (163, 63, 0),
+    "U28": (141, 72.5, 0), "U32": (136, 74.5, 0), "U34": (88, 88, 0),
+    "Q1": (70, 62, 0),
+
+    # User reset controls remain edge-accessible; only the tiny protection and
+    # open-drain circuitry sit inward from the connector/button.
+    "J4": (73, 106.5, 180), "SW1": (82, 106, 0), "D2": (78, 100.5, 0),
+    "U33": (87, 103, 0),
+
+    # RF front end.  J2's launch reference is exactly on the right PCB edge.
+    "J2": (175, 42, 0), "D1": (170.45, 40.75, 0), "FL1": (164.0, 42.1, 180),
+    "J5": (171, 56, 0), "U27": (165, 52, 0), "U21": (155.5, 45, 0),
+    "U23": (149, 53, 0), "U24": (137, 55, 0),
+}
+
+# Parts whose exact physical location materially affects signal integrity,
+# power-loop area, or mechanical performance.
+SPECIAL = {
+    # RF series parts are collinear.  L4 pad 2 lands directly on the SMA feed
+    # rather than creating a bias-tee stub; the optional shunt-tuning pad 1s
+    # likewise land on the two controlled-impedance sections.
+    "C83": (167.5, 42.1, 180), "C84": (162.15, 41.45, 90), "R39": (160.5, 42.1, 180),
+    "C85": (159.0, 40.70, 90), "L4": (169.5, 42.585, 90),
+    "L1": (105.0, 91.0, 0), "L2": (115.0, 91.0, 0), "L3": (130.0, 91.0, 0),
+    "FB1": (60.0, 88.5, 0), "FB2": (36.0, 49.0, 0), "FB3": (39.0, 46.5, 0),
+    "R63": (37.0, 55.50, 0), "R64": (37.0, 54.50, 0),
+    # MAX2771 output damping sits at the receiver; FPGA-driven 3-wire control
+    # damping sits at the BGA source.  R55 holds SHDN low at the receiver.
+    "R45": (151.0, 44.5, 0),
+    "R46": (154.6, 50.2, 90), "R47": (155.8, 50.2, 90),
+    "R48": (157.0, 50.2, 90), "R49": (158.2, 50.2, 90),
+    "R50": (160.5, 47.5, 90),
+    "R51": (121.5, 65.5, 0), "R52": (121.5, 66.7, 0),
+    "R53": (121.5, 67.9, 0), "R54": (121.5, 69.1, 0),
+    "R55": (161.7, 44.5, 90), "C89": (146.5, 53.0, 0),
+    # 40-MHz termination is at U24.  SafeSPI controller outputs are terminated
+    # beside the FPGA; MISO and EXTRESN bias remain beside the IMU.
+    "R56": (140.2, 54.35, 0),
+    "R57": (102.0, 58.8, 0), "R58": (104.0, 58.8, 0),
+    "R59": (106.0, 58.8, 0), "R60": (60.0, 83.6, 0),
+    "R61": (41.0, 83.6, 0),
+    # Buffered FTDI interface-1 hard JTAG.  Output-series parts sit directly
+    # after the power-domain buffer; the TDO part is retained at the FPGA side.
+    "R70": (65.0, 52.0, 0), "R71": (65.0, 53.2, 0),
+    "R72": (65.0, 54.4, 0), "R73": (96.0, 70.0, 0),
+    "R74": (96.0, 71.2, 0),
+}
+
+# Small SMT bring-up pads live beside the circuit they measure; there is no
+# connector-like test-point bank along the board edge.
+SPECIAL.update({
+    "TP1": (37.5, 94.0, 0), "TP2": (45.5, 104.0, 0),
+    "TP3": (166.5, 54.0, 0), "TP4": (29.0, 39.0, 0),
+    "TP5": (22.0, 89.0, 0), "TP6": (49.5, 98.5, 0),
+    "TP7": (66.5, 90.0, 0), "TP8": (105.0, 98.0, 0),
+    "TP9": (118.0, 102.0, 0), "TP10": (133.0, 102.0, 0),
+    "TP11": (146.0, 61.0, 0), "TP12": (137.0, 70.0, 0),
+    "TP13": (97.0, 58.0, 0), "TP14": (99.0, 58.0, 0),
+    "TP15": (91.5, 103.0, 0),
+    # Added configuration/JTAG pulls and reset-domain support.
+    "R89": (96.0, 65.0, 0),
+    "R90": (96.0, 66.2, 0), "R91": (96.0, 67.4, 0), "R92": (96.0, 68.6, 0),
+    "R93": (96.0, 72.4, 0), "R94": (96.0, 73.6, 0),
+    "R95": (96.0, 74.8, 0), "R96": (96.0, 76.0, 0),
+    "R97": (59.0, 65.5, 0), "R98": (145.0, 74.5, 0),
+    "R99": (73.0, 60.0, 0), "R100": (73.0, 61.2, 0), "R101": (73.0, 62.4, 0),
+    "R102": (84.0, 100.5, 0), "R103": (80.0, 102.0, 0),
+    "C120": (145.0, 72.5, 0), "C121": (82.0, 102.0, 0),
+    "C122": (142.0, 76.5, 0), "C123": (64.0, 48.5, 0),
+    "C124": (69.5, 56.0, 0), "C125": (62.0, 66.5, 0),
+    "C126": (136.0, 78.0, 0), "C127": (90.0, 100.5, 0),
+    "R104": (83.0, 86.8, 0), "R105": (83.0, 88.0, 0),
+    "R106": (83.0, 89.2, 0), "C128": (93.0, 88.0, 0),
+})
+
+
+# Critical placement references must never silently drift when parts are added
+# earlier in design_data.py.  A mismatch here would corrupt RF geometry or put
+# a source-series resistor at the receiver end of a long digital trace.
+CRITICAL_REF_NETS = {
+    "C83": {"RF_SMA", "RF_PRE_SAW"},
+    "C84": {"RF_POST_SAW", "GND"},
+    "R39": {"RF_POST_SAW", "MAX_MIXIN_HI"},
+    "C85": {"MAX_MIXIN_HI", "GND"},
+    "R56": {"OSC40_OUT", "CLK_40M_FPGA"},
+    "R57": {"IMU_SCK", "IMU_SCK_DEV"},
+    "R58": {"IMU_MOSI", "IMU_MOSI_DEV"},
+    "R59": {"IMU_CS", "IMU_CS_DEV"},
+    "R60": {"IMU_MISO", "IMU_MISO_DEV"},
+}
+_component_by_ref = {component.ref: component for component in components}
+for _ref, _expected_nets in CRITICAL_REF_NETS.items():
+    _actual_nets = {pin.net for pin in _component_by_ref[_ref].pins if pin.net}
+    assert _actual_nets == _expected_nets, (_ref, _actual_nets, _expected_nets)
+
+
+def local_offsets(count: int, clearance_radius: float) -> list[tuple[float, float]]:
+    """Return dense candidate rings for collision-aware group placement."""
+    result: list[tuple[float, float]] = []
+    ring = 0
+    while len(result) < count:
+        r = clearance_radius + ring * 1.20
+        slots = max(12, int(2 * math.pi * r / 0.80))
+        for idx in range(slots):
+            angle = -math.pi / 2 + idx * 2 * math.pi / slots
+            result.append((r * math.cos(angle), r * math.sin(angle)))
+            if len(result) == count:
+                return result
+        ring += 1
+    return result
+
+
+def courtyard_box(fp: pcbnew.FOOTPRINT, margin: float = 0.12) -> tuple[float, float, float, float]:
+    layers = pcbnew.LSET()
+    layers.AddLayer(pcbnew.F_CrtYd)
+    layers.AddLayer(pcbnew.B_CrtYd)
+    box = fp.GetLayerBoundingBox(layers)
+    return (pcbnew.ToMM(box.GetX()) - margin, pcbnew.ToMM(box.GetY()) - margin,
+            pcbnew.ToMM(box.GetRight()) + margin, pcbnew.ToMM(box.GetBottom()) + margin)
+
+
+def boxes_overlap(a: tuple[float, float, float, float], b: tuple[float, float, float, float]) -> bool:
+    return a[0] < b[2] and a[2] > b[0] and a[1] < b[3] and a[3] > b[1]
+
+
+def add_text(board: pcbnew.BOARD, value: str, x: float, y: float, size: float = 1.0,
+             layer: int = pcbnew.F_SilkS, angle: float = 0) -> None:
+    text = pcbnew.PCB_TEXT(board)
+    text.SetText(value)
+    text.SetPosition(point(x, y))
+    text.SetTextSize(pcbnew.VECTOR2I(mm(size), mm(size)))
+    text.SetTextThickness(mm(max(0.15, size * 0.15)))
+    text.SetLayer(layer)
+    text.SetTextAngle(pcbnew.EDA_ANGLE(angle, pcbnew.DEGREES_T))
+    board.Add(text)
+
+
+def add_outline(board: pcbnew.BOARD) -> None:
+    for start, end in (((X0, Y0), (X1, Y0)), ((X1, Y0), (X1, Y1)),
+                       ((X1, Y1), (X0, Y1)), ((X0, Y1), (X0, Y0))):
+        seg = pcbnew.PCB_SHAPE(board)
+        seg.SetShape(pcbnew.SHAPE_T_SEGMENT)
+        seg.SetStart(point(*start))
+        seg.SetEnd(point(*end))
+        seg.SetWidth(mm(0.05))
+        seg.SetLayer(pcbnew.Edge_Cuts)
+        board.Add(seg)
+
+
+def configure_rules(board: pcbnew.BOARD) -> None:
+    ds = board.GetDesignSettings()
+    ds.SetBoardThickness(mm(1.6))
+    ds.m_TrackMinWidth = mm(0.10)
+    ds.m_MinClearance = mm(0.10)
+    ds.m_ViasMinSize = mm(0.45)
+    ds.m_MinThroughDrill = mm(0.225)
+    ds.m_ViasMinAnnularWidth = mm(0.10)
+    ds.m_CopperEdgeClearance = mm(0.25)
+    ds.m_HoleClearance = mm(0.19)
+
+    settings = ds.m_NetSettings
+    default = settings.GetDefaultNetclass()
+    default.SetClearance(mm(0.10))
+    default.SetTrackWidth(mm(0.12))
+    default.SetViaDiameter(mm(0.45))
+    default.SetViaDrill(mm(0.225))
+    default.SetDiffPairWidth(mm(0.135))
+    default.SetDiffPairGap(mm(0.15))
+
+    def netclass(name: str, clearance: float, width: float, via: float = 0.45, drill: float = 0.225,
+                 diff_width: float | None = None, diff_gap: float | None = None) -> None:
+        nc = pcbnew.NETCLASS(name)
+        nc.SetClearance(mm(clearance))
+        nc.SetTrackWidth(mm(width))
+        nc.SetViaDiameter(mm(via))
+        nc.SetViaDrill(mm(drill))
+        if diff_width is not None:
+            nc.SetDiffPairWidth(mm(diff_width))
+        if diff_gap is not None:
+            nc.SetDiffPairGap(mm(diff_gap))
+        settings.SetNetclass(name, nc)
+
+    netclass("BGA_ESCAPE", 0.10, 0.10)
+    netclass("RF50_CPWG", 0.20, 0.164)
+    netclass("USB90_DIFF", 0.15, 0.135, diff_width=0.135, diff_gap=0.15)
+    netclass("CLOCK", 0.15, 0.15)
+    # A 0.45/0.225-mm dogbone via with 0.10-mm clearance fits the Ti375's
+    # 0.8-mm BGA pitch.  The 0.40-mm trunk width is retained; Freerouting's
+    # automatic neck-down is allowed only inside the escape field.
+    netclass("POWER", 0.10, 0.40, 0.45, 0.225)
+
+    for pattern in ("RF_SMA", "RF_PRE_SAW", "RF_POST_SAW", "MAX_MIXIN_HI"):
+        settings.SetNetclassPatternAssignment(pattern, "RF50_CPWG")
+    for pattern in ("USB_D_P", "USB_D_N", "FTDI_D_P", "FTDI_D_N"):
+        settings.SetNetclassPatternAssignment(pattern, "USB90_DIFF")
+    # Use exact clock families so VCC3V0_CLK does not acquire an accidental
+    # aggregate CLOCK,POWER effective class.
+    for pattern in ("MAX_CLKOUT*", "MAX_SCLK*", "MAX_ADC_CLKIN", "QSPI_SCLK",
+                    "CLK_40M_FPGA", "OSC40_OUT", "TCXO16_OUT", "FTDI_OSC12",
+                    "FTDI_OSCI", "IMU_SCK*", "*TCK*"):
+        settings.SetNetclassPatternAssignment(pattern, "CLOCK")
+    for pattern in ("VCC*", "SYS5", "VBUS_RAW", "USB5_PROT", "EXT5_*", "GND", "CORE_SW",
+                    "BUCK1V8_SW", "BUCK3V3_SW", "ANT_BIAS_SEL", "ANT_BIAS_SW",
+                    "FTDI_1V8", "FTDI_VPHY", "FTDI_VPLL", "IMU_3V3",
+                    "IMU_VREGA2", "IMU_VREGD", "USB_SHIELD"):
+        settings.SetNetclassPatternAssignment(pattern, "POWER")
+    settings.SetNetclassPatternAssignment("EXP_*", "BGA_ESCAPE")
+    settings.SetNetclassPatternAssignment("PMOD*", "BGA_ESCAPE")
+
+
+def add_stackup(board: pcbnew.BOARD) -> None:
+    board.SetCopperLayerCount(8)
+    board.SetLayerName(pcbnew.In1_Cu, "L2_GND")
+    board.SetLayerName(pcbnew.In2_Cu, "L3_SIG")
+    board.SetLayerName(pcbnew.In3_Cu, "L4_PWR")
+    board.SetLayerName(pcbnew.In4_Cu, "L5_SIG")
+    board.SetLayerName(pcbnew.In5_Cu, "L6_SIG")
+    board.SetLayerName(pcbnew.In6_Cu, "L7_GND")
+    board.SetLayerType(pcbnew.In1_Cu, pcbnew.LT_POWER)
+    board.SetLayerType(pcbnew.In3_Cu, pcbnew.LT_POWER)
+    board.SetLayerType(pcbnew.In6_Cu, pcbnew.LT_POWER)
+
+
+def place_components(board: pcbnew.BOARD) -> dict[str, pcbnew.FOOTPRINT]:
+    net_items: dict[str, pcbnew.NETINFO_ITEM] = {}
+    for comp in components:
+        for pin in comp.pins:
+            if pin.net and pin.net not in net_items:
+                item = pcbnew.NETINFO_ITEM(board, pin.net)
+                board.Add(item)
+                net_items[pin.net] = item
+
+    loaded: dict[str, pcbnew.FOOTPRINT] = {}
+    current_group = "U1"
+    groups: dict[str, list] = defaultdict(list)
+    for comp in components:
+        if comp.ref in MAJOR:
+            current_group = comp.ref
+        if comp.ref not in MAJOR and comp.ref not in SPECIAL:
+            if comp.description.startswith("Ti375 ") or "Efinix mandatory" in comp.description:
+                groups["U1"].append(comp)
+            else:
+                groups[current_group].append(comp)
+
+    group_positions: dict[str, list[tuple[float, float]]] = {}
+    for group, members in groups.items():
+        radius = 4.0
+        if group == "U1":
+            radius = 11.5
+        elif group in {"U2", "U13", "U21", "U22"}:
+            radius = 5.5
+        # Extra candidates let the actual courtyard collision pass skip places
+        # occupied by adjacent functional blocks and larger bulk capacitors.
+        group_positions[group] = local_offsets(max(1000, len(members) * 40), radius)
+
+    automatic: list[tuple[object, str]] = []
+    current_group = "U1"
+    for comp in components:
+        path, name = footprint_path(comp.footprint)
+        fp = pcbnew.FootprintLoad(str(path), name)
+        if fp is None:
+            raise RuntimeError(f"Cannot load {comp.footprint} for {comp.ref}")
+        fp.SetReference(comp.ref)
+        fp.SetValue(comp.value)
+        fp.Reference().SetVisible(False)
+        fp.Value().SetVisible(False)
+        fp.Reference().SetLayer(pcbnew.F_Fab)
+        fp.Value().SetLayer(pcbnew.F_Fab)
+        # Dense components retain complete assembly/Fab graphics, while the
+        # production silkscreen is limited to functional labels and the IMU
+        # orientation mark so it cannot print on fine-pitch copper.
+        for graphic in fp.GraphicalItems():
+            if graphic.GetLayer() == pcbnew.F_SilkS:
+                graphic.SetLayer(pcbnew.F_Fab)
+        if comp.ref in MAJOR:
+            current_group = comp.ref
+            x, y, rotation = MAJOR[comp.ref]
+        elif comp.ref in SPECIAL:
+            x, y, rotation = SPECIAL[comp.ref]
+        else:
+            group = "U1" if (comp.description.startswith("Ti375 ") or "Efinix mandatory" in comp.description) else current_group
+            ax, ay, _ = MAJOR[group]
+            x, y, rotation = ax, ay, 0
+            automatic.append((comp, group))
+        fp.SetPosition(point(x, y))
+        fp.SetOrientationDegrees(rotation)
+        if comp.dnp:
+            fp.SetDNP(True)
+            fp.SetExcludedFromPosFiles(True)
+        fp.SetField("MPN", comp.mpn)
+        fp.SetField("Manufacturer", comp.manufacturer)
+        for field_name in ("MPN", "Manufacturer"):
+            field = fp.GetField(field_name)
+            field.SetVisible(False)
+            field.SetLayer(pcbnew.F_Fab)
+        board.Add(fp)
+        loaded[comp.ref] = fp
+
+        pad_map: dict[str, list[pcbnew.PAD]] = defaultdict(list)
+        for physical_pad in fp.Pads():
+            if physical_pad.GetNumber():
+                pad_map[physical_pad.GetNumber()].append(physical_pad)
+        for pin in comp.pins:
+            for physical_pad in pad_map[str(pin.number)]:
+                if pin.net:
+                    physical_pad.SetNet(net_items[pin.net])
+
+    # Place all automatic local parts after the fixed functional floorplan is
+    # known, using their actual KiCad courtyards rather than nominal body size.
+    occupied = [courtyard_box(loaded[ref]) for ref in (*MAJOR.keys(), *SPECIAL.keys()) if ref in loaded]
+    search_start: dict[str, int] = defaultdict(int)
+    for comp, group in automatic:
+        fp = loaded[comp.ref]
+        ax, ay, _ = MAJOR[group]
+        candidates = group_positions[group]
+        placed = False
+        for idx in range(search_start[group], len(candidates)):
+            dx, dy = candidates[idx]
+            x, y = ax + dx, ay + dy
+            fp.SetPosition(point(x, y))
+            candidate = courtyard_box(fp)
+            # Keep assembly courtyards on-board; edge connectors are all fixed
+            # members and are intentionally permitted to protrude.
+            if candidate[0] < X0 + 0.5 or candidate[2] > X1 - 0.5 or candidate[1] < Y0 + 0.5 or candidate[3] > Y1 - 0.5:
+                continue
+            if any(boxes_overlap(candidate, used) for used in occupied):
+                continue
+            occupied.append(candidate)
+            search_start[group] = idx + 1
+            placed = True
+            break
+        if not placed:
+            raise RuntimeError(f"Could not place {comp.ref} near {group} without courtyard overlap")
+    board.BuildListOfNets()
+    return loaded
+
+
+def add_mounting_holes(board: pcbnew.BOARD) -> None:
+    path = STOCK / "MountingHole.pretty"
+    # The lower-left power connector owns the corner; offset H3 so its screw
+    # head and courtyard cannot collide with J3.
+    for idx, (x, y) in enumerate(((24, 24), (171, 24), (31, 106), (171, 106)), 1):
+        fp = pcbnew.FootprintLoad(str(path), "MountingHole_3.2mm_M3")
+        if fp is None:
+            raise RuntimeError("Missing KiCad M3 mounting-hole footprint")
+        fp.SetReference(f"H{idx}")
+        fp.Reference().SetVisible(False)
+        fp.SetPosition(point(x, y))
+        board.Add(fp)
+
+
+def add_zone(board: pcbnew.BOARD, net_name: str, layer: int,
+             bounds: tuple[float, float, float, float], priority: int = 0) -> None:
+    """Add a retained solid inner-layer plane region.
+
+    These regions are retained even before fanout vias exist so the Specctra
+    export contains real plane targets for the router.  The final refill then
+    clears anti-pads around every unrelated via and plated hole.
+    """
+    net = board.FindNet(net_name)
+    if net is None:
+        raise RuntimeError(f"Cannot create plane for missing net {net_name}")
+    x0, y0, x1, y1 = bounds
+    zone = pcbnew.ZONE(board)
+    zone.SetLayer(layer)
+    zone.SetNet(net)
+    zone.SetLocalClearance(mm(0.20))
+    zone.SetMinThickness(mm(0.10))
+    zone.SetThermalReliefGap(mm(0.20))
+    zone.SetThermalReliefSpokeWidth(mm(0.25))
+    zone.SetPadConnection(pcbnew.ZONE_CONNECTION_FULL)
+    zone.SetIslandRemovalMode(pcbnew.ISLAND_REMOVAL_MODE_NEVER)
+    zone.SetAssignedPriority(priority)
+    outline = zone.Outline()
+    outline.NewOutline()
+    for x, y in ((x0, y0), (x1, y0), (x1, y1), (x0, y1)):
+        outline.Append(point(x, y))
+    board.Add(zone)
+
+
+def add_power_planes(board: pcbnew.BOARD) -> None:
+    # Continuous reference planes immediately below the two outer signal
+    # layers.  A 0.50-mm inset exceeds JLCPCB's copper-to-edge requirement.
+    for layer in (pcbnew.In1_Cu, pcbnew.In6_Cu):
+        add_zone(board, "GND", layer, (X0 + 0.50, Y0 + 0.50, X1 - 0.50, Y1 - 0.50))
+
+    # L4 is a deliberately split DC plane.  Islands follow the functional
+    # floorplan; no high-speed route uses L4 and no signal crosses a split on
+    # either adjacent routing layer without a nearby return transition.
+    islands = (
+        ("VCC3V3_AUX", (20.50, 38.00, 67.00, 72.00)),
+        ("VCC3V3",     (39.00, 73.00, 68.00, 85.10)),
+        ("SYS5",       (20.50, 85.50, 90.00, 109.50)),
+        ("SYS5",       (90.40, 106.40, 140.00, 109.50)),
+        # Core balls are interspersed with GND/auxiliary balls, so a complete
+        # local patch (with automatic anti-pads) replaces the invalid left/right
+        # voltage split that previously crossed the BGA field.
+        ("VCC0V95",    (95.00, 60.50, 119.00, 94.00)),
+        ("VCC3V3",     (119.50, 87.00, 140.00, 106.00)),
+        ("VCC3V0_CLK", (126.00, 50.00, 148.50, 72.00)),
+        ("VCC3V0_DIG", (119.50, 60.50, 125.50, 72.00)),
+        ("VCC3V0_DIG", (148.90, 50.40, 164.00, 72.00)),
+        ("VCC3V3_ANT", (164.40, 50.40, 174.50, 70.00)),
+        ("VCC3V0_RF",  (145.00, 36.00, 174.50, 50.00)),
+    )
+    for priority, (net_name, bounds) in enumerate(islands, 1):
+        add_zone(board, net_name, pcbnew.In3_Cu, bounds, priority)
+
+    # Local BGA supply patches.  L2/L7 remain uninterrupted ground planes;
+    # only the area below and immediately south of U1 is reserved on these
+    # otherwise routable signal layers.
+    add_zone(board, "VCC1V8", pcbnew.In4_Cu, (97.50, 60.50, 122.00, 101.00), 50)
+    add_zone(board, "VCC3V3", pcbnew.In5_Cu, (97.50, 60.50, 140.00, 101.00), 50)
+
+
+def add_temporary_critical_keepouts(board: pcbnew.BOARD) -> None:
+    """Reserve the layers below RF and USB while Freerouting is running.
+
+    F.Cu deliberately remains available so the autorouted critical nets reserve
+    their own top-layer corridors.  The rule areas prevent unrelated signal
+    tracks and through vias from crossing underneath.  finalize_routing.py
+    removes these temporary areas before installing the audited copper.
+    """
+    layers = pcbnew.LSET()
+    for layer in (pcbnew.In2_Cu, pcbnew.In4_Cu, pcbnew.In5_Cu, pcbnew.B_Cu):
+        layers.AddLayer(layer)
+    for name, bounds in (
+            ("TEMP_RF_NO_DIGITAL_BELOW", (152.0, 36.0, 174.5, 49.5)),
+            ("TEMP_USB_NO_CROSSING_BELOW", (22.0, 41.5, 44.5, 57.5))):
+        x0, y0, x1, y1 = bounds
+        area = pcbnew.ZONE(board)
+        area.SetZoneName(name)
+        area.SetIsRuleArea(True)
+        area.SetLayerSet(layers)
+        area.SetDoNotAllowTracks(True)
+        area.SetDoNotAllowVias(True)
+        area.SetDoNotAllowPads(False)
+        area.SetDoNotAllowFootprints(False)
+        area.SetDoNotAllowZoneFills(False)
+        outline = area.Outline()
+        outline.NewOutline()
+        for x, y in ((x0, y0), (x1, y0), (x1, y1), (x0, y1)):
+            outline.Append(point(x, y))
+        board.Add(area)
+
+
+def add_documentation_graphics(board: pcbnew.BOARD) -> None:
+    add_text(board, "Ti375 GNSS / SCH16T", 105, 33.0, 1.1)
+    add_text(board, "REV A1  JLC08161H-3313  8L", 105, 35.2, 0.8)
+    add_text(board, "USB-C 5V", 31, 35.5, 0.9)
+    add_text(board, "EXT_5V", 28, 108.0, 0.9)
+    add_text(board, "GPS L1/L1C ACTIVE", 162, 34, 0.9)
+    add_text(board, "BIAS J5: 3V3-OFF-5V", 163, 72, 0.8)
+    add_text(board, "RF - NO DIGITAL ROUTING BELOW", 151, 69, 0.8)
+    add_text(board, "IMU PIN1", 42, 78, 0.8)
+    add_text(board, "X+ ->   Y+ ^", 51, 84, 0.8)
+    add_text(board, "USB JTAG / UART", 55, 38.5, 0.8)
+    add_text(board, "EXT_RST", 73, 101.5, 0.8)
+    add_text(board, "FPGA RESET", 82, 109.0, 0.8)
+    add_text(board, "PMOD1 3V3", 78, 30, 0.8)
+    add_text(board, "PMOD2 3V3", 96, 30, 0.8)
+    add_text(board, "PMOD3 1V8", 114, 30, 0.8)
+    add_text(board, "PMOD4 1V8", 132, 30, 0.8)
+
+
+STACKUP = '''\t\t(stackup
+\t\t\t(layer "F.SilkS" (type "Top Silk Screen"))
+\t\t\t(layer "F.Paste" (type "Top Solder Paste"))
+\t\t\t(layer "F.Mask" (type "Top Solder Mask") (thickness 0.01))
+\t\t\t(layer "F.Cu" (type "copper") (thickness 0.035))
+\t\t\t(layer "dielectric 1" (type "prepreg") (thickness 0.0994) (material "JLC 3313") (epsilon_r 4.1) (loss_tangent 0.02))
+\t\t\t(layer "L2_GND" (type "copper") (thickness 0.0152))
+\t\t\t(layer "dielectric 2" (type "core") (thickness 0.1) (material "JLC FR-4 core") (epsilon_r 4.36) (loss_tangent 0.02))
+\t\t\t(layer "L3_SIG" (type "copper") (thickness 0.0152))
+\t\t\t(layer "dielectric 3" (type "prepreg") (thickness 0.3568) (material "JLC 3x2116") (epsilon_r 4.16) (loss_tangent 0.02))
+\t\t\t(layer "L4_PWR" (type "copper") (thickness 0.0152))
+\t\t\t(layer "dielectric 4" (type "core") (thickness 0.3) (material "JLC FR-4 core") (epsilon_r 4.41) (loss_tangent 0.02))
+\t\t\t(layer "L5_SIG" (type "copper") (thickness 0.0152))
+\t\t\t(layer "dielectric 5" (type "prepreg") (thickness 0.3568) (material "JLC 3x2116") (epsilon_r 4.16) (loss_tangent 0.02))
+\t\t\t(layer "L6_SIG" (type "copper") (thickness 0.0152))
+\t\t\t(layer "dielectric 6" (type "core") (thickness 0.1) (material "JLC FR-4 core") (epsilon_r 4.36) (loss_tangent 0.02))
+\t\t\t(layer "L7_GND" (type "copper") (thickness 0.0152))
+\t\t\t(layer "dielectric 7" (type "prepreg") (thickness 0.0994) (material "JLC 3313") (epsilon_r 4.1) (loss_tangent 0.02))
+\t\t\t(layer "B.Cu" (type "copper") (thickness 0.035))
+\t\t\t(layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01))
+\t\t\t(layer "B.Paste" (type "Bottom Solder Paste"))
+\t\t\t(layer "B.SilkS" (type "Bottom Silk Screen"))
+\t\t\t(copper_finish "ENIG")
+\t\t\t(dielectric_constraints yes)
+\t\t)'''
+
+
+def inject_stackup(path: Path) -> None:
+    data = path.read_text()
+    if "\n\t\t(stackup\n" in data:
+        data = re.sub(r"\n\t\t\(stackup\n.*?\n\t\t\)\n", "\n" + STACKUP + "\n", data, count=1, flags=re.S)
+    else:
+        data = data.replace("\n\t(setup\n", "\n\t(setup\n" + STACKUP + "\n", 1)
+    data = data.replace("(allow_soldermask_bridges_in_footprints no)",
+                        "(allow_soldermask_bridges_in_footprints yes)")
+    path.write_text(data)
+
+
+def main() -> None:
+    board = pcbnew.BOARD()
+    add_stackup(board)
+    configure_rules(board)
+    add_outline(board)
+    loaded = place_components(board)
+    add_mounting_holes(board)
+    add_power_planes(board)
+    add_temporary_critical_keepouts(board)
+    add_documentation_graphics(board)
+    title = board.GetTitleBlock()
+    title.SetTitle("Ti375 C529 GPS L1/L1C + SCH16T acquisition board")
+    title.SetRevision("A0")
+    title.SetCompany("JLCPCB manufacturing design")
+    title.SetComment(0, "USB-C 5 V primary; protected EXT_5V; no back-feed")
+    title.SetComment(1, "JLC08161H-3313 exact eight-layer construction")
+    if not pcbnew.ZONE_FILLER(board).Fill(board.Zones()):
+        raise RuntimeError("Initial inner-plane fill failed")
+    pcbnew.SaveBoard(str(BOARD_FILE), board)
+    inject_stackup(BOARD_FILE)
+    print(f"Placed {len(loaded)} schematic components plus four NPTH mounting holes")
+    print(f"Saved {BOARD_FILE}")
+
+
+if __name__ == "__main__":
+    main()
@@ -0,0 +1,52 @@
+#!/usr/bin/env python3
+"""Compensate Freerouting 2.3.0's KiCad-10 DSN clearance scale mismatch.
+
+KiCad exports widths and clearances in micrometres.  Freerouting 2.3.0 keeps
+the widths but internally imports DSN clearance values at one quarter of the
+intended physical value.  Scaling only ``(clearance N)`` entries by four makes
+the router's physical rules match the source KiCad board.  Coordinates, track
+widths, vias, drills, padstacks, and keepouts are deliberately untouched.
+"""
+
+from __future__ import annotations
+
+import argparse
+import re
+from pathlib import Path
+
+
+CLEARANCE = re.compile(r"(\(clearance\s+)(\d+(?:\.\d+)?)")
+
+
+def main() -> None:
+    parser = argparse.ArgumentParser()
+    parser.add_argument("input", type=Path)
+    parser.add_argument("output", type=Path)
+    parser.add_argument("--factor", type=float, default=4.0)
+    args = parser.parse_args()
+
+    source = args.input.read_text()
+    original = [float(match.group(2)) for match in CLEARANCE.finditer(source)]
+    if not original:
+        raise RuntimeError(f"No clearance rules found in {args.input}")
+
+    def scale(match: re.Match[str]) -> str:
+        value = float(match.group(2)) * args.factor
+        rendered = str(int(value)) if value.is_integer() else f"{value:g}"
+        return match.group(1) + rendered
+
+    converted, count = CLEARANCE.subn(scale, source)
+    scaled = [float(match.group(2)) for match in CLEARANCE.finditer(converted)]
+    assert count == len(original) == len(scaled)
+    assert all(after == before * args.factor
+               for before, after in zip(original, scaled, strict=True))
+    # A conversion must never touch the board geometry or trace-width rules.
+    assert source.count("(width ") == converted.count("(width ")
+    assert source.count("(polygon ") == converted.count("(polygon ")
+    args.output.write_text(converted)
+    print(f"Scaled {count} clearance rules by {args.factor:g}x")
+    print(f"Saved {args.output}")
+
+
+if __name__ == "__main__":
+    main()
@@ -0,0 +1,94 @@
+#!/usr/bin/env python3
+"""Install deterministic 0.8-mm-pitch dogbone escapes for connected Ti375 balls."""
+
+from __future__ import annotations
+
+import argparse
+import shutil
+from pathlib import Path
+
+import pcbnew
+
+
+ROOT = Path(__file__).resolve().parents[1]
+DEFAULT_INPUT = ROOT / "hardware" / "board.kicad_pcb"
+DEFAULT_OUTPUT = ROOT / "hardware" / "board_prerouted.kicad_pcb"
+POWER_NETS = {
+    "GND", "VCC0V95", "VCC1V8", "VCC3V3", "VCC3V0_DIG",
+}
+
+
+def mm(value: float) -> int:
+    return pcbnew.FromMM(value)
+
+
+def add_segment(board: pcbnew.BOARD, pad: pcbnew.PAD,
+                end: pcbnew.VECTOR2I, width_mm: float) -> None:
+    track = pcbnew.PCB_TRACK(board)
+    track.SetStart(pad.GetPosition())
+    track.SetEnd(end)
+    track.SetWidth(mm(width_mm))
+    track.SetLayer(pcbnew.F_Cu)
+    track.SetNet(pad.GetNet())
+    track.SetLocked(True)
+    board.Add(track)
+
+
+def add_via(board: pcbnew.BOARD, pad: pcbnew.PAD,
+            position: pcbnew.VECTOR2I) -> None:
+    via = pcbnew.PCB_VIA(board)
+    via.SetPosition(position)
+    via.SetWidth(mm(0.45))
+    via.SetDrill(mm(0.225))
+    via.SetLayerPair(pcbnew.F_Cu, pcbnew.B_Cu)
+    via.SetNet(pad.GetNet())
+    via.SetLocked(True)
+    board.Add(via)
+
+
+def main() -> None:
+    parser = argparse.ArgumentParser()
+    parser.add_argument("input", nargs="?", type=Path, default=DEFAULT_INPUT)
+    parser.add_argument("output", nargs="?", type=Path, default=DEFAULT_OUTPUT)
+    args = parser.parse_args()
+
+    board = pcbnew.LoadBoard(str(args.input))
+    fpga = board.FindFootprintByReference("U1")
+    if fpga is None:
+        raise RuntimeError("U1 Ti375 footprint is missing")
+    centre = fpga.GetPosition()
+    occupied: set[tuple[int, int]] = set()
+    counts = {"power": 0, "signal": 0}
+
+    for pad in fpga.Pads():
+        if not pad.GetNetname():
+            continue
+        position = pad.GetPosition()
+        # Move each ball toward its package quadrant.  Centre-row/column balls
+        # use the positive direction, leaving a full 0.8-mm via grid without
+        # duplicated interstitial locations.
+        dx = 0.4 if position.x >= centre.x else -0.4
+        dy = 0.4 if position.y >= centre.y else -0.4
+        via_position = pcbnew.VECTOR2I(position.x + mm(dx), position.y + mm(dy))
+        key = (via_position.x, via_position.y)
+        if key in occupied:
+            raise RuntimeError(f"Duplicate dogbone via at {key} for U1.{pad.GetNumber()}")
+        occupied.add(key)
+        is_power = pad.GetNetname() in POWER_NETS
+        add_segment(board, pad, via_position, 0.15 if is_power else 0.10)
+        add_via(board, pad, via_position)
+        counts["power" if is_power else "signal"] += 1
+
+    if not pcbnew.ZONE_FILLER(board).Fill(board.Zones()):
+        raise RuntimeError("Zone fill failed after BGA fanout")
+    pcbnew.SaveBoard(str(args.output), board)
+    for suffix in (".kicad_pro", ".kicad_dru"):
+        source = args.input.with_suffix(suffix)
+        if source.exists():
+            shutil.copyfile(source, args.output.with_suffix(suffix))
+    print(f"Installed {counts['power']} power/GND and {counts['signal']} signal dogbones")
+    print(f"Saved {args.output}")
+
+
+if __name__ == "__main__":
+    main()
@@ -0,0 +1,195 @@
+#!/usr/bin/env python3
+"""Connect SMT power/ground pads locally to their intended solid planes.
+
+This deliberately does not replace power-stage routing.  It only installs
+short pad-to-via connections where a filled, same-net plane is physically
+present below the candidate via.  High-current converter loops and plane
+bridges are handled separately.
+"""
+
+from __future__ import annotations
+
+import argparse
+import math
+import shutil
+from pathlib import Path
+
+import pcbnew
+
+
+ROOT = Path(__file__).resolve().parents[1]
+DEFAULT_INPUT = ROOT / "hardware" / "board_prerouted.kicad_pcb"
+DEFAULT_OUTPUT = ROOT / "hardware" / "board_plane_stitched.kicad_pcb"
+PLANE_NETS = {
+    "GND", "SYS5", "VCC0V95", "VCC1V8", "VCC3V3", "VCC3V3_AUX",
+    "VCC3V0_CLK", "VCC3V0_DIG", "VCC3V0_RF", "VCC3V3_ANT",
+}
+VIA_DIAMETER = 0.45
+VIA_DRILL = 0.225
+CLEARANCE = 0.10
+
+
+def mm(value: float) -> int:
+    return pcbnew.FromMM(value)
+
+
+def distance_mm(a: pcbnew.VECTOR2I, b: pcbnew.VECTOR2I) -> float:
+    return math.hypot(pcbnew.ToMM(a.x - b.x), pcbnew.ToMM(a.y - b.y))
+
+
+def add_track(board: pcbnew.BOARD, pad: pcbnew.PAD,
+              end: pcbnew.VECTOR2I, width: float) -> None:
+    track = pcbnew.PCB_TRACK(board)
+    track.SetStart(pad.GetPosition())
+    track.SetEnd(end)
+    track.SetWidth(mm(width))
+    track.SetLayer(pad.GetLayer())
+    track.SetNet(pad.GetNet())
+    track.SetLocked(True)
+    board.Add(track)
+
+
+def add_via(board: pcbnew.BOARD, pad: pcbnew.PAD,
+            position: pcbnew.VECTOR2I) -> pcbnew.PCB_VIA:
+    via = pcbnew.PCB_VIA(board)
+    via.SetPosition(position)
+    via.SetWidth(mm(VIA_DIAMETER))
+    via.SetDrill(mm(VIA_DRILL))
+    via.SetLayerPair(pcbnew.F_Cu, pcbnew.B_Cu)
+    via.SetNet(pad.GetNet())
+    via.SetLocked(True)
+    board.Add(via)
+    return via
+
+
+def plane_at(zones_by_net: dict[str, list[pcbnew.ZONE]], net: str,
+             position: pcbnew.VECTOR2I) -> bool:
+    return any(zone.HitTestFilledArea(zone.GetLayer(), position)
+               for zone in zones_by_net.get(net, ()))
+
+
+def clear_of_other_copper(position: pcbnew.VECTOR2I, net: str,
+                          pads: list[pcbnew.PAD], vias: list[pcbnew.PCB_VIA]) -> bool:
+    x, y = pcbnew.ToMM(position.x), pcbnew.ToMM(position.y)
+    margin = VIA_DIAMETER / 2 + CLEARANCE + 0.03
+    for other in pads:
+        if other.GetNetname() == net:
+            continue
+        box = other.GetBoundingBox()
+        x0, y0 = pcbnew.ToMM(box.GetX()) - margin, pcbnew.ToMM(box.GetY()) - margin
+        x1, y1 = pcbnew.ToMM(box.GetRight()) + margin, pcbnew.ToMM(box.GetBottom()) + margin
+        if x0 <= x <= x1 and y0 <= y <= y1:
+            return False
+    for other in vias:
+        minimum = (VIA_DIAMETER + pcbnew.ToMM(other.GetWidth(pcbnew.F_Cu))) / 2 + CLEARANCE
+        if distance_mm(position, other.GetPosition()) < minimum:
+            return False
+    return True
+
+
+def clear_track_path(start: pcbnew.VECTOR2I, end: pcbnew.VECTOR2I, net: str,
+                     source: pcbnew.PAD, pads: list[pcbnew.PAD], width: float) -> bool:
+    """Conservatively reject short dogbones that cross another pad bbox."""
+    margin = width / 2 + CLEARANCE + 0.02
+    for step in range(1, 12):
+        fraction = step / 12
+        sample = pcbnew.VECTOR2I(
+            round(start.x + (end.x - start.x) * fraction),
+            round(start.y + (end.y - start.y) * fraction),
+        )
+        x, y = pcbnew.ToMM(sample.x), pcbnew.ToMM(sample.y)
+        for other in pads:
+            if other is source or other.GetNetname() == net:
+                continue
+            box = other.GetBoundingBox()
+            if (pcbnew.ToMM(box.GetX()) - margin <= x <= pcbnew.ToMM(box.GetRight()) + margin and
+                    pcbnew.ToMM(box.GetY()) - margin <= y <= pcbnew.ToMM(box.GetBottom()) + margin):
+                return False
+    return True
+
+
+def candidates(pad: pcbnew.PAD, footprint: pcbnew.FOOTPRINT) -> list[pcbnew.VECTOR2I]:
+    pad_pos = pad.GetPosition()
+    fp_pos = footprint.GetPosition()
+    away = math.atan2(pad_pos.y - fp_pos.y, pad_pos.x - fp_pos.x)
+    if pad_pos == fp_pos:
+        away = 0.0
+    radius = max(pcbnew.ToMM(pad.GetSizeX()), pcbnew.ToMM(pad.GetSizeY())) / 2
+    radius += VIA_DIAMETER / 2 + CLEARANCE + 0.08
+    angles = [away]
+    for delta_deg in (30, -30, 60, -60, 90, -90, 120, -120, 150, -150, 180):
+        angles.append(away + math.radians(delta_deg))
+    result = []
+    for scale in (1.0, 1.35, 1.75):
+        for angle in angles:
+            result.append(pcbnew.VECTOR2I(
+                pad_pos.x + mm(radius * scale * math.cos(angle)),
+                pad_pos.y + mm(radius * scale * math.sin(angle)),
+            ))
+    return result
+
+
+def main() -> None:
+    parser = argparse.ArgumentParser()
+    parser.add_argument("input", nargs="?", type=Path, default=DEFAULT_INPUT)
+    parser.add_argument("output", nargs="?", type=Path, default=DEFAULT_OUTPUT)
+    args = parser.parse_args()
+
+    board = pcbnew.LoadBoard(str(args.input))
+    if not pcbnew.ZONE_FILLER(board).Fill(board.Zones()):
+        raise RuntimeError("Could not fill planes before stitching")
+
+    zones_by_net: dict[str, list[pcbnew.ZONE]] = {}
+    for zone in board.Zones():
+        if not zone.GetIsRuleArea() and zone.GetNetname() in PLANE_NETS:
+            zones_by_net.setdefault(zone.GetNetname(), []).append(zone)
+
+    all_pads = [pad for fp in board.GetFootprints() for pad in fp.Pads()]
+    all_vias = [item for item in board.GetTracks() if isinstance(item, pcbnew.PCB_VIA)]
+    connected: dict[str, int] = {}
+    skipped: dict[str, int] = {}
+
+    for fp in board.GetFootprints():
+        if fp.GetReference() == "U1":
+            continue
+        for pad in fp.Pads():
+            net = pad.GetNetname()
+            if net not in PLANE_NETS or pad.GetAttribute() != pcbnew.PAD_ATTRIB_SMD:
+                continue
+            chosen = None
+            pad_min = min(pcbnew.ToMM(pad.GetSizeX()), pcbnew.ToMM(pad.GetSizeY()))
+            width = max(0.15, min(0.30, pad_min * 0.65))
+            for candidate in candidates(pad, fp):
+                x, y = pcbnew.ToMM(candidate.x), pcbnew.ToMM(candidate.y)
+                if not (20.5 < x < 174.5 and 20.5 < y < 109.5):
+                    continue
+                if not plane_at(zones_by_net, net, candidate):
+                    continue
+                if not clear_of_other_copper(candidate, net, all_pads, all_vias):
+                    continue
+                if not clear_track_path(pad.GetPosition(), candidate, net, pad, all_pads, width):
+                    continue
+                chosen = candidate
+                break
+            if chosen is None:
+                skipped[net] = skipped.get(net, 0) + 1
+                continue
+            add_track(board, pad, chosen, width)
+            all_vias.append(add_via(board, pad, chosen))
+            connected[net] = connected.get(net, 0) + 1
+
+    if not pcbnew.ZONE_FILLER(board).Fill(board.Zones()):
+        raise RuntimeError("Could not refill planes after stitching")
+    pcbnew.SaveBoard(str(args.output), board)
+    for suffix in (".kicad_pro", ".kicad_dru"):
+        source = args.input.with_suffix(suffix)
+        if source.exists():
+            shutil.copyfile(source, args.output.with_suffix(suffix))
+    print("Plane connections:", ", ".join(f"{n}={k}" for n, k in sorted(connected.items())))
+    print("Pads without a local same-net plane:",
+          ", ".join(f"{n}={k}" for n, k in sorted(skipped.items())))
+    print(f"Saved {args.output}")
+
+
+if __name__ == "__main__":
+    main()
				`@@ -0,0 +1 @@`
				{"success":true,"code":200,"message":null,"errorCode":null,"data":[{"impedanceConfigCoverlayId":560413206669881346,"systemCopperThickness":1.00,"coatingAboveSubstrate":1.00,"coatingAboveTrace":0.60,"coatingBetweenTraces":1.00,"layerType":1,"baseCopperThickness":0.33},{"impedanceConfigCoverlayId":560413206669881349,"systemCopperThickness":1.00,"coatingAboveSubstrate":1.00,"coatingAboveTrace":0.60,"coatingBetweenTraces":1.00,"layerType":1,"baseCopperThickness":0.50},{"impedanceConfigCoverlayId":560413206669881352,"systemCopperThickness":0.50,"coatingAboveSubstrate":1.00,"coatingAboveTrace":0.60,"coatingBetweenTraces":1.00,"layerType":2,"baseCopperThickness":0.50},{"impedanceConfigCoverlayId":560413206669881355,"systemCopperThickness":1.50,"coatingAboveSubstrate":1.00,"coatingAboveTrace":0.60,"coatingBetweenTraces":1.00,"layerType":1,"baseCopperThickness":1.00},{"impedanceConfigCoverlayId":560413206669881358,"systemCopperThickness":1.00,"coatingAboveSubstrate":1.00,"coatingAboveTrace":0.60,"coatingBetweenTraces":1.00,"layerType":2,"baseCopperThickness":1.00},{"impedanceConfigCoverlayId":560413206669881361,"systemCopperThickness":2.00,"coatingAboveSubstrate":1.20,"coatingAboveTrace":0.80,"coatingBetweenTraces":1.20,"layerType":1,"baseCopperThickness":1.50},{"impedanceConfigCoverlayId":560413206669881364,"systemCopperThickness":1.50,"coatingAboveSubstrate":1.00,"coatingAboveTrace":0.60,"coatingBetweenTraces":1.00,"layerType":2,"baseCopperThickness":1.50},{"impedanceConfigCoverlayId":560413206669881367,"systemCopperThickness":2.50,"coatingAboveSubstrate":1.20,"coatingAboveTrace":0.80,"coatingBetweenTraces":1.20,"layerType":1,"baseCopperThickness":2.00},{"impedanceConfigCoverlayId":560413206669881370,"systemCopperThickness":2.00,"coatingAboveSubstrate":1.20,"coatingAboveTrace":0.80,"coatingBetweenTraces":1.20,"layerType":2,"baseCopperThickness":2.00}]}