(version 1) # The edge-launch SMA copper must reach the routed board edge by construction. (rule "J2 edge-launch lands" (condition "A.Reference == 'J2' || B.Reference == 'J2'") (constraint edge_clearance (min -0.01mm))) # The manufacturer USB-C locating holes are 0.194 mm from grounded shell # lands. This exception is internal to the qualified connector footprint. (rule "USB-C locating-hole clearance" (condition "A.Reference == 'J1' && B.Reference == 'J1'") (constraint hole_clearance (min 0.19mm))) # RZV0024A is an ultra-dense high-current package. Its adjusted corner lands # and thermal zones meet the selected JLCPCB 0.10-mm copper rule. (rule "TPS6287B RZV internal clearance" (condition "A.Reference == 'U13' && B.Reference == 'U13'") (constraint clearance (min 0.10mm))) # A 0.45-mm dogbone via at the centre of four 0.8-mm-pitch BGA lands has # 0.1407-mm geometric clearance. This local rule is still well above the # selected fabricator's 0.10-mm copper minimum; clocks retain 0.15 mm outside # the U1 escape field. (rule "Ti375 0.8-mm BGA dogbone clearance" (condition "A.Reference == 'U1' || B.Reference == 'U1'") (constraint clearance (min 0.14mm))) # JLC08161H-3313 L1/L2 geometry. Net-class widths are routing defaults only; # these rules make the controlled-impedance geometries actual DRC limits. (rule "GNSS 50-ohm CPWG geometry" (condition "A.NetClass == 'RF50_CPWG'") (constraint track_width (min 0.164mm) (opt 0.164mm) (max 0.164mm))) (rule "GNSS RF stays on top layer" (condition "A.NetClass == 'RF50_CPWG' && A.Type == 'Track' && A.Layer != 'F.Cu'") (constraint disallow track)) (rule "USB2 90-ohm differential geometry" (condition "A.NetClass == 'USB90_DIFF'") (constraint track_width (min 0.135mm) (opt 0.135mm) (max 0.135mm))) (rule "USB2 coupled gap" (condition "A.NetClass == 'USB90_DIFF' && AB.isCoupledDiffPair()") (constraint diff_pair_gap (min 0.15mm) (opt 0.15mm) (max 0.15mm))) (rule "Clock trunk width outside Ti375 escape" (condition "A.NetClass == 'CLOCK' && A.Type == 'Track' && !A.insideCourtyard('U1')") (constraint track_width (min 0.15mm)))