address,value_hex,default_hex,changed,purpose
0x0,0xBEA71619,0xBEA41603,yes,"MIXIN_HI, both LNAs disabled, 23.4 MHz 5th-order LPF, 36 MHz mixer pole"
0x1,0x20550288,0x20550288,no,Preserve MAX2771 documented reset/default value
0x2,0x0EAFA1DC,0x0EAFA1DC,no,Preserve MAX2771 documented reset/default value
0x3,0x698C0008,0x698C0008,no,Integer-N L1 PLL
0x4,0x00C08080,0x00C00080,yes,"NDIV=1540, RDIV=16: 16.368 MHz / 16 * 1540 = 1575.42 MHz"
0x5,0x08000070,0x08000070,no,Preserve MAX2771 documented reset/default value
0x6,0x08000000,0x08000000,no,Preserve MAX2771 documented reset/default value
0x7,0x110061B2,0x010061B2,yes,External 40 MHz ADC sampling clock on ADC_CLKIN
0x8,0x01E0F401,0x01E0F401,no,Preserve MAX2771 documented reset/default value
0x9,0x00C00002,0x00C00002,no,Preserve MAX2771 documented reset/default value
0xA,0x010061B4,0x010061B0,yes,Route ADC sampling clock to CLKOUT for source-synchronous FPGA capture