onur
1218c33aa4
Four RF points came back from review. Two were real gaps, two were already
sound but undocumented, and one premise was stale.
Real gap 1 - nothing told the fab this is a controlled-impedance board.
docs/FABRICATION.md now carries the stackup (JLC08161H-3313, layer by layer
with dielectric heights and Er), the two impedance targets (RF50_CPWG 50 ohm at
0.164/0.200 on F.Cu over L2, USB90_DIFF 90 ohm at 0.135/0.150), the process
minima, and an explicit request that the vendor confirm the widths with their
own field solver. It records that JLC models this as
CoatedCoplanarWaveguideWithLowerGnd1B assuming 1.6 mil finished outer copper,
0.6 mil soldermask at Er 3.8 and top width = base - 0.7 mil, and that copper
thickness alone moves this geometry by more than 10 ohm - which is why the
number has to be fixed by the vendor's model rather than ours. It also states
the decision rule: 44 ohm is still 24 dB return loss and not the worst term in
the chain, so the geometry should not be changed unless the vendor reports
below that.
Real gap 2 - the active-antenna requirement was implied everywhere but never
quantified. hardware/README.md and docs/INTERFACES.md now state it plainly:
with both internal LNAs off the mixer input is the first active stage at
10.3 dB NF, so a ~25 dB active antenna gives ~1.65 dB system NF while a passive
antenna puts it above 12 dB and the receiver is unusable. The same section now
explains why the SAW is not optional either.
Documented, not changed - the launch relief. Its ~37 ohm / 30 dB figure is a 2D
quasi-static estimate of a genuinely 3D transition (connector, board edge, pad
overhang) and is now labelled as such, with 3D EM or VNA named as what would
settle it. The unrelieved case was 10.7 ohm / 12 dB, so the improvement holds
regardless of the exact figure.
Documented, not changed - the bias choke. Its 2.1 GHz SRF sits above 1575 MHz,
so the choke is still inductive and the proximity raises |Z| from 554 to about
1270 ohm, which helps a bias tee rather than hurting it. Swept +/-10% on both L
and SRF: |Z| stays above 900 ohm, return loss above 30 dB, insertion loss below
0.003 dB.
Stale premise - the review tied the impedance to "the inconsistent stackup".
That inconsistency was fixed in 791ca5c, and the F.Cu-to-L2 construction that
sets the RF impedance (3313 prepreg, 0.0994 mm, Er 4.1) was in fact identical
in both the old ten-layer and the current eight-layer stacks, so the CPWG
geometry never actually moved.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d
1.9 KiB
1.9 KiB
Türetilmiş tasarım verileri
Bu klasördeki CSV/ISF dosyaları elle düzenlenecek ana tasarım kaynağı değildir;
scripts/design_data.py ve scripts/generate_design_tables.py üzerinden tekrar
üretilir.
Okunabilir tasarım dokümanları:
COMPONENT_SELECTION.md: ana IC seçimi, besleme ve kapasite sınırları.INTERFACES.md: RF, MAX2771, SafeSPI, QSPI, FTDI/USB ve test noktaları.FPGA_PINOUT.md: FPGA ball/bank/gerilim ve dört PMOD eşlemesi.POWER_TREE.md: giriş power-path, rail sıralaması, supervisor ve reset.
| Dosya | Açıklama |
|---|---|
ti375_c529_package.csv |
Efinity 2025.2 Ti375C529 paket veritabanından çıkarılmış 529 ball kaydı |
ti375_c529_package.meta.json |
Paket verisinin kaynak/sürüm metadatası |
ti375_pinout.csv |
Kartta kullanılan sinyal, ball, bank, VCCIO, I/O standardı ve konnektör eşlemesi |
unused_gpio_inventory.csv |
Kullanılan ve fiziksel olarak boş bırakılan fabric GPIO envanteri |
ti375_pin_constraints.isf |
HDL/Efinity tarafı için pin ve I/O standardı constraintleri |
max2771_registers.csv |
Kartın MAX2771 başlangıç register görüntüsü |
Yeniden üretmek için:
python3 scripts/generate_design_tables.py
Script aşağıdaki koşulları doğrular:
- Paket kaynağında tam 529 benzersiz ball bulunması.
- Dedicated TCK/TMS/TDI/TDO, CRESET_N, CDONE ve JTAG_VCCIO_SEL adları.
- Seçilen bankın istenen 3.3 V, 3.0 V veya 1.8 V I/O standardını desteklemesi.
- PMOD tahsislerinde konfigürasyon/PLL/clock özel fonksiyonlarının yanlışlıkla kullanılmaması.
- MAX2771 ve SCH16T için ayrılmış pinlerle PMOD çakışması olmaması.
Hard JTAG yalnızca kart üzerindeki FT4232H interface 1 üzerinden erişilir;
harici ARM/JTAG headerı yoktur. FPGA_CRESET_N, açık-drenç power/FTDI/harici
reset fan-in'i olarak belgelenmiştir.