onur
791ca5c9fa
The routed deliverable has always been eight layers (JLC08161H-3313), but generate_pcb.py still emitted ten and hardware/board.kicad_pcb was itself still a ten-layer board. Source and generator agreed with each other and disagreed with what is actually being fabricated, so running the documented regeneration flow would have silently replaced the eight-layer design with a conflicting ten-layer one and destroyed the routing. generate_pcb.py now builds the real stack: SetCopperLayerCount(8), no L8_PWR / L9_SIG, and the STACKUP string taken verbatim from board_routed.kicad_pcb - the two are now byte-identical. Silkscreen reads JLC08161H-3313 8L instead of JLC10161H 10L, and the title block follows. The zone layout follows the same correction. With only one dedicated power plane there is no third plane for the two big FPGA I/O rails, so they are carried as islands on the routing layers that have room: VCC1V8 on L6 and VCC3V3 on B.Cu, replacing the ten-layer arrangement of a VCC3V3 background on L8 and a board-wide GND pour on B.Cu. The regenerated board now reproduces the routed board's 26 copper zones exactly (the 27th, the F.Cu RF ground pour, is added later by finalize_routing). Also drops the In7_Cu/In8_Cu remnants from finalize_routing's RF_NO_DIGITAL layer set and route_local_power's RF_REGION_LAYERS - those layers do not exist on this board, so they were dead bits in a layer mask - and corrects the JLC10161H reference in board.kicad_dru. The placement check now reports 21 isolated_copper warnings rather than 17. That is expected and explained in README.md: on an unrouted board the I/O-rail islands on L6 and B.Cu have nothing joining them yet. The routed board still reports zero. Verified: regenerated board is 8 layers with a stackup identical to the routed board, 312 footprints (311 + R108), TEMP keepouts at their corrected extents. design_data assertions pass, ERC 0/0, routed board still 0 DRC violations, 0 unconnected, every net one copper group, parity unchanged at 402. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d
85 lines
4.5 KiB
Plaintext
85 lines
4.5 KiB
Plaintext
(version 1)
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# The edge-launch SMA copper must reach the routed board edge by construction.
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(rule "J2 edge-launch lands"
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(condition "A.Reference == 'J2' || B.Reference == 'J2'")
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(constraint edge_clearance (min -0.01mm)))
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# The manufacturer USB-C locating holes are 0.194 mm from grounded shell
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# lands. This exception is internal to the qualified connector footprint.
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(rule "USB-C locating-hole clearance"
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(condition "A.Reference == 'J1' && B.Reference == 'J1'")
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(constraint hole_clearance (min 0.19mm)))
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# RZV0024A is an ultra-dense high-current package. Its adjusted corner lands
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# and thermal zones meet the selected JLCPCB 0.10-mm copper rule.
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(rule "TPS6287B RZV internal clearance"
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(condition "A.Reference == 'U13' && B.Reference == 'U13'")
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(constraint clearance (min 0.10mm)))
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# Inside the Ti375 escape field the 0.8-mm ball pitch fixes the geometry: a
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# 0.45-mm dogbone via between four lands leaves 0.1407 mm, and a 0.12-mm trace
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# threading between two lands leaves 0.14 mm only if it stays exactly centred.
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# This field therefore runs at the fabricator's 0.10-mm copper minimum, which
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# is what the Default class uses across the rest of the board anyway. The rule
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# only fires when one of the two objects belongs to U1, so it relaxes copper
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# against the balls and nothing else: two tracks crossing the field still owe
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# each other their own net classes' clearance, CLOCK's 0.15 mm included.
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(rule "Ti375 0.8-mm BGA escape clearance"
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(condition "A.Reference == 'U1' || B.Reference == 'U1'")
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(constraint clearance (min 0.10mm)))
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# JLC08161H-3313 L1/L2 geometry (3313 prepreg, 0.0994 mm, er 4.1). Net-class widths are routing defaults only;
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# these rules make the controlled-impedance geometries actual DRC limits.
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(rule "GNSS 50-ohm CPWG geometry"
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(condition "A.NetClass == 'RF50_CPWG'")
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(constraint track_width (min 0.164mm) (opt 0.164mm) (max 0.164mm)))
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(rule "GNSS RF stays on top layer"
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(condition "A.NetClass == 'RF50_CPWG' && A.Type == 'Track' && A.Layer != 'F.Cu'")
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(constraint disallow track))
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(rule "USB2 90-ohm differential geometry"
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(condition "A.NetClass == 'USB90_DIFF'")
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(constraint track_width (min 0.135mm) (opt 0.135mm) (max 0.135mm)))
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# The TPD2EUSB30A clamp is a SOT-23 whose ground pad sits between its two
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# channel pads, so the pair has to open up for about 1.5 mm to pass it. The
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# 0.90-mm coupled limit still applies over the whole rest of the run.
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(rule "USB2 coupled gap"
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(condition "A.NetClass == 'USB90_DIFF' && AB.isCoupledDiffPair() && !A.intersectsArea('USB_ESD_BREAKOUT')")
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(constraint diff_pair_gap (min 0.15mm) (opt 0.15mm) (max 0.90mm)))
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# The 50-ohm line owns the band it runs in on every layer under F.Cu, so no
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# digital route can pass beneath or immediately beside it. Ground stitching
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# and the MAX2771's own supply drops still have to reach it, so the disallow is
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# scoped to the signal classes rather than made a plain keepout. The RF line
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# itself is on F.Cu, which the area does not cover, and the L2/L7 GND planes
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# stay solid because nothing routes on them at all -- the actual RF return path
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# is guaranteed by those planes, not by this area.
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#
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# The area covers y <= 43.7, which is the same corridor generate_pcb.py
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# reserves as TEMP_RF_LINE and clears the RF copper (y <= 42.6) by 1.1 mm. It
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# deliberately stops short of the MAX2771's digital pin rows at y = 44.5 ..
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# 47.4: those pins have to reach the FPGA, and with the area extended over them
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# every one of them was forced onto F.Cu alone, which does not fit.
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(rule "No digital copper under the GNSS front end"
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(condition "A.intersectsArea('RF_NO_DIGITAL') && A.NetClass != 'POWER'")
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(constraint disallow track via))
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(rule "Clock trunk width outside Ti375 escape"
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(condition "A.NetClass == 'CLOCK' && A.Type == 'Track' && !A.insideCourtyard('U1')")
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(constraint track_width (min 0.15mm)))
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# A 0.8-mm ball pitch leaves a 0.35-mm channel between two adjacent 0.45-mm
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# dogbone vias. A 0.10-mm trace fits that channel at the escape field's
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# 0.10-mm copper minimum but not at CLOCK's 0.15 mm, so a clock ball could not
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# be escaped from the package at all. Inside the field -- and only where BOTH
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# objects are inside it -- copper therefore runs at the same 0.10 mm the rest
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# of this field already uses. The clock trunk keeps its 0.15 mm the moment it
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# leaves U1's courtyard, which is where coupling to neighbours actually costs
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# something.
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(rule "Ti375 escape field copper clearance"
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(condition "A.insideCourtyard('U1') && B.insideCourtyard('U1')")
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(constraint clearance (min 0.10mm)))
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