68 lines
3.3 KiB
Markdown
68 lines
3.3 KiB
Markdown
# Navigation hardware/software partition
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The measured partition keeps sample-rate work in the tracking IP and performs
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I/NAV decoding in software. No result in this milestone justifies placing a
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soft-decision Viterbi decoder or navigation database in RTL.
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## Tracking-IP output contract
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The tracking IP uses E1C VE/E/P/L/VL for shared carrier/code loops, C/N0, and
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BOC-aware lock monitoring. A separate E1B correlator branch consumes the same
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sample-by-sample NCO phases. One navigation record is emitted from that branch
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for every 4 ms E1B primary-code epoch:
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| Field | Proposed representation | Meaning |
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| --- | --- | --- |
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| PRN/channel | unsigned integer | Logical satellite and component |
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| start/end timestamp | 64-bit sample counters | Continuous receiver time association |
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| Prompt I/Q | signed fixed-point accumulators | Unreduced coherent evidence |
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| carrier phase/frequency | NCO state/measurement words | Reprocessing and phase diagnostics |
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| code phase | unsigned fixed-point chips | Code-time association |
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| C/N0 | fixed-point dB-Hz or invalid | Monitoring only |
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| carrier/code lock | bits | E1C pilot-derived decoder validity gate |
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| lock metric valid | bit | BOC smoothing/calibration window is valid |
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| BOC main/side metrics | fixed-point monitor words | false-lock diagnosis |
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| cycle slip/discontinuity | bits | Immediate symbol/page synchronizer reset |
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| valid | bit | Transaction validity |
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The interface should use an AXI-Stream-like `valid/ready` transaction. A FIFO
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must absorb software service latency; backpressure cannot be allowed to stop the
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sample-rate tracking datapath. At 250 records/s/channel, even 36 active E1B
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channels produce only 9000 records/s, so a memory-mapped DMA ring is sufficient.
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E1C secondary-code synchronization can remain software-assisted initially: a
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bounded Prompt buffer is searched for secondary phase and residual carrier
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frequency, then the phase is written to tracking-channel state. Continuous
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secondary wipeoff and the E1C/E1B correlator branches remain sample-rate RTL.
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## Software decoder
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Software retains floating `numpy.float64` prompt/soft values in the reference
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model and performs:
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```text
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prompt axis and symbol synchronization
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-> page synchronization and polarity resolution
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-> 30x8 deinterleaving
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-> soft Viterbi decode
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-> vertical-page assembly and CRC-24Q
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-> typed word parsing
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-> atomic IODnav ephemeris assembly
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-> GST/clock/health navigation database
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```
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This split keeps policy-rich, low-rate state machines inspectable and updateable.
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The saved `prompt_epochs.npz` files are the exact boundary between future RTL
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tracking and the software decoder. HDL verification shall replay the same RF
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vector, compare each tracking epoch with the bit-true model, then feed the RTL
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prompt records into this decoder without SignalSim truth.
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## Conditions that could justify later hardware offload
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Only measured CPU load, power, or startup-latency failure should trigger an
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offload study. Plausible granular offloads are symbol accumulate-and-dump,
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deinterleaver address generation, or a shared Viterbi accelerator. CRC, word
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parsing, ephemeris consistency, time rollover handling, and the navigation store
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remain better software candidates because their throughput is negligible and
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their standards/policy behavior is state-rich.
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