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fix(efinity): stream build progress without buffering

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onur cayan
2026-08-13 02:26:42 +03:00
parent 3cc609a350
commit 8850ece2a4
2 changed files with 7 additions and 5 deletions
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targets/fpga/ti375c529/README.md
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@@ -31,6 +31,8 @@ programming targets require a complete Efinity installation containing
elaboration with a direct diagnostic when it is absent.
Concurrent Ti375 `map` or `bitstream` invocations are rejected because they
share generated FIRRTL, SystemVerilog, and Efinity work directories.
Efinity is run with unbuffered Python output so `map`, `pnr`, and `pgm`
progress remains visible in the terminal and `out/logs/full.log`.
Programming auto-selects the connected Ti375 development kit. If more than
one compatible FTDI device is attached, run `make FPGA_BOARD=ti375c529