max2771 spi liens has been added.

hardware/generated/genesys2-soc-verilog/AsyncResetSynchronizerPrimitiveShiftReg_d3_i0.sv

@@ -0,0 +1,41 @@
+// Generated by CIRCT firtool-1.151.0
+module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0(
+  input  clock,
+         reset,
+         io_d,
+  output io_q
+);
+
+  reg sync_0;
+  reg sync_1;
+  reg sync_2;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      sync_0 <= 1'h0;
+      sync_1 <= 1'h0;
+      sync_2 <= 1'h0;
+    end
+    else begin
+      sync_0 <= sync_1;
+      sync_1 <= sync_2;
+      sync_2 <= io_d;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    initial begin
+      if (reset) begin
+        sync_0 = 1'h0;
+        sync_1 = 1'h0;
+        sync_2 = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_q = sync_0;
+endmodule
+