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max2771 spi liens has been added.

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onur
2026-08-06 22:14:52 +03:00
parent 847523078b
commit b4920d31e3
288 changed files with 214687 additions and 18389 deletions
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.Xil/genesys2_rocket_top_propImpl.xdc
+5 -5
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@@ -1,8 +1,8 @@
set_property SRC_FILE_INFO {cfile:/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_rocket.xdc id:1} [current_design]
set_property SRC_FILE_INFO {cfile:/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc id:2} [current_design]
set_property SRC_FILE_INFO {cfile:/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc id:3} [current_design]
set_property SRC_FILE_INFO {cfile:/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc id:4} [current_design]
set_property SRC_FILE_INFO {cfile:/home/onur/Desktop/rocket/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc id:5} [current_design]
set_property SRC_FILE_INFO {cfile:/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_rocket.xdc id:1} [current_design]
set_property SRC_FILE_INFO {cfile:/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc id:2} [current_design]
set_property SRC_FILE_INFO {cfile:/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc id:3} [current_design]
set_property SRC_FILE_INFO {cfile:/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_pmod_pps.xdc id:4} [current_design]
set_property SRC_FILE_INFO {cfile:/home/ankaoc/Desktop/tmp/gps/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc rfile:../hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc id:5} [current_design]
set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD12 [get_ports sysclk_p]
set_property src_info {type:XDC file:1 line:5 export:INPUT save:INPUT read:READ} [current_design]
README.md
+46
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@@ -240,6 +240,52 @@ RF_INPUT_MODE=generated Dahili RF clock uretilir, RF data sifira baglanir.
RF_INPUT_MODE=ethernet Kart bazli raw-Ethernet RF streamer path'i.
```
## MAX2771 EVKIT PMOD Baglantisi
MAX2771, mevcut standart PMOD SPI'dan ayri bir uc-telli seri IP ve MMIO
peripheralidir. MAX2771 IP tabani `0x10016000`, mevcut PMOD SPI tabani ise
`0x10015000` adresindedir. Iki arayuzun portlari ve kart pinleri birbirinden
bagimsizdir.
Genesys2 icin MAX2771 EVKIT, PMOD `JB` grubuna baglanir:
| MAX2771 sinyali | FPGA yonu | Genesys2 PMOD | FPGA pini | Elektrik standardi |
|---|---|---|---|---|
| `SCLK` | cikis | `JB2` | `V30` | LVCMOS33 |
| `CSN` | cikis | `JB3` | `V25` | LVCMOS33 |
| `SDATA` | yazmada cikis, okumada giris | `JB4` | `W26` | LVCMOS33 |
Okuma komutunda FPGA, R/W bitinden sonraki turnaround baslangicinda `SDATA`
surucusunu high-Z yapar ve ayni `JB4` pinini giris olarak ornekler. Yazmada
ayni pin cikis olarak kullanilir. EVKIT ve kart GND hatlari ortaklanmalidir.
VCU118 icin ayrilan bos PMOD0/J52 pinleri:
| MAX2771 sinyali | FPGA yonu | VCU118 PMOD | Header pini | FPGA pini | FPGA I/O standardi |
|---|---|---|---|---|---|
| `SCLK` | cikis | `PMOD0_5` | `J52.4` | `AU16` | LVCMOS18 |
| `CSN` | cikis | `PMOD0_6` | `J52.6` | `AT15` | LVCMOS18 |
| `SDATA` | yazmada cikis, okumada giris | `PMOD0_7` | `J52.8` | `AT16` | LVCMOS18 |
VCU118'in U41 level shifter'i PMOD header tarafini 3.3 V'a cevirir. Mevcut
standart PMOD SPI pinleri degistirilmemistir:
| Kart | Standart PMOD SPI CSN/MOSI/MISO/SCLK | MAX2771 CSN/SDATA/SCLK |
|---|---|---|
| Genesys2 | `JC1/JC2/JC3/JC4` | `JB3/JB4/JB2` |
| VCU118 | `J53.1/J53.3/J53.5/J53.7` | `J52.6/J52.8/J52.4` |
MAX2771 register varsayilanlarini yazip tek-hat `SDATA` uzerinden geri okuyarak
dogrulayan bare-metal uygulama:
```sh
make -C targets/fpga/genesys2 software APP=max2771_spi_test
```
Test MAX2771 register `0x0`-`0xA` icerigini veri sayfasindaki degerlerle
degistirir. EVKIT uzerindeki MAX32625 kontrolcusunun seri hatlari test boyunca
high-Z olmali ve EVKIT GUI ayni anda kullanilmamalidir.
Top-level FPGA wrapper'lar elle yazilmaz; `targets/fpga/*/tools/gen_*_wrapper.py`
scriptleri tarafindan uretilir. Bu yuzden RF secimi RTL `ifdef` ile degil,
generator parametresi ile yapilir. `make rtl` ve Vivado `build.tcl` ayni
clockInfo.txt
+2 -2
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@@ -1,7 +1,7 @@
-------------------------------------
| Tool Version : Vivado v.2025.2
| Date : Sat Jul 11 19:56:30 2026
| Host : onur
| Date : Thu Aug 6 21:30:24 2026
| Host : ankalab04
| Design : design_1
| Device : xc7k325t-ffg900-2--
-------------------------------------
hardware/README.md
+4
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@@ -35,6 +35,10 @@ fpga/vcu118/rtl/
fpga/vcu118/constraints/
VCU118 XDC constraints.
ip/max2771_spi/
Dedicated MAX2771 48-clock three-wire SPI engine, timing documentation, and
self-checking Questa testbench. This is separate from generic PMOD SPI.
sim/asic/rocket/
ASIC testbench, behavioral models, and wave.do.
hardware/fpga/genesys2/constraints/genesys2_max2771_spi.xdc
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@@ -0,0 +1,14 @@
## MAX2771 dedicated three-wire serial interface on Genesys 2 PMOD JB.
## This interface uses JB2 through JB4; JB1 is not used by this IP.
##
## max2771_spi_sclk JB2
## max2771_spi_csn JB3
## max2771_spi_sdata JB4 (bidirectional)
set_property PACKAGE_PIN V30 [get_ports max2771_spi_sclk]
set_property PACKAGE_PIN V25 [get_ports max2771_spi_csn]
set_property PACKAGE_PIN W26 [get_ports max2771_spi_sdata]
set_property IOSTANDARD LVCMOS33 [get_ports {max2771_spi_sclk max2771_spi_csn max2771_spi_sdata}]
set_property DRIVE 8 [get_ports {max2771_spi_sclk max2771_spi_csn max2771_spi_sdata}]
set_property SLEW SLOW [get_ports {max2771_spi_sclk max2771_spi_csn max2771_spi_sdata}]
hardware/fpga/vcu118/constraints/vcu118_max2771_spi.xdc
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@@ -0,0 +1,15 @@
## MAX2771 dedicated three-wire serial interface on unused PMOD0/J52 pins.
## PMOD0_0..4 remain assigned to GPS RF. U41 level-shifts the connector's
## 3.3 V signals to the FPGA bank's 1.8 V I/O.
##
## max2771_spi_sclk PMOD0_5 J52.4
## max2771_spi_csn PMOD0_6 J52.6
## max2771_spi_sdata PMOD0_7 J52.8 (bidirectional)
set_property PACKAGE_PIN AU16 [get_ports max2771_spi_sclk]
set_property PACKAGE_PIN AT15 [get_ports max2771_spi_csn]
set_property PACKAGE_PIN AT16 [get_ports max2771_spi_sdata]
set_property IOSTANDARD LVCMOS18 [get_ports {max2771_spi_sclk max2771_spi_csn max2771_spi_sdata}]
set_property DRIVE 8 [get_ports {max2771_spi_sclk max2771_spi_csn max2771_spi_sdata}]
set_property SLEW SLOW [get_ports {max2771_spi_sclk max2771_spi_csn max2771_spi_sdata}]
hardware/generated/genesys2-soc-verilog/AMOALU.sv
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@@ -0,0 +1,32 @@
// Generated by CIRCT firtool-1.151.0
module AMOALU(
input [7:0] io_mask,
input [4:0] io_cmd,
input [63:0] io_lhs,
io_rhs,
output [63:0] io_out_unmasked
);
wire _logic_xor_T_1 = io_cmd == 5'hA;
wire logic_and = _logic_xor_T_1 | io_cmd == 5'hB;
wire logic_xor = io_cmd == 5'h9 | _logic_xor_T_1;
wire [63:0] adder_out_mask = {32'hFFFFFFFF, io_mask[3], 31'h7FFFFFFF};
assign io_out_unmasked =
io_cmd == 5'h8
? (io_lhs & adder_out_mask) + (io_rhs & adder_out_mask)
: logic_and | logic_xor
? (logic_and ? io_lhs & io_rhs : 64'h0) | (logic_xor ? io_lhs ^ io_rhs : 64'h0)
: ((io_mask[4]
? (io_lhs[63] == io_rhs[63]
? io_lhs[63:32] < io_rhs[63:32] | io_lhs[63:32] == io_rhs[63:32]
& io_lhs[31:0] < io_rhs[31:0]
: io_cmd[1] ? io_rhs[63] : io_lhs[63])
: io_lhs[31] == io_rhs[31]
? io_lhs[31:0] < io_rhs[31:0]
: io_cmd[1] ? io_rhs[31] : io_lhs[31])
? io_cmd == 5'hC | io_cmd == 5'hE
: io_cmd == 5'hD | io_cmd == 5'hF)
? io_lhs
: io_rhs;
endmodule
hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv
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@@ -0,0 +1,446 @@
// Generated by CIRCT firtool-1.151.0
module APBGpsBlock(
input clock,
reset,
output auto_pps_out_out,
input [3:0] auto_rf_data_in,
input auto_afe_clock_in,
auto_tracking_clock_in,
auto_acq_clock_in,
auto_in_psel,
auto_in_penable,
auto_in_pwrite,
input [28:0] auto_in_paddr,
input [31:0] auto_in_pwdata,
output auto_in_pready,
auto_in_pslverr,
output [31:0] auto_in_prdata,
output auto_int_out_0,
auto_int_out_1,
auto_int_out_2,
auto_int_out_3,
auto_int_out_4,
auto_int_out_5,
auto_int_out_6,
auto_int_out_7,
auto_int_out_8,
auto_int_out_9
);
wire _afeReset_gps_afe_reset_io_sync_reset;
wire _trckReset_gps_trck_reset_io_sync_reset;
wire _acqReset_gps_acq_reset_io_sync_reset;
wire _apbReset_gps_apb_reset_io_sync_reset;
wire _pps_PREADY;
wire [31:0] _pps_PRDATA;
wire _pps_PSLVERR;
wire _tracking_8_PREADY;
wire [31:0] _tracking_8_PRDATA;
wire _tracking_8_PSLVERR;
wire _tracking_8_pps_capture;
wire _tracking_7_PREADY;
wire [31:0] _tracking_7_PRDATA;
wire _tracking_7_PSLVERR;
wire _tracking_7_pps_capture;
wire _tracking_6_PREADY;
wire [31:0] _tracking_6_PRDATA;
wire _tracking_6_PSLVERR;
wire _tracking_6_pps_capture;
wire _tracking_5_PREADY;
wire [31:0] _tracking_5_PRDATA;
wire _tracking_5_PSLVERR;
wire _tracking_5_pps_capture;
wire _tracking_4_PREADY;
wire [31:0] _tracking_4_PRDATA;
wire _tracking_4_PSLVERR;
wire _tracking_4_pps_capture;
wire _tracking_3_PREADY;
wire [31:0] _tracking_3_PRDATA;
wire _tracking_3_PSLVERR;
wire _tracking_3_pps_capture;
wire _tracking_2_PREADY;
wire [31:0] _tracking_2_PRDATA;
wire _tracking_2_PSLVERR;
wire _tracking_2_pps_capture;
wire _tracking_1_PREADY;
wire [31:0] _tracking_1_PRDATA;
wire _tracking_1_PSLVERR;
wire _tracking_1_pps_capture;
wire _tracking_0_PREADY;
wire [31:0] _tracking_0_PRDATA;
wire _tracking_0_PSLVERR;
wire _tracking_0_pps_capture;
wire _afe_sample_align_o;
wire [31:0] _afe_sample_counter_o;
wire _acq_PREADY;
wire [31:0] _acq_PRDATA;
wire _acq_PSLVERR;
wire _acq_afe_start;
wire _acq_sample_counter_clear;
wire sel_0 = auto_in_paddr[28:12] == 17'h10020;
wire sel_1 = auto_in_paddr[28:12] == 17'h10021;
wire sel_2 = auto_in_paddr[28:12] == 17'h10022;
wire sel_3 = auto_in_paddr[28:12] == 17'h10023;
wire sel_4 = auto_in_paddr[28:12] == 17'h10024;
wire sel_5 = auto_in_paddr[28:12] == 17'h10025;
wire sel_6 = auto_in_paddr[28:12] == 17'h10026;
wire sel_7 = auto_in_paddr[28:12] == 17'h10027;
wire sel_8 = auto_in_paddr[28:12] == 17'h10028;
wire sel_9 = auto_in_paddr[28:12] == 17'h10029;
wire sel_10 = auto_in_paddr[28:12] == 17'h1002A;
wire _GEN =
{sel_10,
sel_9,
sel_8,
sel_7,
sel_6,
sel_5,
sel_4,
sel_3,
sel_2,
sel_1,
sel_0} == 11'h0;
acq_wrapper #(
.ADDR_BUS_WIDTH(12),
.DATA_BUS_WIDTH(32),
.HIGH_ADDRESS(4095),
.LOW_ADDRESS(0)
) acq (
.PCLK (clock),
.PRESETN (~_apbReset_gps_apb_reset_io_sync_reset),
.PADDR (auto_in_paddr[11:0]),
.PSEL (auto_in_psel & sel_0),
.PENABLE (auto_in_penable),
.PWRITE (auto_in_pwrite),
.PWDATA (auto_in_pwdata),
.PREADY (_acq_PREADY),
.PRDATA (_acq_PRDATA),
.PSLVERR (_acq_PSLVERR),
.afe_start (_acq_afe_start),
.sample_counter_clear (_acq_sample_counter_clear),
.clk_80mhz (auto_acq_clock_in),
.rf_clk (auto_afe_clock_in),
.acq_resetn (~_acqReset_gps_acq_reset_io_sync_reset),
.afe_resetn (~_afeReset_gps_afe_reset_io_sync_reset),
.rf_data (auto_rf_data_in),
.sample_align (_afe_sample_align_o),
.start_acq_manuel (1'h0),
.acq_intr (auto_int_out_0)
);
afe_top afe (
.afe_rstn (~_afeReset_gps_afe_reset_io_sync_reset),
.trk_rstn (~_trckReset_gps_trck_reset_io_sync_reset),
.afe_clk (auto_afe_clock_in),
.trk_clk (auto_tracking_clock_in),
.start_i (_acq_afe_start),
.sample_counter_clear_i (_acq_sample_counter_clear),
.sample_align_o (_afe_sample_align_o),
.sample_counter_o (_afe_sample_counter_o),
.rf_data_o (/* unused */)
);
tracking_wrapper #(
.ADDR_BUS_WIDTH(12),
.DATA_BUS_WIDTH(32),
.HIGH_ADDRESS(4095),
.LOW_ADDRESS(0)
) tracking_0 (
.PCLK (clock),
.PRESETN (~_apbReset_gps_apb_reset_io_sync_reset),
.PADDR (auto_in_paddr[11:0]),
.PSEL (auto_in_psel & sel_1),
.PENABLE (auto_in_penable),
.PWRITE (auto_in_pwrite),
.PWDATA (auto_in_pwdata),
.PREADY (_tracking_0_PREADY),
.PRDATA (_tracking_0_PRDATA),
.PSLVERR (_tracking_0_PSLVERR),
.trck_resetn (~_trckReset_gps_trck_reset_io_sync_reset),
.afe_resetn (~_afeReset_gps_afe_reset_io_sync_reset),
.trck_clk (auto_tracking_clock_in),
.afe_clk (auto_afe_clock_in),
.afe_data (auto_rf_data_in),
.sample_align (_afe_sample_align_o),
.sample_counter (_afe_sample_counter_o),
.gps_frame_ready (auto_int_out_1),
.pps_capture (_tracking_0_pps_capture)
);
tracking_wrapper #(
.ADDR_BUS_WIDTH(12),
.DATA_BUS_WIDTH(32),
.HIGH_ADDRESS(4095),
.LOW_ADDRESS(0)
) tracking_1 (
.PCLK (clock),
.PRESETN (~_apbReset_gps_apb_reset_io_sync_reset),
.PADDR (auto_in_paddr[11:0]),
.PSEL (auto_in_psel & sel_2),
.PENABLE (auto_in_penable),
.PWRITE (auto_in_pwrite),
.PWDATA (auto_in_pwdata),
.PREADY (_tracking_1_PREADY),
.PRDATA (_tracking_1_PRDATA),
.PSLVERR (_tracking_1_PSLVERR),
.trck_resetn (~_trckReset_gps_trck_reset_io_sync_reset),
.afe_resetn (~_afeReset_gps_afe_reset_io_sync_reset),
.trck_clk (auto_tracking_clock_in),
.afe_clk (auto_afe_clock_in),
.afe_data (auto_rf_data_in),
.sample_align (_afe_sample_align_o),
.sample_counter (_afe_sample_counter_o),
.gps_frame_ready (auto_int_out_2),
.pps_capture (_tracking_1_pps_capture)
);
tracking_wrapper #(
.ADDR_BUS_WIDTH(12),
.DATA_BUS_WIDTH(32),
.HIGH_ADDRESS(4095),
.LOW_ADDRESS(0)
) tracking_2 (
.PCLK (clock),
.PRESETN (~_apbReset_gps_apb_reset_io_sync_reset),
.PADDR (auto_in_paddr[11:0]),
.PSEL (auto_in_psel & sel_3),
.PENABLE (auto_in_penable),
.PWRITE (auto_in_pwrite),
.PWDATA (auto_in_pwdata),
.PREADY (_tracking_2_PREADY),
.PRDATA (_tracking_2_PRDATA),
.PSLVERR (_tracking_2_PSLVERR),
.trck_resetn (~_trckReset_gps_trck_reset_io_sync_reset),
.afe_resetn (~_afeReset_gps_afe_reset_io_sync_reset),
.trck_clk (auto_tracking_clock_in),
.afe_clk (auto_afe_clock_in),
.afe_data (auto_rf_data_in),
.sample_align (_afe_sample_align_o),
.sample_counter (_afe_sample_counter_o),
.gps_frame_ready (auto_int_out_3),
.pps_capture (_tracking_2_pps_capture)
);
tracking_wrapper #(
.ADDR_BUS_WIDTH(12),
.DATA_BUS_WIDTH(32),
.HIGH_ADDRESS(4095),
.LOW_ADDRESS(0)
) tracking_3 (
.PCLK (clock),
.PRESETN (~_apbReset_gps_apb_reset_io_sync_reset),
.PADDR (auto_in_paddr[11:0]),
.PSEL (auto_in_psel & sel_4),
.PENABLE (auto_in_penable),
.PWRITE (auto_in_pwrite),
.PWDATA (auto_in_pwdata),
.PREADY (_tracking_3_PREADY),
.PRDATA (_tracking_3_PRDATA),
.PSLVERR (_tracking_3_PSLVERR),
.trck_resetn (~_trckReset_gps_trck_reset_io_sync_reset),
.afe_resetn (~_afeReset_gps_afe_reset_io_sync_reset),
.trck_clk (auto_tracking_clock_in),
.afe_clk (auto_afe_clock_in),
.afe_data (auto_rf_data_in),
.sample_align (_afe_sample_align_o),
.sample_counter (_afe_sample_counter_o),
.gps_frame_ready (auto_int_out_4),
.pps_capture (_tracking_3_pps_capture)
);
tracking_wrapper #(
.ADDR_BUS_WIDTH(12),
.DATA_BUS_WIDTH(32),
.HIGH_ADDRESS(4095),
.LOW_ADDRESS(0)
) tracking_4 (
.PCLK (clock),
.PRESETN (~_apbReset_gps_apb_reset_io_sync_reset),
.PADDR (auto_in_paddr[11:0]),
.PSEL (auto_in_psel & sel_5),
.PENABLE (auto_in_penable),
.PWRITE (auto_in_pwrite),
.PWDATA (auto_in_pwdata),
.PREADY (_tracking_4_PREADY),
.PRDATA (_tracking_4_PRDATA),
.PSLVERR (_tracking_4_PSLVERR),
.trck_resetn (~_trckReset_gps_trck_reset_io_sync_reset),
.afe_resetn (~_afeReset_gps_afe_reset_io_sync_reset),
.trck_clk (auto_tracking_clock_in),
.afe_clk (auto_afe_clock_in),
.afe_data (auto_rf_data_in),
.sample_align (_afe_sample_align_o),
.sample_counter (_afe_sample_counter_o),
.gps_frame_ready (auto_int_out_5),
.pps_capture (_tracking_4_pps_capture)
);
tracking_wrapper #(
.ADDR_BUS_WIDTH(12),
.DATA_BUS_WIDTH(32),
.HIGH_ADDRESS(4095),
.LOW_ADDRESS(0)
) tracking_5 (
.PCLK (clock),
.PRESETN (~_apbReset_gps_apb_reset_io_sync_reset),
.PADDR (auto_in_paddr[11:0]),
.PSEL (auto_in_psel & sel_6),
.PENABLE (auto_in_penable),
.PWRITE (auto_in_pwrite),
.PWDATA (auto_in_pwdata),
.PREADY (_tracking_5_PREADY),
.PRDATA (_tracking_5_PRDATA),
.PSLVERR (_tracking_5_PSLVERR),
.trck_resetn (~_trckReset_gps_trck_reset_io_sync_reset),
.afe_resetn (~_afeReset_gps_afe_reset_io_sync_reset),
.trck_clk (auto_tracking_clock_in),
.afe_clk (auto_afe_clock_in),
.afe_data (auto_rf_data_in),
.sample_align (_afe_sample_align_o),
.sample_counter (_afe_sample_counter_o),
.gps_frame_ready (auto_int_out_6),
.pps_capture (_tracking_5_pps_capture)
);
tracking_wrapper #(
.ADDR_BUS_WIDTH(12),
.DATA_BUS_WIDTH(32),
.HIGH_ADDRESS(4095),
.LOW_ADDRESS(0)
) tracking_6 (
.PCLK (clock),
.PRESETN (~_apbReset_gps_apb_reset_io_sync_reset),
.PADDR (auto_in_paddr[11:0]),
.PSEL (auto_in_psel & sel_7),
.PENABLE (auto_in_penable),
.PWRITE (auto_in_pwrite),
.PWDATA (auto_in_pwdata),
.PREADY (_tracking_6_PREADY),
.PRDATA (_tracking_6_PRDATA),
.PSLVERR (_tracking_6_PSLVERR),
.trck_resetn (~_trckReset_gps_trck_reset_io_sync_reset),
.afe_resetn (~_afeReset_gps_afe_reset_io_sync_reset),
.trck_clk (auto_tracking_clock_in),
.afe_clk (auto_afe_clock_in),
.afe_data (auto_rf_data_in),
.sample_align (_afe_sample_align_o),
.sample_counter (_afe_sample_counter_o),
.gps_frame_ready (auto_int_out_7),
.pps_capture (_tracking_6_pps_capture)
);
tracking_wrapper #(
.ADDR_BUS_WIDTH(12),
.DATA_BUS_WIDTH(32),
.HIGH_ADDRESS(4095),
.LOW_ADDRESS(0)
) tracking_7 (
.PCLK (clock),
.PRESETN (~_apbReset_gps_apb_reset_io_sync_reset),
.PADDR (auto_in_paddr[11:0]),
.PSEL (auto_in_psel & sel_8),
.PENABLE (auto_in_penable),
.PWRITE (auto_in_pwrite),
.PWDATA (auto_in_pwdata),
.PREADY (_tracking_7_PREADY),
.PRDATA (_tracking_7_PRDATA),
.PSLVERR (_tracking_7_PSLVERR),
.trck_resetn (~_trckReset_gps_trck_reset_io_sync_reset),
.afe_resetn (~_afeReset_gps_afe_reset_io_sync_reset),
.trck_clk (auto_tracking_clock_in),
.afe_clk (auto_afe_clock_in),
.afe_data (auto_rf_data_in),
.sample_align (_afe_sample_align_o),
.sample_counter (_afe_sample_counter_o),
.gps_frame_ready (auto_int_out_8),
.pps_capture (_tracking_7_pps_capture)
);
tracking_wrapper #(
.ADDR_BUS_WIDTH(12),
.DATA_BUS_WIDTH(32),
.HIGH_ADDRESS(4095),
.LOW_ADDRESS(0)
) tracking_8 (
.PCLK (clock),
.PRESETN (~_apbReset_gps_apb_reset_io_sync_reset),
.PADDR (auto_in_paddr[11:0]),
.PSEL (auto_in_psel & sel_9),
.PENABLE (auto_in_penable),
.PWRITE (auto_in_pwrite),
.PWDATA (auto_in_pwdata),
.PREADY (_tracking_8_PREADY),
.PRDATA (_tracking_8_PRDATA),
.PSLVERR (_tracking_8_PSLVERR),
.trck_resetn (~_trckReset_gps_trck_reset_io_sync_reset),
.afe_resetn (~_afeReset_gps_afe_reset_io_sync_reset),
.trck_clk (auto_tracking_clock_in),
.afe_clk (auto_afe_clock_in),
.afe_data (auto_rf_data_in),
.sample_align (_afe_sample_align_o),
.sample_counter (_afe_sample_counter_o),
.gps_frame_ready (auto_int_out_9),
.pps_capture (_tracking_8_pps_capture)
);
pps_wrapper #(
.ADDR_BUS_WIDTH(12),
.DATA_BUS_WIDTH(32),
.HIGH_ADDRESS(4095),
.LOW_ADDRESS(0),
.NUM_CAPTURE_CHANNELS(9)
) pps (
.PCLK (clock),
.PRESETN (~_apbReset_gps_apb_reset_io_sync_reset),
.PADDR (auto_in_paddr[11:0]),
.PSEL (auto_in_psel & sel_10),
.PENABLE (auto_in_penable),
.PWRITE (auto_in_pwrite),
.PWDATA (auto_in_pwdata),
.PREADY (_pps_PREADY),
.PRDATA (_pps_PRDATA),
.PSLVERR (_pps_PSLVERR),
.pps_clk (auto_tracking_clock_in),
.pps_resetn (~_trckReset_gps_trck_reset_io_sync_reset),
.capture_i
({_tracking_8_pps_capture,
_tracking_7_pps_capture,
_tracking_6_pps_capture,
_tracking_5_pps_capture,
_tracking_4_pps_capture,
_tracking_3_pps_capture,
_tracking_2_pps_capture,
_tracking_1_pps_capture,
_tracking_0_pps_capture}),
.pps_out (auto_pps_out_out),
.pps_valid (/* unused */)
);
ResetCatchAndSync_d3 apbReset_gps_apb_reset (
.clock (clock),
.reset (reset),
.io_sync_reset (_apbReset_gps_apb_reset_io_sync_reset)
);
ResetCatchAndSync_d3 acqReset_gps_acq_reset (
.clock (auto_acq_clock_in),
.reset (reset),
.io_sync_reset (_acqReset_gps_acq_reset_io_sync_reset)
);
ResetCatchAndSync_d3 trckReset_gps_trck_reset (
.clock (auto_tracking_clock_in),
.reset (reset),
.io_sync_reset (_trckReset_gps_trck_reset_io_sync_reset)
);
ResetCatchAndSync_d3 afeReset_gps_afe_reset (
.clock (auto_afe_clock_in),
.reset (reset),
.io_sync_reset (_afeReset_gps_afe_reset_io_sync_reset)
);
assign auto_in_pready =
_GEN | sel_0 & _acq_PREADY | sel_1 & _tracking_0_PREADY | sel_2 & _tracking_1_PREADY
| sel_3 & _tracking_2_PREADY | sel_4 & _tracking_3_PREADY | sel_5 & _tracking_4_PREADY
| sel_6 & _tracking_5_PREADY | sel_7 & _tracking_6_PREADY | sel_8 & _tracking_7_PREADY
| sel_9 & _tracking_8_PREADY | sel_10 & _pps_PREADY;
assign auto_in_pslverr =
_GEN | sel_0 & _acq_PSLVERR | sel_1 & _tracking_0_PSLVERR | sel_2
& _tracking_1_PSLVERR | sel_3 & _tracking_2_PSLVERR | sel_4 & _tracking_3_PSLVERR
| sel_5 & _tracking_4_PSLVERR | sel_6 & _tracking_5_PSLVERR | sel_7
& _tracking_6_PSLVERR | sel_8 & _tracking_7_PSLVERR | sel_9 & _tracking_8_PSLVERR
| sel_10 & _pps_PSLVERR;
assign auto_in_prdata =
(sel_0 ? _acq_PRDATA : 32'h0) | (sel_1 ? _tracking_0_PRDATA : 32'h0)
| (sel_2 ? _tracking_1_PRDATA : 32'h0) | (sel_3 ? _tracking_2_PRDATA : 32'h0)
| (sel_4 ? _tracking_3_PRDATA : 32'h0) | (sel_5 ? _tracking_4_PRDATA : 32'h0)
| (sel_6 ? _tracking_5_PRDATA : 32'h0) | (sel_7 ? _tracking_6_PRDATA : 32'h0)
| (sel_8 ? _tracking_7_PRDATA : 32'h0) | (sel_9 ? _tracking_8_PRDATA : 32'h0)
| (sel_10 ? _pps_PRDATA : 32'h0);
endmodule
hardware/generated/genesys2-soc-verilog/Arbiter3_LLWB.sv
+18
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// Generated by CIRCT firtool-1.151.0
module Arbiter3_LLWB(
output io_in_0_ready,
input io_in_0_valid,
input [63:0] io_in_0_bits_data,
input [4:0] io_in_0_bits_tag,
input io_out_ready,
output io_out_valid,
output [63:0] io_out_bits_data,
output [4:0] io_out_bits_tag
);
assign io_in_0_ready = io_out_ready;
assign io_out_valid = io_in_0_valid;
assign io_out_bits_data = io_in_0_valid ? io_in_0_bits_data : 64'h0;
assign io_out_bits_tag = io_in_0_valid ? io_in_0_bits_tag : 5'h0;
endmodule
hardware/generated/genesys2-soc-verilog/Arbiter4_DCacheDataReq.sv
+42
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@@ -0,0 +1,42 @@
// Generated by CIRCT firtool-1.151.0
module Arbiter4_DCacheDataReq(
input io_in_0_valid,
input [19:0] io_in_0_bits_addr,
input io_in_0_bits_write,
input [63:0] io_in_0_bits_wdata,
input [7:0] io_in_0_bits_eccMask,
output io_in_1_ready,
input io_in_1_valid,
input [19:0] io_in_1_bits_addr,
input io_in_1_bits_write,
input [63:0] io_in_1_bits_wdata,
input [7:0] io_in_1_bits_eccMask,
output io_in_3_ready,
input io_in_3_valid,
input [19:0] io_in_3_bits_addr,
input [63:0] io_in_3_bits_wdata,
output io_out_valid,
output [19:0] io_out_bits_addr,
output io_out_bits_write,
output [63:0] io_out_bits_wdata,
output [7:0] io_out_bits_eccMask
);
wire _grant_T = io_in_0_valid | io_in_1_valid;
assign io_in_1_ready = ~io_in_0_valid;
assign io_in_3_ready = ~_grant_T;
assign io_out_valid = _grant_T | io_in_3_valid;
assign io_out_bits_addr =
io_in_0_valid
? io_in_0_bits_addr
: io_in_1_valid ? io_in_1_bits_addr : io_in_3_bits_addr;
assign io_out_bits_write =
io_in_0_valid ? io_in_0_bits_write : io_in_1_valid & io_in_1_bits_write;
assign io_out_bits_wdata =
io_in_0_valid
? io_in_0_bits_wdata
: io_in_1_valid ? io_in_1_bits_wdata : io_in_3_bits_wdata;
assign io_out_bits_eccMask =
io_in_0_valid ? io_in_0_bits_eccMask : io_in_1_valid ? io_in_1_bits_eccMask : 8'hFF;
endmodule
hardware/generated/genesys2-soc-verilog/Arbiter8_DCacheMetadataReq.sv
+24
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// Generated by CIRCT firtool-1.151.0
module Arbiter8_DCacheMetadataReq(
input io_in_2_valid,
input [33:0] io_in_2_bits_addr,
input io_in_3_valid,
input [33:0] io_in_3_bits_addr,
output io_in_7_ready,
input io_in_7_valid,
input [33:0] io_in_7_bits_addr,
output io_out_valid,
io_out_bits_write,
output [33:0] io_out_bits_addr
);
wire _grant_T_2 = io_in_2_valid | io_in_3_valid;
assign io_in_7_ready = ~_grant_T_2;
assign io_out_valid = _grant_T_2 | io_in_7_valid;
assign io_out_bits_write = io_in_2_valid | io_in_3_valid;
assign io_out_bits_addr =
io_in_2_valid
? io_in_2_bits_addr
: io_in_3_valid ? io_in_3_bits_addr : io_in_7_bits_addr;
endmodule
hardware/generated/genesys2-soc-verilog/AsyncQueueSink_DebugInternalBundle.sv
+110
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@@ -0,0 +1,110 @@
// Generated by CIRCT firtool-1.151.0
module AsyncQueueSink_DebugInternalBundle(
input clock,
reset,
output io_deq_valid,
io_deq_bits_resumereq,
output [9:0] io_deq_bits_hartsel,
output io_deq_bits_ackhavereset,
io_deq_bits_hrmask_0,
input io_async_mem_0_resumereq,
input [9:0] io_async_mem_0_hartsel,
input io_async_mem_0_ackhavereset,
io_async_mem_0_hrmask_0,
output io_async_ridx,
input io_async_widx,
output io_async_safe_ridx_valid,
input io_async_safe_widx_valid,
io_async_safe_source_reset_n,
output io_async_safe_sink_reset_n
);
wire io_deq_valid_0;
wire _source_valid_io_out;
wire _source_extend_io_out;
wire _sink_valid_0_io_out;
wire [14:0] _io_deq_bits_deq_bits_reg_io_q;
wire _widx_widx_gray_io_q;
reg ridx_ridx_bin;
wire ridx = _source_valid_io_out & ridx_ridx_bin + io_deq_valid_0;
wire valid = _source_valid_io_out & ridx != _widx_widx_gray_io_q;
reg valid_reg;
assign io_deq_valid_0 = valid_reg & _source_valid_io_out;
reg ridx_gray;
always @(posedge clock or posedge reset) begin
if (reset) begin
ridx_ridx_bin <= 1'h0;
valid_reg <= 1'h0;
ridx_gray <= 1'h0;
end
else begin
ridx_ridx_bin <= ridx;
valid_reg <= valid;
ridx_gray <= ridx;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
initial begin
if (reset) begin
ridx_ridx_bin = 1'h0;
valid_reg = 1'h0;
ridx_gray = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
AsyncResetSynchronizerShiftReg_w1_d3_i0 widx_widx_gray (
.clock (clock),
.reset (reset),
.io_d (io_async_widx),
.io_q (_widx_widx_gray_io_q)
);
ClockCrossingReg_w15 io_deq_bits_deq_bits_reg (
.clock (clock),
.io_d
({io_async_mem_0_resumereq,
io_async_mem_0_hartsel,
io_async_mem_0_ackhavereset,
2'h0,
io_async_mem_0_hrmask_0}),
.io_q (_io_deq_bits_deq_bits_reg_io_q),
.io_en (valid)
);
AsyncValidSync sink_valid_0 (
.io_in (1'h1),
.io_out (_sink_valid_0_io_out),
.clock (clock),
.reset (reset | ~io_async_safe_source_reset_n)
);
AsyncValidSync sink_valid_1 (
.io_in (_sink_valid_0_io_out),
.io_out (io_async_safe_ridx_valid),
.clock (clock),
.reset (reset | ~io_async_safe_source_reset_n)
);
AsyncValidSync source_extend (
.io_in (io_async_safe_widx_valid),
.io_out (_source_extend_io_out),
.clock (clock),
.reset (reset | ~io_async_safe_source_reset_n)
);
AsyncValidSync source_valid (
.io_in (_source_extend_io_out),
.io_out (_source_valid_io_out),
.clock (clock),
.reset (reset)
);
assign io_deq_valid = io_deq_valid_0;
assign io_deq_bits_resumereq = _io_deq_bits_deq_bits_reg_io_q[14];
assign io_deq_bits_hartsel = _io_deq_bits_deq_bits_reg_io_q[13:4];
assign io_deq_bits_ackhavereset = _io_deq_bits_deq_bits_reg_io_q[3];
assign io_deq_bits_hrmask_0 = _io_deq_bits_deq_bits_reg_io_q[0];
assign io_async_ridx = ridx_gray;
assign io_async_safe_sink_reset_n = ~reset;
endmodule
hardware/generated/genesys2-soc-verilog/AsyncQueueSink_TLBundleA_a9d32s1k1z2u.sv
+116
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// Generated by CIRCT firtool-1.151.0
module AsyncQueueSink_TLBundleA_a9d32s1k1z2u(
input clock,
reset,
io_deq_ready,
output io_deq_valid,
output [2:0] io_deq_bits_opcode,
output [1:0] io_deq_bits_size,
output io_deq_bits_source,
output [8:0] io_deq_bits_address,
output [3:0] io_deq_bits_mask,
output [31:0] io_deq_bits_data,
input [2:0] io_async_mem_0_opcode,
input [8:0] io_async_mem_0_address,
input [31:0] io_async_mem_0_data,
output io_async_ridx,
input io_async_widx,
output io_async_safe_ridx_valid,
input io_async_safe_widx_valid,
io_async_safe_source_reset_n,
output io_async_safe_sink_reset_n
);
wire io_deq_valid_0;
wire _source_valid_io_out;
wire _source_extend_io_out;
wire _sink_valid_0_io_out;
wire [54:0] _io_deq_bits_deq_bits_reg_io_q;
wire _widx_widx_gray_io_q;
reg ridx_ridx_bin;
wire ridx =
_source_valid_io_out & ridx_ridx_bin + (io_deq_ready & io_deq_valid_0);
wire valid = _source_valid_io_out & ridx != _widx_widx_gray_io_q;
reg valid_reg;
assign io_deq_valid_0 = valid_reg & _source_valid_io_out;
reg ridx_gray;
always @(posedge clock or posedge reset) begin
if (reset) begin
ridx_ridx_bin <= 1'h0;
valid_reg <= 1'h0;
ridx_gray <= 1'h0;
end
else begin
ridx_ridx_bin <= ridx;
valid_reg <= valid;
ridx_gray <= ridx;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
initial begin
if (reset) begin
ridx_ridx_bin = 1'h0;
valid_reg = 1'h0;
ridx_gray = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
AsyncResetSynchronizerShiftReg_w1_d3_i0 widx_widx_gray (
.clock (clock),
.reset (reset),
.io_d (io_async_widx),
.io_q (_widx_widx_gray_io_q)
);
ClockCrossingReg_w55 io_deq_bits_deq_bits_reg (
.clock (clock),
.io_d
({io_async_mem_0_opcode,
6'h4,
io_async_mem_0_address,
4'hF,
io_async_mem_0_data,
1'h0}),
.io_q (_io_deq_bits_deq_bits_reg_io_q),
.io_en (valid)
);
AsyncValidSync sink_valid_0 (
.io_in (1'h1),
.io_out (_sink_valid_0_io_out),
.clock (clock),
.reset (reset | ~io_async_safe_source_reset_n)
);
AsyncValidSync sink_valid_1 (
.io_in (_sink_valid_0_io_out),
.io_out (io_async_safe_ridx_valid),
.clock (clock),
.reset (reset | ~io_async_safe_source_reset_n)
);
AsyncValidSync source_extend (
.io_in (io_async_safe_widx_valid),
.io_out (_source_extend_io_out),
.clock (clock),
.reset (reset | ~io_async_safe_source_reset_n)
);
AsyncValidSync source_valid (
.io_in (_source_extend_io_out),
.io_out (_source_valid_io_out),
.clock (clock),
.reset (reset)
);
assign io_deq_valid = io_deq_valid_0;
assign io_deq_bits_opcode = _io_deq_bits_deq_bits_reg_io_q[54:52];
assign io_deq_bits_size = _io_deq_bits_deq_bits_reg_io_q[48:47];
assign io_deq_bits_source = _io_deq_bits_deq_bits_reg_io_q[46];
assign io_deq_bits_address = _io_deq_bits_deq_bits_reg_io_q[45:37];
assign io_deq_bits_mask = _io_deq_bits_deq_bits_reg_io_q[36:33];
assign io_deq_bits_data = _io_deq_bits_deq_bits_reg_io_q[32:1];
assign io_async_ridx = ridx_gray;
assign io_async_safe_sink_reset_n = ~reset;
endmodule
hardware/generated/genesys2-soc-verilog/AsyncQueueSink_TLBundleD_a9d32s1k1z2u.sv
+114
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@@ -0,0 +1,114 @@
// Generated by CIRCT firtool-1.151.0
module AsyncQueueSink_TLBundleD_a9d32s1k1z2u(
input clock,
reset,
io_deq_ready,
output io_deq_valid,
output [2:0] io_deq_bits_opcode,
output io_deq_bits_denied,
output [31:0] io_deq_bits_data,
output io_deq_bits_corrupt,
input [2:0] io_async_mem_0_opcode,
input [1:0] io_async_mem_0_size,
input io_async_mem_0_source,
input [31:0] io_async_mem_0_data,
output io_async_ridx,
input io_async_widx,
output io_async_safe_ridx_valid,
input io_async_safe_widx_valid,
io_async_safe_source_reset_n,
output io_async_safe_sink_reset_n
);
wire io_deq_valid_0;
wire _source_valid_io_out;
wire _source_extend_io_out;
wire _sink_valid_0_io_out;
wire [42:0] _io_deq_bits_deq_bits_reg_io_q;
wire _widx_widx_gray_io_q;
reg ridx_ridx_bin;
wire ridx =
_source_valid_io_out & ridx_ridx_bin + (io_deq_ready & io_deq_valid_0);
wire valid = _source_valid_io_out & ridx != _widx_widx_gray_io_q;
reg valid_reg;
assign io_deq_valid_0 = valid_reg & _source_valid_io_out;
reg ridx_gray;
always @(posedge clock or posedge reset) begin
if (reset) begin
ridx_ridx_bin <= 1'h0;
valid_reg <= 1'h0;
ridx_gray <= 1'h0;
end
else begin
ridx_ridx_bin <= ridx;
valid_reg <= valid;
ridx_gray <= ridx;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
initial begin
if (reset) begin
ridx_ridx_bin = 1'h0;
valid_reg = 1'h0;
ridx_gray = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
AsyncResetSynchronizerShiftReg_w1_d3_i0 widx_widx_gray (
.clock (clock),
.reset (reset),
.io_d (io_async_widx),
.io_q (_widx_widx_gray_io_q)
);
ClockCrossingReg_w43 io_deq_bits_deq_bits_reg (
.clock (clock),
.io_d
({io_async_mem_0_opcode,
2'h0,
io_async_mem_0_size,
io_async_mem_0_source,
2'h0,
io_async_mem_0_data,
1'h0}),
.io_q (_io_deq_bits_deq_bits_reg_io_q),
.io_en (valid)
);
AsyncValidSync sink_valid_0 (
.io_in (1'h1),
.io_out (_sink_valid_0_io_out),
.clock (clock),
.reset (reset | ~io_async_safe_source_reset_n)
);
AsyncValidSync sink_valid_1 (
.io_in (_sink_valid_0_io_out),
.io_out (io_async_safe_ridx_valid),
.clock (clock),
.reset (reset | ~io_async_safe_source_reset_n)
);
AsyncValidSync source_extend (
.io_in (io_async_safe_widx_valid),
.io_out (_source_extend_io_out),
.clock (clock),
.reset (reset | ~io_async_safe_source_reset_n)
);
AsyncValidSync source_valid (
.io_in (_source_extend_io_out),
.io_out (_source_valid_io_out),
.clock (clock),
.reset (reset)
);
assign io_deq_valid = io_deq_valid_0;
assign io_deq_bits_opcode = _io_deq_bits_deq_bits_reg_io_q[42:40];
assign io_deq_bits_denied = _io_deq_bits_deq_bits_reg_io_q[33];
assign io_deq_bits_data = _io_deq_bits_deq_bits_reg_io_q[32:1];
assign io_deq_bits_corrupt = _io_deq_bits_deq_bits_reg_io_q[0];
assign io_async_ridx = ridx_gray;
assign io_async_safe_sink_reset_n = ~reset;
endmodule
hardware/generated/genesys2-soc-verilog/AsyncQueueSource_DebugInternalBundle.sv
+112
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@@ -0,0 +1,112 @@
// Generated by CIRCT firtool-1.151.0
module AsyncQueueSource_DebugInternalBundle(
input clock,
reset,
output io_enq_ready,
input io_enq_valid,
io_enq_bits_resumereq,
input [9:0] io_enq_bits_hartsel,
input io_enq_bits_ackhavereset,
io_enq_bits_hrmask_0,
output io_async_mem_0_resumereq,
output [9:0] io_async_mem_0_hartsel,
output io_async_mem_0_ackhavereset,
io_async_mem_0_hrmask_0,
input io_async_ridx,
output io_async_widx,
input io_async_safe_ridx_valid,
output io_async_safe_widx_valid,
io_async_safe_source_reset_n,
input io_async_safe_sink_reset_n
);
wire io_enq_ready_0;
wire _sink_valid_io_out;
wire _sink_extend_io_out;
wire _source_valid_0_io_out;
wire _ridx_ridx_gray_io_q;
reg mem_0_resumereq;
reg [9:0] mem_0_hartsel;
reg mem_0_ackhavereset;
reg mem_0_hrmask_0;
wire _widx_T_1 = io_enq_ready_0 & io_enq_valid;
reg widx_widx_bin;
reg ready_reg;
assign io_enq_ready_0 = ready_reg & _sink_valid_io_out;
reg widx_gray;
always @(posedge clock) begin
if (_widx_T_1) begin
mem_0_resumereq <= io_enq_bits_resumereq;
mem_0_hartsel <= io_enq_bits_hartsel;
mem_0_ackhavereset <= io_enq_bits_ackhavereset;
mem_0_hrmask_0 <= io_enq_bits_hrmask_0;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset) begin
widx_widx_bin <= 1'h0;
ready_reg <= 1'h0;
widx_gray <= 1'h0;
end
else begin
automatic logic widx;
widx = _sink_valid_io_out & widx_widx_bin + _widx_T_1;
widx_widx_bin <= widx;
ready_reg <= _sink_valid_io_out & widx != ~_ridx_ridx_gray_io_q;
widx_gray <= widx;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
initial begin
if (reset) begin
widx_widx_bin = 1'h0;
ready_reg = 1'h0;
widx_gray = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
AsyncResetSynchronizerShiftReg_w1_d3_i0 ridx_ridx_gray (
.clock (clock),
.reset (reset),
.io_d (io_async_ridx),
.io_q (_ridx_ridx_gray_io_q)
);
AsyncValidSync source_valid_0 (
.io_in (1'h1),
.io_out (_source_valid_0_io_out),
.clock (clock),
.reset (reset | ~io_async_safe_sink_reset_n)
);
AsyncValidSync source_valid_1 (
.io_in (_source_valid_0_io_out),
.io_out (io_async_safe_widx_valid),
.clock (clock),
.reset (reset | ~io_async_safe_sink_reset_n)
);
AsyncValidSync sink_extend (
.io_in (io_async_safe_ridx_valid),
.io_out (_sink_extend_io_out),
.clock (clock),
.reset (reset | ~io_async_safe_sink_reset_n)
);
AsyncValidSync sink_valid (
.io_in (_sink_extend_io_out),
.io_out (_sink_valid_io_out),
.clock (clock),
.reset (reset)
);
assign io_enq_ready = io_enq_ready_0;
assign io_async_mem_0_resumereq = mem_0_resumereq;
assign io_async_mem_0_hartsel = mem_0_hartsel;
assign io_async_mem_0_ackhavereset = mem_0_ackhavereset;
assign io_async_mem_0_hrmask_0 = mem_0_hrmask_0;
assign io_async_widx = widx_gray;
assign io_async_safe_source_reset_n = ~reset;
endmodule
hardware/generated/genesys2-soc-verilog/AsyncQueueSource_TLBundleA_a9d32s1k1z2u.sv
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// Generated by CIRCT firtool-1.151.0
module AsyncQueueSource_TLBundleA_a9d32s1k1z2u(
input clock,
reset,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
input [8:0] io_enq_bits_address,
input [31:0] io_enq_bits_data,
output [2:0] io_async_mem_0_opcode,
output [8:0] io_async_mem_0_address,
output [31:0] io_async_mem_0_data,
input io_async_ridx,
output io_async_widx,
input io_async_safe_ridx_valid,
output io_async_safe_widx_valid,
io_async_safe_source_reset_n,
input io_async_safe_sink_reset_n
);
wire io_enq_ready_0;
wire _sink_valid_io_out;
wire _sink_extend_io_out;
wire _source_valid_0_io_out;
wire _ridx_ridx_gray_io_q;
reg [2:0] mem_0_opcode;
reg [8:0] mem_0_address;
reg [31:0] mem_0_data;
wire _widx_T_1 = io_enq_ready_0 & io_enq_valid;
reg widx_widx_bin;
reg ready_reg;
assign io_enq_ready_0 = ready_reg & _sink_valid_io_out;
reg widx_gray;
always @(posedge clock) begin
if (_widx_T_1) begin
mem_0_opcode <= io_enq_bits_opcode;
mem_0_address <= io_enq_bits_address;
mem_0_data <= io_enq_bits_data;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset) begin
widx_widx_bin <= 1'h0;
ready_reg <= 1'h0;
widx_gray <= 1'h0;
end
else begin
automatic logic widx;
widx = _sink_valid_io_out & widx_widx_bin + _widx_T_1;
widx_widx_bin <= widx;
ready_reg <= _sink_valid_io_out & widx != ~_ridx_ridx_gray_io_q;
widx_gray <= widx;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
initial begin
if (reset) begin
widx_widx_bin = 1'h0;
ready_reg = 1'h0;
widx_gray = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
AsyncResetSynchronizerShiftReg_w1_d3_i0 ridx_ridx_gray (
.clock (clock),
.reset (reset),
.io_d (io_async_ridx),
.io_q (_ridx_ridx_gray_io_q)
);
AsyncValidSync source_valid_0 (
.io_in (1'h1),
.io_out (_source_valid_0_io_out),
.clock (clock),
.reset (reset | ~io_async_safe_sink_reset_n)
);
AsyncValidSync source_valid_1 (
.io_in (_source_valid_0_io_out),
.io_out (io_async_safe_widx_valid),
.clock (clock),
.reset (reset | ~io_async_safe_sink_reset_n)
);
AsyncValidSync sink_extend (
.io_in (io_async_safe_ridx_valid),
.io_out (_sink_extend_io_out),
.clock (clock),
.reset (reset | ~io_async_safe_sink_reset_n)
);
AsyncValidSync sink_valid (
.io_in (_sink_extend_io_out),
.io_out (_sink_valid_io_out),
.clock (clock),
.reset (reset)
);
assign io_enq_ready = io_enq_ready_0;
assign io_async_mem_0_opcode = mem_0_opcode;
assign io_async_mem_0_address = mem_0_address;
assign io_async_mem_0_data = mem_0_data;
assign io_async_widx = widx_gray;
assign io_async_safe_source_reset_n = ~reset;
endmodule
hardware/generated/genesys2-soc-verilog/AsyncQueueSource_TLBundleD_a9d32s1k1z2u.sv
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// Generated by CIRCT firtool-1.151.0
module AsyncQueueSource_TLBundleD_a9d32s1k1z2u(
input clock,
reset,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
input [1:0] io_enq_bits_size,
input io_enq_bits_source,
input [31:0] io_enq_bits_data,
output [2:0] io_async_mem_0_opcode,
output [1:0] io_async_mem_0_size,
output io_async_mem_0_source,
output [31:0] io_async_mem_0_data,
input io_async_ridx,
output io_async_widx,
input io_async_safe_ridx_valid,
output io_async_safe_widx_valid,
io_async_safe_source_reset_n,
input io_async_safe_sink_reset_n
);
wire io_enq_ready_0;
wire _sink_valid_io_out;
wire _sink_extend_io_out;
wire _source_valid_0_io_out;
wire _ridx_ridx_gray_io_q;
reg [2:0] mem_0_opcode;
reg [1:0] mem_0_size;
reg mem_0_source;
reg [31:0] mem_0_data;
wire _widx_T_1 = io_enq_ready_0 & io_enq_valid;
reg widx_widx_bin;
reg ready_reg;
assign io_enq_ready_0 = ready_reg & _sink_valid_io_out;
reg widx_gray;
always @(posedge clock) begin
if (_widx_T_1) begin
mem_0_opcode <= io_enq_bits_opcode;
mem_0_size <= io_enq_bits_size;
mem_0_source <= io_enq_bits_source;
mem_0_data <= io_enq_bits_data;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset) begin
widx_widx_bin <= 1'h0;
ready_reg <= 1'h0;
widx_gray <= 1'h0;
end
else begin
automatic logic widx;
widx = _sink_valid_io_out & widx_widx_bin + _widx_T_1;
widx_widx_bin <= widx;
ready_reg <= _sink_valid_io_out & widx != ~_ridx_ridx_gray_io_q;
widx_gray <= widx;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
initial begin
if (reset) begin
widx_widx_bin = 1'h0;
ready_reg = 1'h0;
widx_gray = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
AsyncResetSynchronizerShiftReg_w1_d3_i0 ridx_ridx_gray (
.clock (clock),
.reset (reset),
.io_d (io_async_ridx),
.io_q (_ridx_ridx_gray_io_q)
);
AsyncValidSync source_valid_0 (
.io_in (1'h1),
.io_out (_source_valid_0_io_out),
.clock (clock),
.reset (reset | ~io_async_safe_sink_reset_n)
);
AsyncValidSync source_valid_1 (
.io_in (_source_valid_0_io_out),
.io_out (io_async_safe_widx_valid),
.clock (clock),
.reset (reset | ~io_async_safe_sink_reset_n)
);
AsyncValidSync sink_extend (
.io_in (io_async_safe_ridx_valid),
.io_out (_sink_extend_io_out),
.clock (clock),
.reset (reset | ~io_async_safe_sink_reset_n)
);
AsyncValidSync sink_valid (
.io_in (_sink_extend_io_out),
.io_out (_sink_valid_io_out),
.clock (clock),
.reset (reset)
);
assign io_enq_ready = io_enq_ready_0;
assign io_async_mem_0_opcode = mem_0_opcode;
assign io_async_mem_0_size = mem_0_size;
assign io_async_mem_0_source = mem_0_source;
assign io_async_mem_0_data = mem_0_data;
assign io_async_widx = widx_gray;
assign io_async_safe_source_reset_n = ~reset;
endmodule
hardware/generated/genesys2-soc-verilog/AsyncResetRegVec_w1_i0.sv
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// Generated by CIRCT firtool-1.151.0
module AsyncResetRegVec_w1_i0(
input clock,
reset,
io_d,
output io_q
);
reg reg_0;
always @(posedge clock or posedge reset) begin
if (reset)
reg_0 <= 1'h0;
else
reg_0 <= io_d;
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
initial begin
if (reset)
reg_0 = 1'h0;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_q = reg_0;
endmodule
hardware/generated/genesys2-soc-verilog/AsyncResetRegVec_w2_i0.sv
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// Generated by CIRCT firtool-1.151.0
module AsyncResetRegVec_w2_i0(
input clock,
reset,
input [1:0] io_d,
output [1:0] io_q
);
reg [1:0] reg_0;
always @(posedge clock or posedge reset) begin
if (reset)
reg_0 <= 2'h0;
else
reg_0 <= io_d;
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
initial begin
if (reset)
reg_0 = 2'h0;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_q = reg_0;
endmodule
hardware/generated/genesys2-soc-verilog/AsyncResetSynchronizerPrimitiveShiftReg_d3_i0.sv
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// Generated by CIRCT firtool-1.151.0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0(
input clock,
reset,
io_d,
output io_q
);
reg sync_0;
reg sync_1;
reg sync_2;
always @(posedge clock or posedge reset) begin
if (reset) begin
sync_0 <= 1'h0;
sync_1 <= 1'h0;
sync_2 <= 1'h0;
end
else begin
sync_0 <= sync_1;
sync_1 <= sync_2;
sync_2 <= io_d;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
initial begin
if (reset) begin
sync_0 = 1'h0;
sync_1 = 1'h0;
sync_2 = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_q = sync_0;
endmodule
hardware/generated/genesys2-soc-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0.sv
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// Generated by CIRCT firtool-1.151.0
module AsyncResetSynchronizerShiftReg_w1_d3_i0(
input clock,
reset,
io_d,
output io_q
);
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain (
.clock (clock),
.reset (reset),
.io_d (io_d),
.io_q (io_q)
);
endmodule
hardware/generated/genesys2-soc-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0_1.sv
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// Generated by CIRCT firtool-1.151.0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_1(
input clock,
reset,
io_d,
output io_q
);
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain (
.clock (clock),
.reset (reset),
.io_d (io_d),
.io_q (io_q)
);
endmodule
hardware/generated/genesys2-soc-verilog/AsyncValidSync.sv
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// Generated by CIRCT firtool-1.151.0
module AsyncValidSync(
input io_in,
output io_out,
input clock,
reset
);
AsyncResetSynchronizerShiftReg_w1_d3_i0_1 io_out_source_valid_0 (
.clock (clock),
.reset (reset),
.io_d (io_in),
.io_q (io_out)
);
endmodule
hardware/generated/genesys2-soc-verilog/BreakpointUnit.sv
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// Generated by CIRCT firtool-1.151.0
module BreakpointUnit(
input io_status_debug,
io_bp_0_control_action,
input [1:0] io_bp_0_control_tmatch,
input io_bp_0_control_x,
io_bp_0_control_w,
io_bp_0_control_r,
input [32:0] io_bp_0_address,
io_pc,
io_ea,
output io_xcpt_if,
io_xcpt_ld,
io_xcpt_st,
io_debug_if,
io_debug_ld,
io_debug_st
);
wire _w_T_2 = io_ea >= io_bp_0_address;
wire [32:0] _w_T_5 = ~io_ea;
wire _r_T_8 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];
wire _r_T_10 = _r_T_8 & io_bp_0_address[1];
wire [32:0] _x_T_15 = ~io_bp_0_address;
wire _r_T_18 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];
wire _r_T_20 = _r_T_18 & io_bp_0_address[1];
wire r =
~io_status_debug & io_bp_0_control_r
& (io_bp_0_control_tmatch[1]
? _w_T_2 ^ io_bp_0_control_tmatch[0]
: {_w_T_5[32:4],
_w_T_5[3:0]
| {_r_T_10 & io_bp_0_address[2],
_r_T_10,
_r_T_8,
io_bp_0_control_tmatch[0]}} == {_x_T_15[32:4],
_x_T_15[3:0]
| {_r_T_20 & io_bp_0_address[2],
_r_T_20,
_r_T_18,
io_bp_0_control_tmatch[0]}});
wire _w_T_8 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];
wire _w_T_10 = _w_T_8 & io_bp_0_address[1];
wire _w_T_18 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];
wire _w_T_20 = _w_T_18 & io_bp_0_address[1];
wire w =
~io_status_debug & io_bp_0_control_w
& (io_bp_0_control_tmatch[1]
? _w_T_2 ^ io_bp_0_control_tmatch[0]
: {_w_T_5[32:4],
_w_T_5[3:0]
| {_w_T_10 & io_bp_0_address[2],
_w_T_10,
_w_T_8,
io_bp_0_control_tmatch[0]}} == {_x_T_15[32:4],
_x_T_15[3:0]
| {_w_T_20 & io_bp_0_address[2],
_w_T_20,
_w_T_18,
io_bp_0_control_tmatch[0]}});
wire [32:0] _x_T_5 = ~io_pc;
wire _x_T_8 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];
wire _x_T_10 = _x_T_8 & io_bp_0_address[1];
wire _x_T_18 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];
wire _x_T_20 = _x_T_18 & io_bp_0_address[1];
wire x =
~io_status_debug & io_bp_0_control_x
& (io_bp_0_control_tmatch[1]
? io_pc >= io_bp_0_address ^ io_bp_0_control_tmatch[0]
: {_x_T_5[32:4],
_x_T_5[3:0]
| {_x_T_10 & io_bp_0_address[2],
_x_T_10,
_x_T_8,
io_bp_0_control_tmatch[0]}} == {_x_T_15[32:4],
_x_T_15[3:0]
| {_x_T_20 & io_bp_0_address[2],
_x_T_20,
_x_T_18,
io_bp_0_control_tmatch[0]}});
assign io_xcpt_if = x & ~io_bp_0_control_action;
assign io_xcpt_ld = r & ~io_bp_0_control_action;
assign io_xcpt_st = w & ~io_bp_0_control_action;
assign io_debug_if = x & io_bp_0_control_action;
assign io_debug_ld = r & io_bp_0_control_action;
assign io_debug_st = w & io_bp_0_control_action;
endmodule
hardware/generated/genesys2-soc-verilog/CLINT.sv
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// Generated by CIRCT firtool-1.151.0
module CLINT(
input clock,
reset,
output auto_int_out_0,
auto_int_out_1,
auto_in_a_ready,
input auto_in_a_valid,
input [2:0] auto_in_a_bits_opcode,
input [1:0] auto_in_a_bits_size,
input [5:0] auto_in_a_bits_source,
input [25:0] auto_in_a_bits_address,
input [7:0] auto_in_a_bits_mask,
input [63:0] auto_in_a_bits_data,
input auto_in_d_ready,
output auto_in_d_valid,
output [2:0] auto_in_d_bits_opcode,
output [1:0] auto_in_d_bits_size,
output [5:0] auto_in_d_bits_source,
output [63:0] auto_in_d_bits_data,
input io_rtcTick
);
wire out_woready_9;
wire out_woready_17;
reg [63:0] time_0;
reg [63:0] timecmp_0;
reg ipi_0;
wire _out_out_bits_data_WIRE_1 = auto_in_a_bits_address[13:3] == 11'h0;
wire _out_out_bits_data_WIRE_2 = &(auto_in_a_bits_address[13:3]);
wire valids_1_0 = out_woready_9 & auto_in_a_bits_mask[0];
wire valids_1_1 = out_woready_9 & auto_in_a_bits_mask[1];
wire valids_1_2 = out_woready_9 & auto_in_a_bits_mask[2];
wire valids_1_3 = out_woready_9 & auto_in_a_bits_mask[3];
wire valids_1_4 = out_woready_9 & auto_in_a_bits_mask[4];
wire valids_1_5 = out_woready_9 & auto_in_a_bits_mask[5];
wire valids_1_6 = out_woready_9 & auto_in_a_bits_mask[6];
wire valids_1_7 = out_woready_9 & auto_in_a_bits_mask[7];
wire valids_0 = out_woready_17 & auto_in_a_bits_mask[0];
wire valids_1 = out_woready_17 & auto_in_a_bits_mask[1];
wire valids_2 = out_woready_17 & auto_in_a_bits_mask[2];
wire valids_3 = out_woready_17 & auto_in_a_bits_mask[3];
wire valids_4 = out_woready_17 & auto_in_a_bits_mask[4];
wire valids_5 = out_woready_17 & auto_in_a_bits_mask[5];
wire valids_6 = out_woready_17 & auto_in_a_bits_mask[6];
wire valids_7 = out_woready_17 & auto_in_a_bits_mask[7];
wire [3:0] _out_backSel_T = 4'h1 << auto_in_a_bits_address[15:14];
wire _out_wofireMux_T_2 =
auto_in_a_valid & auto_in_d_ready & auto_in_a_bits_opcode != 3'h4;
assign out_woready_17 =
_out_wofireMux_T_2 & _out_backSel_T[1] & _out_out_bits_data_WIRE_1;
assign out_woready_9 =
_out_wofireMux_T_2 & _out_backSel_T[2] & _out_out_bits_data_WIRE_2;
wire [3:0] _GEN =
{{1'h1},
{_out_out_bits_data_WIRE_2},
{_out_out_bits_data_WIRE_1},
{_out_out_bits_data_WIRE_1}};
wire [3:0][63:0] _GEN_0 = {{64'h0}, {time_0}, {timecmp_0}, {{63'h0, ipi_0}}};
always @(posedge clock) begin
if (reset) begin
time_0 <= 64'h0;
ipi_0 <= 1'h0;
end
else begin
if (valids_1_0 | valids_1_1 | valids_1_2 | valids_1_3 | valids_1_4 | valids_1_5
| valids_1_6 | valids_1_7)
time_0 <=
{valids_1_7 ? auto_in_a_bits_data[63:56] : time_0[63:56],
valids_1_6 ? auto_in_a_bits_data[55:48] : time_0[55:48],
valids_1_5 ? auto_in_a_bits_data[47:40] : time_0[47:40],
valids_1_4 ? auto_in_a_bits_data[39:32] : time_0[39:32],
valids_1_3 ? auto_in_a_bits_data[31:24] : time_0[31:24],
valids_1_2 ? auto_in_a_bits_data[23:16] : time_0[23:16],
valids_1_1 ? auto_in_a_bits_data[15:8] : time_0[15:8],
valids_1_0 ? auto_in_a_bits_data[7:0] : time_0[7:0]};
else if (io_rtcTick)
time_0 <= time_0 + 64'h1;
if (_out_wofireMux_T_2 & _out_backSel_T[0] & _out_out_bits_data_WIRE_1
& auto_in_a_bits_mask[0])
ipi_0 <= auto_in_a_bits_data[0];
end
if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6
| valids_7)
timecmp_0 <=
{valids_7 ? auto_in_a_bits_data[63:56] : timecmp_0[63:56],
valids_6 ? auto_in_a_bits_data[55:48] : timecmp_0[55:48],
valids_5 ? auto_in_a_bits_data[47:40] : timecmp_0[47:40],
valids_4 ? auto_in_a_bits_data[39:32] : timecmp_0[39:32],
valids_3 ? auto_in_a_bits_data[31:24] : timecmp_0[31:24],
valids_2 ? auto_in_a_bits_data[23:16] : timecmp_0[23:16],
valids_1 ? auto_in_a_bits_data[15:8] : timecmp_0[15:8],
valids_0 ? auto_in_a_bits_data[7:0] : timecmp_0[7:0]};
end // always @(posedge)
assign auto_int_out_0 = ipi_0;
assign auto_int_out_1 = time_0 >= timecmp_0;
assign auto_in_a_ready = auto_in_d_ready;
assign auto_in_d_valid = auto_in_a_valid;
assign auto_in_d_bits_opcode = {2'h0, auto_in_a_bits_opcode == 3'h4};
assign auto_in_d_bits_size = auto_in_a_bits_size;
assign auto_in_d_bits_source = auto_in_a_bits_source;
assign auto_in_d_bits_data =
_GEN[auto_in_a_bits_address[15:14]] ? _GEN_0[auto_in_a_bits_address[15:14]] : 64'h0;
endmodule
hardware/generated/genesys2-soc-verilog/CLINTClockSinkDomain.sv
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// Generated by CIRCT firtool-1.151.0
module CLINTClockSinkDomain(
output auto_clint_in_a_ready,
input auto_clint_in_a_valid,
input [2:0] auto_clint_in_a_bits_opcode,
input [1:0] auto_clint_in_a_bits_size,
input [5:0] auto_clint_in_a_bits_source,
input [25:0] auto_clint_in_a_bits_address,
input [7:0] auto_clint_in_a_bits_mask,
input [63:0] auto_clint_in_a_bits_data,
input auto_clint_in_d_ready,
output auto_clint_in_d_valid,
output [2:0] auto_clint_in_d_bits_opcode,
output [1:0] auto_clint_in_d_bits_size,
output [5:0] auto_clint_in_d_bits_source,
output [63:0] auto_clint_in_d_bits_data,
output auto_int_in_clock_xing_out_sync_0,
auto_int_in_clock_xing_out_sync_1,
input auto_clock_in_clock,
auto_clock_in_reset,
tick,
output clock,
reset
);
wire _clint_auto_int_out_0;
wire _clint_auto_int_out_1;
CLINT clint (
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_int_out_0 (_clint_auto_int_out_0),
.auto_int_out_1 (_clint_auto_int_out_1),
.auto_in_a_ready (auto_clint_in_a_ready),
.auto_in_a_valid (auto_clint_in_a_valid),
.auto_in_a_bits_opcode (auto_clint_in_a_bits_opcode),
.auto_in_a_bits_size (auto_clint_in_a_bits_size),
.auto_in_a_bits_source (auto_clint_in_a_bits_source),
.auto_in_a_bits_address (auto_clint_in_a_bits_address),
.auto_in_a_bits_mask (auto_clint_in_a_bits_mask),
.auto_in_a_bits_data (auto_clint_in_a_bits_data),
.auto_in_d_ready (auto_clint_in_d_ready),
.auto_in_d_valid (auto_clint_in_d_valid),
.auto_in_d_bits_opcode (auto_clint_in_d_bits_opcode),
.auto_in_d_bits_size (auto_clint_in_d_bits_size),
.auto_in_d_bits_source (auto_clint_in_d_bits_source),
.auto_in_d_bits_data (auto_clint_in_d_bits_data),
.io_rtcTick (tick)
);
IntSyncCrossingSource_n1x2 intsource (
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_clint_auto_int_out_0),
.auto_in_1 (_clint_auto_int_out_1),
.auto_out_sync_0 (auto_int_in_clock_xing_out_sync_0),
.auto_out_sync_1 (auto_int_in_clock_xing_out_sync_1)
);
assign clock = auto_clock_in_clock;
assign reset = auto_clock_in_reset;
endmodule
hardware/generated/genesys2-soc-verilog/CSRFile.sv
+1463
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hardware/generated/genesys2-soc-verilog/ClockCrossingReg_w15.sv
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@@ -0,0 +1,16 @@
// Generated by CIRCT firtool-1.151.0
module ClockCrossingReg_w15(
input clock,
input [14:0] io_d,
output [14:0] io_q,
input io_en
);
reg [14:0] cdc_reg;
always @(posedge clock) begin
if (io_en)
cdc_reg <= io_d;
end // always @(posedge)
assign io_q = cdc_reg;
endmodule
hardware/generated/genesys2-soc-verilog/ClockCrossingReg_w43.sv
+16
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// Generated by CIRCT firtool-1.151.0
module ClockCrossingReg_w43(
input clock,
input [42:0] io_d,
output [42:0] io_q,
input io_en
);
reg [42:0] cdc_reg;
always @(posedge clock) begin
if (io_en)
cdc_reg <= io_d;
end // always @(posedge)
assign io_q = cdc_reg;
endmodule
hardware/generated/genesys2-soc-verilog/ClockCrossingReg_w55.sv
+16
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// Generated by CIRCT firtool-1.151.0
module ClockCrossingReg_w55(
input clock,
input [54:0] io_d,
output [54:0] io_q,
input io_en
);
reg [54:0] cdc_reg;
always @(posedge clock) begin
if (io_en)
cdc_reg <= io_d;
end // always @(posedge)
assign io_q = cdc_reg;
endmodule
hardware/generated/genesys2-soc-verilog/ClockGroup.sv
+12
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// Generated by CIRCT firtool-1.151.0
module ClockGroup(
input auto_in_member_sbus_0_clock,
auto_in_member_sbus_0_reset,
output auto_out_clock,
auto_out_reset
);
assign auto_out_clock = auto_in_member_sbus_0_clock;
assign auto_out_reset = auto_in_member_sbus_0_reset;
endmodule
hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_aggregator.sv
+30
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// Generated by CIRCT firtool-1.151.0
module ClockGroupAggregator_aggregator(
input auto_in_member_aggregator_3_clock,
auto_in_member_aggregator_3_reset,
auto_in_member_aggregator_2_clock,
auto_in_member_aggregator_2_reset,
auto_in_member_aggregator_1_clock,
auto_in_member_aggregator_1_reset,
auto_in_member_aggregator_0_clock,
auto_in_member_aggregator_0_reset,
output auto_out_member_sbus_3_clock,
auto_out_member_sbus_3_reset,
auto_out_member_sbus_2_clock,
auto_out_member_sbus_2_reset,
auto_out_member_sbus_1_clock,
auto_out_member_sbus_1_reset,
auto_out_member_sbus_0_clock,
auto_out_member_sbus_0_reset
);
assign auto_out_member_sbus_3_clock = auto_in_member_aggregator_3_clock;
assign auto_out_member_sbus_3_reset = auto_in_member_aggregator_3_reset;
assign auto_out_member_sbus_2_clock = auto_in_member_aggregator_2_clock;
assign auto_out_member_sbus_2_reset = auto_in_member_aggregator_2_reset;
assign auto_out_member_sbus_1_clock = auto_in_member_aggregator_1_clock;
assign auto_out_member_sbus_1_reset = auto_in_member_aggregator_1_reset;
assign auto_out_member_sbus_0_clock = auto_in_member_aggregator_0_clock;
assign auto_out_member_sbus_0_reset = auto_in_member_aggregator_0_reset;
endmodule
hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_cbus.sv
+18
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// Generated by CIRCT firtool-1.151.0
module ClockGroupAggregator_cbus(
input auto_in_member_cbus_1_clock,
auto_in_member_cbus_1_reset,
auto_in_member_cbus_0_clock,
auto_in_member_cbus_0_reset,
output auto_out_1_member_pbus_0_clock,
auto_out_1_member_pbus_0_reset,
auto_out_0_member_cbus_0_clock,
auto_out_0_member_cbus_0_reset
);
assign auto_out_1_member_pbus_0_clock = auto_in_member_cbus_1_clock;
assign auto_out_1_member_pbus_0_reset = auto_in_member_cbus_1_reset;
assign auto_out_0_member_cbus_0_clock = auto_in_member_cbus_0_clock;
assign auto_out_0_member_cbus_0_reset = auto_in_member_cbus_0_reset;
endmodule
hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_pbus.sv
+12
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// Generated by CIRCT firtool-1.151.0
module ClockGroupAggregator_pbus(
input auto_in_member_pbus_0_clock,
auto_in_member_pbus_0_reset,
output auto_out_member_pbus_0_clock,
auto_out_member_pbus_0_reset
);
assign auto_out_member_pbus_0_clock = auto_in_member_pbus_0_clock;
assign auto_out_member_pbus_0_reset = auto_in_member_pbus_0_reset;
endmodule
hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_sbus.sv
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// Generated by CIRCT firtool-1.151.0
module ClockGroupAggregator_sbus(
input auto_in_member_sbus_3_clock,
auto_in_member_sbus_3_reset,
auto_in_member_sbus_2_clock,
auto_in_member_sbus_2_reset,
auto_in_member_sbus_1_clock,
auto_in_member_sbus_1_reset,
auto_in_member_sbus_0_clock,
auto_in_member_sbus_0_reset,
output auto_out_2_member_fbus_0_clock,
auto_out_2_member_fbus_0_reset,
auto_out_1_member_cbus_1_clock,
auto_out_1_member_cbus_1_reset,
auto_out_1_member_cbus_0_clock,
auto_out_1_member_cbus_0_reset,
auto_out_0_member_sbus_0_clock,
auto_out_0_member_sbus_0_reset
);
assign auto_out_2_member_fbus_0_clock = auto_in_member_sbus_3_clock;
assign auto_out_2_member_fbus_0_reset = auto_in_member_sbus_3_reset;
assign auto_out_1_member_cbus_1_clock = auto_in_member_sbus_2_clock;
assign auto_out_1_member_cbus_1_reset = auto_in_member_sbus_2_reset;
assign auto_out_1_member_cbus_0_clock = auto_in_member_sbus_1_clock;
assign auto_out_1_member_cbus_0_reset = auto_in_member_sbus_1_reset;
assign auto_out_0_member_sbus_0_clock = auto_in_member_sbus_0_clock;
assign auto_out_0_member_sbus_0_reset = auto_in_member_sbus_0_reset;
endmodule
hardware/generated/genesys2-soc-verilog/ClockSinkDomain.sv
+67
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// Generated by CIRCT firtool-1.151.0
module ClockSinkDomain(
input auto_int_bus_anon_in_0,
auto_int_bus_anon_in_1,
auto_int_bus_anon_in_2,
auto_int_bus_anon_in_3,
auto_int_bus_anon_in_4,
auto_int_bus_anon_in_5,
auto_int_bus_anon_in_6,
auto_int_bus_anon_in_7,
auto_int_bus_anon_in_8,
auto_int_bus_anon_in_9,
output auto_int_bus_anon_out_0,
auto_int_bus_anon_out_1,
auto_int_bus_anon_out_2,
auto_int_bus_anon_out_3,
auto_int_bus_anon_out_4,
auto_int_bus_anon_out_5,
auto_int_bus_anon_out_6,
auto_int_bus_anon_out_7,
auto_int_bus_anon_out_8,
auto_int_bus_anon_out_9,
auto_int_bus_anon_out_10,
input auto_with_no_name_in_0,
auto_clock_in_clock,
auto_clock_in_reset
);
wire _intsource_auto_out_sync_0;
wire _intsink_auto_out_0;
IntXbar_i2_o1 int_bus (
.auto_anon_in_1_0 (_intsink_auto_out_0),
.auto_anon_in_0_0 (auto_int_bus_anon_in_0),
.auto_anon_in_0_1 (auto_int_bus_anon_in_1),
.auto_anon_in_0_2 (auto_int_bus_anon_in_2),
.auto_anon_in_0_3 (auto_int_bus_anon_in_3),
.auto_anon_in_0_4 (auto_int_bus_anon_in_4),
.auto_anon_in_0_5 (auto_int_bus_anon_in_5),
.auto_anon_in_0_6 (auto_int_bus_anon_in_6),
.auto_anon_in_0_7 (auto_int_bus_anon_in_7),
.auto_anon_in_0_8 (auto_int_bus_anon_in_8),
.auto_anon_in_0_9 (auto_int_bus_anon_in_9),
.auto_anon_out_0 (auto_int_bus_anon_out_0),
.auto_anon_out_1 (auto_int_bus_anon_out_1),
.auto_anon_out_2 (auto_int_bus_anon_out_2),
.auto_anon_out_3 (auto_int_bus_anon_out_3),
.auto_anon_out_4 (auto_int_bus_anon_out_4),
.auto_anon_out_5 (auto_int_bus_anon_out_5),
.auto_anon_out_6 (auto_int_bus_anon_out_6),
.auto_anon_out_7 (auto_int_bus_anon_out_7),
.auto_anon_out_8 (auto_int_bus_anon_out_8),
.auto_anon_out_9 (auto_int_bus_anon_out_9),
.auto_anon_out_10 (auto_int_bus_anon_out_10)
);
IntSyncAsyncCrossingSink_n1x1 intsink (
.clock (auto_clock_in_clock),
.auto_in_sync_0 (_intsource_auto_out_sync_0),
.auto_out_0 (_intsink_auto_out_0)
);
IntSyncCrossingSource_n1x1 intsource (
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (auto_with_no_name_in_0),
.auto_out_sync_0 (_intsource_auto_out_sync_0)
);
endmodule
hardware/generated/genesys2-soc-verilog/CompareRecFN.sv
+35
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// Generated by CIRCT firtool-1.151.0
module CompareRecFN(
input [64:0] io_a,
io_b,
input io_signaling,
output io_lt,
io_eq,
output [4:0] io_exceptionFlags
);
wire _rawA_out_sig_T = |(io_a[63:61]);
wire rawA_isSpecial = &(io_a[63:62]);
wire rawA_isNaN = rawA_isSpecial & io_a[61];
wire _rawB_out_sig_T = |(io_b[63:61]);
wire rawB_isSpecial = &(io_b[63:62]);
wire rawB_isNaN = rawB_isSpecial & io_b[61];
wire ordered = ~rawA_isNaN & ~rawB_isNaN;
wire bothInfs = rawA_isSpecial & ~(io_a[61]) & rawB_isSpecial & ~(io_b[61]);
wire bothZeros = ~_rawA_out_sig_T & ~_rawB_out_sig_T;
wire eqExps = io_a[63:52] == io_b[63:52];
wire [52:0] _GEN = {_rawA_out_sig_T, io_a[51:0]};
wire [52:0] _GEN_0 = {_rawB_out_sig_T, io_b[51:0]};
wire common_ltMags =
$signed({1'h0, io_a[63:52]}) < $signed({1'h0, io_b[63:52]}) | eqExps & _GEN < _GEN_0;
wire common_eqMags = eqExps & _GEN == _GEN_0;
assign io_lt =
ordered & ~bothZeros
& (io_a[64] & ~(io_b[64]) | ~bothInfs
& (io_a[64] & ~common_ltMags & ~common_eqMags | ~(io_b[64]) & common_ltMags));
assign io_eq =
ordered & (bothZeros | io_a[64] == io_b[64] & (bothInfs | common_eqMags));
assign io_exceptionFlags =
{rawA_isNaN & ~(io_a[51]) | rawB_isNaN & ~(io_b[51]) | io_signaling & ~ordered, 4'h0};
endmodule
hardware/generated/genesys2-soc-verilog/DCache.sv
+1245
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hardware/generated/genesys2-soc-verilog/DCacheDataArray.sv
+30
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@@ -0,0 +1,30 @@
// Generated by CIRCT firtool-1.151.0
module DCacheDataArray(
input clock,
io_req_valid,
input [19:0] io_req_bits_addr,
input io_req_bits_write,
input [63:0] io_req_bits_wdata,
input [7:0] io_req_bits_eccMask,
output [63:0] io_resp_0
);
wire rockettile_dcache_data_arrays_0_rdata_data_en;
wire rockettile_dcache_data_arrays_0_rdata_MPORT_en;
assign rockettile_dcache_data_arrays_0_rdata_MPORT_en =
io_req_valid & io_req_bits_write;
assign rockettile_dcache_data_arrays_0_rdata_data_en =
io_req_valid & ~io_req_bits_write;
rockettile_dcache_data_arrays_0_131072x64 rockettile_dcache_data_arrays_0_ext (
.RW0_addr (io_req_bits_addr[19:3]),
.RW0_en
(rockettile_dcache_data_arrays_0_rdata_data_en
| rockettile_dcache_data_arrays_0_rdata_MPORT_en),
.RW0_clk (clock),
.RW0_wmode (io_req_bits_write),
.RW0_wdata (io_req_bits_wdata),
.RW0_rdata (io_resp_0),
.RW0_wmask (io_req_bits_eccMask)
);
endmodule
hardware/generated/genesys2-soc-verilog/DMIToTL.sv
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// Generated by CIRCT firtool-1.151.0
module DMIToTL(
input auto_out_a_ready,
output auto_out_a_valid,
output [2:0] auto_out_a_bits_opcode,
output [8:0] auto_out_a_bits_address,
output [31:0] auto_out_a_bits_data,
output auto_out_d_ready,
input auto_out_d_valid,
auto_out_d_bits_denied,
input [31:0] auto_out_d_bits_data,
input auto_out_d_bits_corrupt,
output io_dmi_req_ready,
input io_dmi_req_valid,
input [6:0] io_dmi_req_bits_addr,
input [31:0] io_dmi_req_bits_data,
input [1:0] io_dmi_req_bits_op,
input io_dmi_resp_ready,
output io_dmi_resp_valid,
output [31:0] io_dmi_resp_bits_data,
output [1:0] io_dmi_resp_bits_resp
);
wire _GEN = io_dmi_req_bits_op == 2'h2;
wire _GEN_0 = io_dmi_req_bits_op == 2'h1;
assign auto_out_a_valid = io_dmi_req_valid;
assign auto_out_a_bits_opcode = _GEN ? 3'h0 : {_GEN_0, 2'h0};
assign auto_out_a_bits_address = _GEN | _GEN_0 ? {io_dmi_req_bits_addr, 2'h0} : 9'h48;
assign auto_out_a_bits_data = _GEN ? io_dmi_req_bits_data : 32'h0;
assign auto_out_d_ready = io_dmi_resp_ready;
assign io_dmi_req_ready = auto_out_a_ready;
assign io_dmi_resp_valid = auto_out_d_valid;
assign io_dmi_resp_bits_data = auto_out_d_bits_data;
assign io_dmi_resp_bits_resp = {1'h0, auto_out_d_bits_corrupt | auto_out_d_bits_denied};
endmodule
hardware/generated/genesys2-soc-verilog/DTLB.sv
+383
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// Generated by CIRCT firtool-1.151.0
module DTLB(
input [33:0] io_req_bits_vaddr,
input [1:0] io_req_bits_size,
input [4:0] io_req_bits_cmd,
input [1:0] io_req_bits_prv,
output [31:0] io_resp_paddr,
output io_resp_pf_ld,
io_resp_pf_st,
io_resp_ae_ld,
io_resp_ae_st,
io_resp_ma_ld,
io_resp_ma_st,
io_resp_cacheable,
input io_ptw_status_debug,
io_ptw_pmp_0_cfg_l,
input [1:0] io_ptw_pmp_0_cfg_a,
input io_ptw_pmp_0_cfg_w,
io_ptw_pmp_0_cfg_r,
input [29:0] io_ptw_pmp_0_addr,
input [31:0] io_ptw_pmp_0_mask,
input io_ptw_pmp_1_cfg_l,
input [1:0] io_ptw_pmp_1_cfg_a,
input io_ptw_pmp_1_cfg_w,
io_ptw_pmp_1_cfg_r,
input [29:0] io_ptw_pmp_1_addr,
input [31:0] io_ptw_pmp_1_mask,
input io_ptw_pmp_2_cfg_l,
input [1:0] io_ptw_pmp_2_cfg_a,
input io_ptw_pmp_2_cfg_w,
io_ptw_pmp_2_cfg_r,
input [29:0] io_ptw_pmp_2_addr,
input [31:0] io_ptw_pmp_2_mask,
input io_ptw_pmp_3_cfg_l,
input [1:0] io_ptw_pmp_3_cfg_a,
input io_ptw_pmp_3_cfg_w,
io_ptw_pmp_3_cfg_r,
input [29:0] io_ptw_pmp_3_addr,
input [31:0] io_ptw_pmp_3_mask,
input io_ptw_pmp_4_cfg_l,
input [1:0] io_ptw_pmp_4_cfg_a,
input io_ptw_pmp_4_cfg_w,
io_ptw_pmp_4_cfg_r,
input [29:0] io_ptw_pmp_4_addr,
input [31:0] io_ptw_pmp_4_mask,
input io_ptw_pmp_5_cfg_l,
input [1:0] io_ptw_pmp_5_cfg_a,
input io_ptw_pmp_5_cfg_w,
io_ptw_pmp_5_cfg_r,
input [29:0] io_ptw_pmp_5_addr,
input [31:0] io_ptw_pmp_5_mask,
input io_ptw_pmp_6_cfg_l,
input [1:0] io_ptw_pmp_6_cfg_a,
input io_ptw_pmp_6_cfg_w,
io_ptw_pmp_6_cfg_r,
input [29:0] io_ptw_pmp_6_addr,
input [31:0] io_ptw_pmp_6_mask,
input io_ptw_pmp_7_cfg_l,
input [1:0] io_ptw_pmp_7_cfg_a,
input io_ptw_pmp_7_cfg_w,
io_ptw_pmp_7_cfg_r,
input [29:0] io_ptw_pmp_7_addr,
input [31:0] io_ptw_pmp_7_mask
);
wire _pma_io_resp_r;
wire _pma_io_resp_w;
wire _pma_io_resp_pp;
wire _pma_io_resp_al;
wire _pma_io_resp_aa;
wire _pma_io_resp_eff;
wire _pmp_io_r;
wire _pmp_io_w;
wire deny_access_to_debug = ~io_ptw_status_debug & io_req_bits_vaddr[33:12] == 22'h0;
wire misaligned = |(io_req_bits_vaddr[3:0] & (4'h1 << io_req_bits_size) - 4'h1);
wire _cmd_read_T_2 = io_req_bits_cmd == 5'h6;
wire _cmd_write_T_3 = io_req_bits_cmd == 5'h7;
wire _cmd_write_T_5 = io_req_bits_cmd == 5'h4;
wire _cmd_write_T_6 = io_req_bits_cmd == 5'h9;
wire _cmd_write_T_7 = io_req_bits_cmd == 5'hA;
wire _cmd_write_T_8 = io_req_bits_cmd == 5'hB;
wire _cmd_write_T_12 = io_req_bits_cmd == 5'h8;
wire _cmd_write_T_13 = io_req_bits_cmd == 5'hC;
wire _cmd_write_T_14 = io_req_bits_cmd == 5'hD;
wire _cmd_write_T_15 = io_req_bits_cmd == 5'hE;
wire _cmd_write_T_16 = io_req_bits_cmd == 5'hF;
wire cmd_put_partial = io_req_bits_cmd == 5'h11;
wire cmd_read =
io_req_bits_cmd == 5'h0 | io_req_bits_cmd == 5'h10 | _cmd_read_T_2 | _cmd_write_T_3
| _cmd_write_T_5 | _cmd_write_T_6 | _cmd_write_T_7 | _cmd_write_T_8 | _cmd_write_T_12
| _cmd_write_T_13 | _cmd_write_T_14 | _cmd_write_T_15 | _cmd_write_T_16;
wire cmd_write =
io_req_bits_cmd == 5'h1 | cmd_put_partial | _cmd_write_T_3 | _cmd_write_T_5
| _cmd_write_T_6 | _cmd_write_T_7 | _cmd_write_T_8 | _cmd_write_T_12 | _cmd_write_T_13
| _cmd_write_T_14 | _cmd_write_T_15 | _cmd_write_T_16;
wire ae_array = misaligned & _pma_io_resp_eff | _cmd_read_T_2 | _cmd_write_T_3;
PMPChecker_s3 pmp (
.io_prv (io_req_bits_prv),
.io_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l),
.io_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a),
.io_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w),
.io_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r),
.io_pmp_0_addr (io_ptw_pmp_0_addr),
.io_pmp_0_mask (io_ptw_pmp_0_mask),
.io_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l),
.io_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a),
.io_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w),
.io_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r),
.io_pmp_1_addr (io_ptw_pmp_1_addr),
.io_pmp_1_mask (io_ptw_pmp_1_mask),
.io_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l),
.io_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a),
.io_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w),
.io_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r),
.io_pmp_2_addr (io_ptw_pmp_2_addr),
.io_pmp_2_mask (io_ptw_pmp_2_mask),
.io_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l),
.io_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a),
.io_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w),
.io_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r),
.io_pmp_3_addr (io_ptw_pmp_3_addr),
.io_pmp_3_mask (io_ptw_pmp_3_mask),
.io_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l),
.io_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a),
.io_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w),
.io_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r),
.io_pmp_4_addr (io_ptw_pmp_4_addr),
.io_pmp_4_mask (io_ptw_pmp_4_mask),
.io_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l),
.io_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a),
.io_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w),
.io_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r),
.io_pmp_5_addr (io_ptw_pmp_5_addr),
.io_pmp_5_mask (io_ptw_pmp_5_mask),
.io_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l),
.io_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a),
.io_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w),
.io_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r),
.io_pmp_6_addr (io_ptw_pmp_6_addr),
.io_pmp_6_mask (io_ptw_pmp_6_mask),
.io_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l),
.io_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a),
.io_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w),
.io_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r),
.io_pmp_7_addr (io_ptw_pmp_7_addr),
.io_pmp_7_mask (io_ptw_pmp_7_mask),
.io_addr (io_req_bits_vaddr[31:0]),
.io_size (io_req_bits_size),
.io_r (_pmp_io_r),
.io_w (_pmp_io_w)
);
PMAChecker pma (
.io_paddr (io_req_bits_vaddr),
.io_resp_r (_pma_io_resp_r),
.io_resp_w (_pma_io_resp_w),
.io_resp_pp (_pma_io_resp_pp),
.io_resp_al (_pma_io_resp_al),
.io_resp_aa (_pma_io_resp_aa),
.io_resp_x (/* unused */),
.io_resp_eff (_pma_io_resp_eff)
);
OptimizationBarrier_TLBEntryData entries_barrier (
.io_x_u (1'h0),
.io_x_ae_ptw (1'h0),
.io_x_ae_final (1'h0),
.io_x_pf (1'h0),
.io_x_gf (1'h0),
.io_x_sw (1'h0),
.io_x_sx (1'h0),
.io_x_sr (1'h0),
.io_x_pw (1'h0),
.io_x_px (1'h0),
.io_x_pr (1'h0),
.io_x_ppp (1'h0),
.io_x_pal (1'h0),
.io_x_paa (1'h0),
.io_x_eff (1'h0),
.io_x_c (1'h0),
.io_y_u (/* unused */),
.io_y_ae_ptw (/* unused */),
.io_y_ae_final (/* unused */),
.io_y_pf (/* unused */),
.io_y_gf (/* unused */),
.io_y_sw (/* unused */),
.io_y_sx (/* unused */),
.io_y_sr (/* unused */),
.io_y_pw (/* unused */),
.io_y_px (/* unused */),
.io_y_pr (/* unused */),
.io_y_ppp (/* unused */),
.io_y_pal (/* unused */),
.io_y_paa (/* unused */),
.io_y_eff (/* unused */),
.io_y_c (/* unused */)
);
OptimizationBarrier_TLBEntryData entries_barrier_1 (
.io_x_u (1'h0),
.io_x_ae_ptw (1'h0),
.io_x_ae_final (1'h0),
.io_x_pf (1'h0),
.io_x_gf (1'h0),
.io_x_sw (1'h0),
.io_x_sx (1'h0),
.io_x_sr (1'h0),
.io_x_pw (1'h0),
.io_x_px (1'h0),
.io_x_pr (1'h0),
.io_x_ppp (1'h0),
.io_x_pal (1'h0),
.io_x_paa (1'h0),
.io_x_eff (1'h0),
.io_x_c (1'h0),
.io_y_u (/* unused */),
.io_y_ae_ptw (/* unused */),
.io_y_ae_final (/* unused */),
.io_y_pf (/* unused */),
.io_y_gf (/* unused */),
.io_y_sw (/* unused */),
.io_y_sx (/* unused */),
.io_y_sr (/* unused */),
.io_y_pw (/* unused */),
.io_y_px (/* unused */),
.io_y_pr (/* unused */),
.io_y_ppp (/* unused */),
.io_y_pal (/* unused */),
.io_y_paa (/* unused */),
.io_y_eff (/* unused */),
.io_y_c (/* unused */)
);
OptimizationBarrier_TLBEntryData entries_barrier_2 (
.io_x_u (1'h0),
.io_x_ae_ptw (1'h0),
.io_x_ae_final (1'h0),
.io_x_pf (1'h0),
.io_x_gf (1'h0),
.io_x_sw (1'h0),
.io_x_sx (1'h0),
.io_x_sr (1'h0),
.io_x_pw (1'h0),
.io_x_px (1'h0),
.io_x_pr (1'h0),
.io_x_ppp (1'h0),
.io_x_pal (1'h0),
.io_x_paa (1'h0),
.io_x_eff (1'h0),
.io_x_c (1'h0),
.io_y_u (/* unused */),
.io_y_ae_ptw (/* unused */),
.io_y_ae_final (/* unused */),
.io_y_pf (/* unused */),
.io_y_gf (/* unused */),
.io_y_sw (/* unused */),
.io_y_sx (/* unused */),
.io_y_sr (/* unused */),
.io_y_pw (/* unused */),
.io_y_px (/* unused */),
.io_y_pr (/* unused */),
.io_y_ppp (/* unused */),
.io_y_pal (/* unused */),
.io_y_paa (/* unused */),
.io_y_eff (/* unused */),
.io_y_c (/* unused */)
);
OptimizationBarrier_TLBEntryData entries_barrier_3 (
.io_x_u (1'h0),
.io_x_ae_ptw (1'h0),
.io_x_ae_final (1'h0),
.io_x_pf (1'h0),
.io_x_gf (1'h0),
.io_x_sw (1'h0),
.io_x_sx (1'h0),
.io_x_sr (1'h0),
.io_x_pw (1'h0),
.io_x_px (1'h0),
.io_x_pr (1'h0),
.io_x_ppp (1'h0),
.io_x_pal (1'h0),
.io_x_paa (1'h0),
.io_x_eff (1'h0),
.io_x_c (1'h0),
.io_y_u (/* unused */),
.io_y_ae_ptw (/* unused */),
.io_y_ae_final (/* unused */),
.io_y_pf (/* unused */),
.io_y_gf (/* unused */),
.io_y_sw (/* unused */),
.io_y_sx (/* unused */),
.io_y_sr (/* unused */),
.io_y_pw (/* unused */),
.io_y_px (/* unused */),
.io_y_pr (/* unused */),
.io_y_ppp (/* unused */),
.io_y_pal (/* unused */),
.io_y_paa (/* unused */),
.io_y_eff (/* unused */),
.io_y_c (/* unused */)
);
OptimizationBarrier_TLBEntryData entries_barrier_4 (
.io_x_u (1'h0),
.io_x_ae_ptw (1'h0),
.io_x_ae_final (1'h0),
.io_x_pf (1'h0),
.io_x_gf (1'h0),
.io_x_sw (1'h0),
.io_x_sx (1'h0),
.io_x_sr (1'h0),
.io_x_pw (1'h0),
.io_x_px (1'h0),
.io_x_pr (1'h0),
.io_x_ppp (1'h0),
.io_x_pal (1'h0),
.io_x_paa (1'h0),
.io_x_eff (1'h0),
.io_x_c (1'h0),
.io_y_u (/* unused */),
.io_y_ae_ptw (/* unused */),
.io_y_ae_final (/* unused */),
.io_y_pf (/* unused */),
.io_y_gf (/* unused */),
.io_y_sw (/* unused */),
.io_y_sx (/* unused */),
.io_y_sr (/* unused */),
.io_y_pw (/* unused */),
.io_y_px (/* unused */),
.io_y_pr (/* unused */),
.io_y_ppp (/* unused */),
.io_y_pal (/* unused */),
.io_y_paa (/* unused */),
.io_y_eff (/* unused */),
.io_y_c (/* unused */)
);
OptimizationBarrier_TLBEntryData entries_barrier_5 (
.io_x_u (1'h0),
.io_x_ae_ptw (1'h0),
.io_x_ae_final (1'h0),
.io_x_pf (1'h0),
.io_x_gf (1'h0),
.io_x_sw (1'h0),
.io_x_sx (1'h0),
.io_x_sr (1'h0),
.io_x_pw (1'h0),
.io_x_px (1'h0),
.io_x_pr (1'h0),
.io_x_ppp (1'h0),
.io_x_pal (1'h0),
.io_x_paa (1'h0),
.io_x_eff (1'h0),
.io_x_c (1'h0),
.io_y_u (/* unused */),
.io_y_ae_ptw (/* unused */),
.io_y_ae_final (/* unused */),
.io_y_pf (/* unused */),
.io_y_gf (/* unused */),
.io_y_sw (/* unused */),
.io_y_sx (/* unused */),
.io_y_sr (/* unused */),
.io_y_pw (/* unused */),
.io_y_px (/* unused */),
.io_y_pr (/* unused */),
.io_y_ppp (/* unused */),
.io_y_pal (/* unused */),
.io_y_paa (/* unused */),
.io_y_eff (/* unused */),
.io_y_c (/* unused */)
);
assign io_resp_paddr = io_req_bits_vaddr[31:0];
assign io_resp_pf_ld = 1'h0;
assign io_resp_pf_st = 1'h0;
assign io_resp_ae_ld =
cmd_read & (ae_array | ~(_pma_io_resp_r & ~deny_access_to_debug & _pmp_io_r));
assign io_resp_ae_st =
(cmd_write | io_req_bits_cmd == 5'h5 | io_req_bits_cmd == 5'h17)
& (ae_array | ~(_pma_io_resp_w & ~deny_access_to_debug & _pmp_io_w)) | cmd_put_partial
& ~_pma_io_resp_pp
| (_cmd_write_T_5 | _cmd_write_T_6 | _cmd_write_T_7 | _cmd_write_T_8)
& ~_pma_io_resp_al
| (_cmd_write_T_12 | _cmd_write_T_13 | _cmd_write_T_14 | _cmd_write_T_15
| _cmd_write_T_16) & ~_pma_io_resp_aa;
assign io_resp_ma_ld = misaligned & cmd_read;
assign io_resp_ma_st = misaligned & cmd_write;
assign io_resp_cacheable = 1'h0;
endmodule
hardware/generated/genesys2-soc-verilog/DivSqrtRawFN_small.sv
+171
View File
@@ -0,0 +1,171 @@
// Generated by CIRCT firtool-1.151.0
module DivSqrtRawFN_small(
input clock,
reset,
output io_inReady,
input io_inValid,
io_sqrtOp,
io_a_isNaN,
io_a_isInf,
io_a_isZero,
io_a_sign,
input [9:0] io_a_sExp,
input [24:0] io_a_sig,
input io_b_isNaN,
io_b_isInf,
io_b_isZero,
io_b_sign,
input [9:0] io_b_sExp,
input [24:0] io_b_sig,
input [2:0] io_roundingMode,
output io_rawOutValid_div,
io_rawOutValid_sqrt,
output [2:0] io_roundingModeOut,
output io_invalidExc,
io_infiniteExc,
io_rawOut_isNaN,
io_rawOut_isInf,
io_rawOut_isZero,
io_rawOut_sign,
output [9:0] io_rawOut_sExp,
output [26:0] io_rawOut_sig
);
reg [4:0] cycleNum;
reg inReady;
reg rawOutValid;
reg sqrtOp_Z;
reg majorExc_Z;
reg isNaN_Z;
reg isInf_Z;
reg isZero_Z;
reg sign_Z;
reg [9:0] sExp_Z;
reg [23:0] fractB_Z;
reg [2:0] roundingMode_Z;
reg [25:0] rem_Z;
reg notZeroRem_Z;
reg [25:0] sigX_Z;
always @(posedge clock) begin
automatic logic oddSqrt_S = io_sqrtOp & io_a_sExp[0];
automatic logic entering;
automatic logic _sigX_Z_T_7;
automatic logic [26:0] rem;
automatic logic [25:0] _trialTerm_T_3 =
inReady & ~io_sqrtOp ? {io_b_sig, 1'h0} : 26'h0;
automatic logic [25:0] _trialTerm_T_9;
automatic logic [28:0] trialRem;
automatic logic newBit;
automatic logic _GEN;
entering = inReady & io_inValid;
_sigX_Z_T_7 = inReady & oddSqrt_S;
rem =
{1'h0, inReady & ~oddSqrt_S ? {io_a_sig, 1'h0} : 26'h0}
| (_sigX_Z_T_7 ? {io_a_sig[23:22] - 2'h1, io_a_sig[21:0], 3'h0} : 27'h0)
| (inReady ? 27'h0 : {rem_Z, 1'h0});
_trialTerm_T_9 =
{_trialTerm_T_3[25],
_trialTerm_T_3[24:0] | {inReady & io_sqrtOp & ~(io_a_sExp[0]), 24'h0}}
| (_sigX_Z_T_7 ? 26'h2800000 : 26'h0);
trialRem =
{2'h0, rem}
- {2'h0,
{1'h0,
_trialTerm_T_9[25],
{_trialTerm_T_9[24], _trialTerm_T_9[23:0] | (inReady ? 24'h0 : fractB_Z)}
| {~inReady & ~sqrtOp_Z, 24'h0}}
| (~inReady & sqrtOp_Z ? {sigX_Z, 1'h0} : 27'h0)};
newBit = $signed(trialRem) > -29'sh1;
_GEN = entering | ~inReady;
if (reset) begin
cycleNum <= 5'h0;
inReady <= 1'h1;
rawOutValid <= 1'h0;
end
else if ((|cycleNum) | entering) begin
automatic logic specialCaseA_S = io_a_isNaN | io_a_isInf | io_a_isZero;
automatic logic normalCase_S =
io_sqrtOp
? ~specialCaseA_S & ~io_a_sign
: ~specialCaseA_S & ~(io_b_isNaN | io_b_isInf | io_b_isZero);
automatic logic skipCycle2 = cycleNum == 5'h3 & sigX_Z[25];
automatic logic [4:0] _cycleNum_T_15;
_cycleNum_T_15 =
{4'h0, entering & ~normalCase_S}
| (entering & normalCase_S ? (io_sqrtOp ? {4'hC, ~(io_a_sExp[0])} : 5'h1A) : 5'h0)
| (entering | skipCycle2 ? 5'h0 : cycleNum - 5'h1);
cycleNum <= {_cycleNum_T_15[4:1], _cycleNum_T_15[0] | skipCycle2};
inReady <=
entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 5'h1 < 5'h2
| skipCycle2;
rawOutValid <=
entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 5'h1 == 5'h1
| skipCycle2;
end
if (entering) begin
automatic logic notSigNaNIn_invalidExc_S_div =
io_a_isZero & io_b_isZero | io_a_isInf & io_b_isInf;
automatic logic notSigNaNIn_invalidExc_S_sqrt =
~io_a_isNaN & ~io_a_isZero & io_a_sign;
automatic logic [10:0] sExpQuot_S_div =
{io_a_sExp[9], io_a_sExp} + {{3{io_b_sExp[8]}}, ~(io_b_sExp[7:0])};
sqrtOp_Z <= io_sqrtOp;
majorExc_Z <=
io_sqrtOp
? io_a_isNaN & ~(io_a_sig[22]) | notSigNaNIn_invalidExc_S_sqrt
: io_a_isNaN & ~(io_a_sig[22]) | io_b_isNaN & ~(io_b_sig[22])
| notSigNaNIn_invalidExc_S_div | ~io_a_isNaN & ~io_a_isInf & io_b_isZero;
isNaN_Z <=
io_sqrtOp
? io_a_isNaN | notSigNaNIn_invalidExc_S_sqrt
: io_a_isNaN | io_b_isNaN | notSigNaNIn_invalidExc_S_div;
isInf_Z <= ~io_sqrtOp & io_b_isZero | io_a_isInf;
isZero_Z <= ~io_sqrtOp & io_b_isInf | io_a_isZero;
sign_Z <= io_a_sign ^ ~io_sqrtOp & io_b_sign;
sExp_Z <=
io_sqrtOp
? {io_a_sExp[9], io_a_sExp[9:1]} + 10'h80
: {$signed(sExpQuot_S_div) > 11'sh1BF ? 4'h6 : sExpQuot_S_div[9:6],
sExpQuot_S_div[5:0]};
roundingMode_Z <= io_roundingMode;
end
if (entering | ~inReady & sqrtOp_Z) begin
automatic logic [23:0] _fractB_Z_T_4 =
inReady & ~io_sqrtOp ? {io_b_sig[22:0], 1'h0} : 24'h0;
automatic logic _fractB_Z_T_10 = inReady & io_sqrtOp;
automatic logic [23:0] _fractB_Z_T_20 =
{_fractB_Z_T_4[23], _fractB_Z_T_4[22:0] | {_fractB_Z_T_10 & io_a_sExp[0], 22'h0}}
| {_fractB_Z_T_10 & ~(io_a_sExp[0]), 23'h0};
fractB_Z <=
{_fractB_Z_T_20[23], _fractB_Z_T_20[22:0] | (inReady ? 23'h0 : fractB_Z[23:1])};
end
if (_GEN) begin
automatic logic [25:0] _sigX_Z_T_3;
automatic logic [24:0] _GEN_0;
automatic logic [31:0] _bitMask_T = 32'h1 << cycleNum;
_sigX_Z_T_3 = inReady & ~io_sqrtOp ? {newBit, 25'h0} : 26'h0;
_GEN_0 = _sigX_Z_T_3[24:0] | {inReady & io_sqrtOp, 24'h0};
rem_Z <= newBit ? trialRem[25:0] : rem[25:0];
sigX_Z <=
{_sigX_Z_T_3[25],
_GEN_0[24],
_GEN_0[23:0] | (_sigX_Z_T_7 ? {newBit, 23'h0} : 24'h0)}
| (inReady ? 26'h0 : sigX_Z) | (~inReady & newBit ? _bitMask_T[27:2] : 26'h0);
end
if (_GEN & (inReady | newBit))
notZeroRem_Z <= |trialRem;
end // always @(posedge)
assign io_inReady = inReady;
assign io_rawOutValid_div = rawOutValid & ~sqrtOp_Z;
assign io_rawOutValid_sqrt = rawOutValid & sqrtOp_Z;
assign io_roundingModeOut = roundingMode_Z;
assign io_invalidExc = majorExc_Z & isNaN_Z;
assign io_infiniteExc = majorExc_Z & ~isNaN_Z;
assign io_rawOut_isNaN = isNaN_Z;
assign io_rawOut_isInf = isInf_Z;
assign io_rawOut_isZero = isZero_Z;
assign io_rawOut_sign = sign_Z;
assign io_rawOut_sExp = sExp_Z;
assign io_rawOut_sig = {sigX_Z, notZeroRem_Z};
endmodule
hardware/generated/genesys2-soc-verilog/DivSqrtRawFN_small_1.sv
+172
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@@ -0,0 +1,172 @@
// Generated by CIRCT firtool-1.151.0
module DivSqrtRawFN_small_1(
input clock,
reset,
output io_inReady,
input io_inValid,
io_sqrtOp,
io_a_isNaN,
io_a_isInf,
io_a_isZero,
io_a_sign,
input [12:0] io_a_sExp,
input [53:0] io_a_sig,
input io_b_isNaN,
io_b_isInf,
io_b_isZero,
io_b_sign,
input [12:0] io_b_sExp,
input [53:0] io_b_sig,
input [2:0] io_roundingMode,
output io_rawOutValid_div,
io_rawOutValid_sqrt,
output [2:0] io_roundingModeOut,
output io_invalidExc,
io_infiniteExc,
io_rawOut_isNaN,
io_rawOut_isInf,
io_rawOut_isZero,
io_rawOut_sign,
output [12:0] io_rawOut_sExp,
output [55:0] io_rawOut_sig
);
reg [5:0] cycleNum;
reg inReady;
reg rawOutValid;
reg sqrtOp_Z;
reg majorExc_Z;
reg isNaN_Z;
reg isInf_Z;
reg isZero_Z;
reg sign_Z;
reg [12:0] sExp_Z;
reg [52:0] fractB_Z;
reg [2:0] roundingMode_Z;
reg [54:0] rem_Z;
reg notZeroRem_Z;
reg [54:0] sigX_Z;
always @(posedge clock) begin
automatic logic oddSqrt_S = io_sqrtOp & io_a_sExp[0];
automatic logic entering;
automatic logic _sigX_Z_T_7;
automatic logic [55:0] rem;
automatic logic [54:0] _trialTerm_T_3 =
inReady & ~io_sqrtOp ? {io_b_sig, 1'h0} : 55'h0;
automatic logic [54:0] _trialTerm_T_9;
automatic logic [57:0] trialRem;
automatic logic newBit;
automatic logic _GEN;
entering = inReady & io_inValid;
_sigX_Z_T_7 = inReady & oddSqrt_S;
rem =
{1'h0, inReady & ~oddSqrt_S ? {io_a_sig, 1'h0} : 55'h0}
| (_sigX_Z_T_7 ? {io_a_sig[52:51] - 2'h1, io_a_sig[50:0], 3'h0} : 56'h0)
| (inReady ? 56'h0 : {rem_Z, 1'h0});
_trialTerm_T_9 =
{_trialTerm_T_3[54],
_trialTerm_T_3[53:0] | {inReady & io_sqrtOp & ~(io_a_sExp[0]), 53'h0}}
| (_sigX_Z_T_7 ? 55'h50000000000000 : 55'h0);
trialRem =
{2'h0, rem}
- {2'h0,
{1'h0,
_trialTerm_T_9[54],
{_trialTerm_T_9[53], _trialTerm_T_9[52:0] | (inReady ? 53'h0 : fractB_Z)}
| {~inReady & ~sqrtOp_Z, 53'h0}}
| (~inReady & sqrtOp_Z ? {sigX_Z, 1'h0} : 56'h0)};
newBit = $signed(trialRem) > -58'sh1;
_GEN = entering | ~inReady;
if (reset) begin
cycleNum <= 6'h0;
inReady <= 1'h1;
rawOutValid <= 1'h0;
end
else if ((|cycleNum) | entering) begin
automatic logic specialCaseA_S = io_a_isNaN | io_a_isInf | io_a_isZero;
automatic logic normalCase_S =
io_sqrtOp
? ~specialCaseA_S & ~io_a_sign
: ~specialCaseA_S & ~(io_b_isNaN | io_b_isInf | io_b_isZero);
automatic logic skipCycle2 = cycleNum == 6'h3 & sigX_Z[54];
automatic logic [5:0] _cycleNum_T_15;
_cycleNum_T_15 =
{5'h0, entering & ~normalCase_S}
| (entering & normalCase_S
? (io_sqrtOp ? (io_a_sExp[0] ? 6'h35 : 6'h36) : 6'h37)
: 6'h0) | (entering | skipCycle2 ? 6'h0 : cycleNum - 6'h1);
cycleNum <= {_cycleNum_T_15[5:1], _cycleNum_T_15[0] | skipCycle2};
inReady <=
entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 6'h1 < 6'h2
| skipCycle2;
rawOutValid <=
entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 6'h1 == 6'h1
| skipCycle2;
end
if (entering) begin
automatic logic notSigNaNIn_invalidExc_S_div =
io_a_isZero & io_b_isZero | io_a_isInf & io_b_isInf;
automatic logic notSigNaNIn_invalidExc_S_sqrt =
~io_a_isNaN & ~io_a_isZero & io_a_sign;
automatic logic [13:0] sExpQuot_S_div =
{io_a_sExp[12], io_a_sExp} + {{3{io_b_sExp[11]}}, ~(io_b_sExp[10:0])};
sqrtOp_Z <= io_sqrtOp;
majorExc_Z <=
io_sqrtOp
? io_a_isNaN & ~(io_a_sig[51]) | notSigNaNIn_invalidExc_S_sqrt
: io_a_isNaN & ~(io_a_sig[51]) | io_b_isNaN & ~(io_b_sig[51])
| notSigNaNIn_invalidExc_S_div | ~io_a_isNaN & ~io_a_isInf & io_b_isZero;
isNaN_Z <=
io_sqrtOp
? io_a_isNaN | notSigNaNIn_invalidExc_S_sqrt
: io_a_isNaN | io_b_isNaN | notSigNaNIn_invalidExc_S_div;
isInf_Z <= ~io_sqrtOp & io_b_isZero | io_a_isInf;
isZero_Z <= ~io_sqrtOp & io_b_isInf | io_a_isZero;
sign_Z <= io_a_sign ^ ~io_sqrtOp & io_b_sign;
sExp_Z <=
io_sqrtOp
? {io_a_sExp[12], io_a_sExp[12:1]} + 13'h400
: {$signed(sExpQuot_S_div) > 14'shDFF ? 4'h6 : sExpQuot_S_div[12:9],
sExpQuot_S_div[8:0]};
roundingMode_Z <= io_roundingMode;
end
if (entering | ~inReady & sqrtOp_Z) begin
automatic logic [52:0] _fractB_Z_T_4 =
inReady & ~io_sqrtOp ? {io_b_sig[51:0], 1'h0} : 53'h0;
automatic logic _fractB_Z_T_10 = inReady & io_sqrtOp;
automatic logic [52:0] _fractB_Z_T_20 =
{_fractB_Z_T_4[52], _fractB_Z_T_4[51:0] | {_fractB_Z_T_10 & io_a_sExp[0], 51'h0}}
| {_fractB_Z_T_10 & ~(io_a_sExp[0]), 52'h0};
fractB_Z <=
{_fractB_Z_T_20[52], _fractB_Z_T_20[51:0] | (inReady ? 52'h0 : fractB_Z[52:1])};
end
if (_GEN) begin
automatic logic [54:0] _sigX_Z_T_3;
automatic logic [53:0] _GEN_0;
automatic logic [63:0] _bitMask_T = 64'h1 << cycleNum;
_sigX_Z_T_3 = inReady & ~io_sqrtOp ? {newBit, 54'h0} : 55'h0;
_GEN_0 = _sigX_Z_T_3[53:0] | {inReady & io_sqrtOp, 53'h0};
rem_Z <= newBit ? trialRem[54:0] : rem[54:0];
sigX_Z <=
{_sigX_Z_T_3[54],
_GEN_0[53],
_GEN_0[52:0] | (_sigX_Z_T_7 ? {newBit, 52'h0} : 53'h0)}
| (inReady ? 55'h0 : sigX_Z) | (~inReady & newBit ? _bitMask_T[56:2] : 55'h0);
end
if (_GEN & (inReady | newBit))
notZeroRem_Z <= |trialRem;
end // always @(posedge)
assign io_inReady = inReady;
assign io_rawOutValid_div = rawOutValid & ~sqrtOp_Z;
assign io_rawOutValid_sqrt = rawOutValid & sqrtOp_Z;
assign io_roundingModeOut = roundingMode_Z;
assign io_invalidExc = majorExc_Z & isNaN_Z;
assign io_infiniteExc = majorExc_Z & ~isNaN_Z;
assign io_rawOut_isNaN = isNaN_Z;
assign io_rawOut_isInf = isInf_Z;
assign io_rawOut_isZero = isZero_Z;
assign io_rawOut_sign = sign_Z;
assign io_rawOut_sExp = sExp_Z;
assign io_rawOut_sig = {sigX_Z, notZeroRem_Z};
endmodule
hardware/generated/genesys2-soc-verilog/DivSqrtRecFNToRaw_small.sv
+60
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@@ -0,0 +1,60 @@
// Generated by CIRCT firtool-1.151.0
module DivSqrtRecFNToRaw_small(
input clock,
reset,
output io_inReady,
input io_inValid,
io_sqrtOp,
input [32:0] io_a,
io_b,
input [2:0] io_roundingMode,
output io_rawOutValid_div,
io_rawOutValid_sqrt,
output [2:0] io_roundingModeOut,
output io_invalidExc,
io_infiniteExc,
io_rawOut_isNaN,
io_rawOut_isInf,
io_rawOut_isZero,
io_rawOut_sign,
output [9:0] io_rawOut_sExp,
output [26:0] io_rawOut_sig
);
wire _divSqrtRawFN_io_a_out_sig_T = |(io_a[31:29]);
wire divSqrtRawFN_io_a_isSpecial = &(io_a[31:30]);
wire _divSqrtRawFN_io_b_out_sig_T = |(io_b[31:29]);
wire divSqrtRawFN_io_b_isSpecial = &(io_b[31:30]);
DivSqrtRawFN_small divSqrtRawFN (
.clock (clock),
.reset (reset),
.io_inReady (io_inReady),
.io_inValid (io_inValid),
.io_sqrtOp (io_sqrtOp),
.io_a_isNaN (divSqrtRawFN_io_a_isSpecial & io_a[29]),
.io_a_isInf (divSqrtRawFN_io_a_isSpecial & ~(io_a[29])),
.io_a_isZero (~_divSqrtRawFN_io_a_out_sig_T),
.io_a_sign (io_a[32]),
.io_a_sExp ({1'h0, io_a[31:23]}),
.io_a_sig ({1'h0, _divSqrtRawFN_io_a_out_sig_T, io_a[22:0]}),
.io_b_isNaN (divSqrtRawFN_io_b_isSpecial & io_b[29]),
.io_b_isInf (divSqrtRawFN_io_b_isSpecial & ~(io_b[29])),
.io_b_isZero (~_divSqrtRawFN_io_b_out_sig_T),
.io_b_sign (io_b[32]),
.io_b_sExp ({1'h0, io_b[31:23]}),
.io_b_sig ({1'h0, _divSqrtRawFN_io_b_out_sig_T, io_b[22:0]}),
.io_roundingMode (io_roundingMode),
.io_rawOutValid_div (io_rawOutValid_div),
.io_rawOutValid_sqrt (io_rawOutValid_sqrt),
.io_roundingModeOut (io_roundingModeOut),
.io_invalidExc (io_invalidExc),
.io_infiniteExc (io_infiniteExc),
.io_rawOut_isNaN (io_rawOut_isNaN),
.io_rawOut_isInf (io_rawOut_isInf),
.io_rawOut_isZero (io_rawOut_isZero),
.io_rawOut_sign (io_rawOut_sign),
.io_rawOut_sExp (io_rawOut_sExp),
.io_rawOut_sig (io_rawOut_sig)
);
endmodule
hardware/generated/genesys2-soc-verilog/DivSqrtRecFNToRaw_small_1.sv
+60
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@@ -0,0 +1,60 @@
// Generated by CIRCT firtool-1.151.0
module DivSqrtRecFNToRaw_small_1(
input clock,
reset,
output io_inReady,
input io_inValid,
io_sqrtOp,
input [64:0] io_a,
io_b,
input [2:0] io_roundingMode,
output io_rawOutValid_div,
io_rawOutValid_sqrt,
output [2:0] io_roundingModeOut,
output io_invalidExc,
io_infiniteExc,
io_rawOut_isNaN,
io_rawOut_isInf,
io_rawOut_isZero,
io_rawOut_sign,
output [12:0] io_rawOut_sExp,
output [55:0] io_rawOut_sig
);
wire _divSqrtRawFN_io_a_out_sig_T = |(io_a[63:61]);
wire divSqrtRawFN_io_a_isSpecial = &(io_a[63:62]);
wire _divSqrtRawFN_io_b_out_sig_T = |(io_b[63:61]);
wire divSqrtRawFN_io_b_isSpecial = &(io_b[63:62]);
DivSqrtRawFN_small_1 divSqrtRawFN (
.clock (clock),
.reset (reset),
.io_inReady (io_inReady),
.io_inValid (io_inValid),
.io_sqrtOp (io_sqrtOp),
.io_a_isNaN (divSqrtRawFN_io_a_isSpecial & io_a[61]),
.io_a_isInf (divSqrtRawFN_io_a_isSpecial & ~(io_a[61])),
.io_a_isZero (~_divSqrtRawFN_io_a_out_sig_T),
.io_a_sign (io_a[64]),
.io_a_sExp ({1'h0, io_a[63:52]}),
.io_a_sig ({1'h0, _divSqrtRawFN_io_a_out_sig_T, io_a[51:0]}),
.io_b_isNaN (divSqrtRawFN_io_b_isSpecial & io_b[61]),
.io_b_isInf (divSqrtRawFN_io_b_isSpecial & ~(io_b[61])),
.io_b_isZero (~_divSqrtRawFN_io_b_out_sig_T),
.io_b_sign (io_b[64]),
.io_b_sExp ({1'h0, io_b[63:52]}),
.io_b_sig ({1'h0, _divSqrtRawFN_io_b_out_sig_T, io_b[51:0]}),
.io_roundingMode (io_roundingMode),
.io_rawOutValid_div (io_rawOutValid_div),
.io_rawOutValid_sqrt (io_rawOutValid_sqrt),
.io_roundingModeOut (io_roundingModeOut),
.io_invalidExc (io_invalidExc),
.io_infiniteExc (io_infiniteExc),
.io_rawOut_isNaN (io_rawOut_isNaN),
.io_rawOut_isInf (io_rawOut_isInf),
.io_rawOut_isZero (io_rawOut_isZero),
.io_rawOut_sign (io_rawOut_sign),
.io_rawOut_sExp (io_rawOut_sExp),
.io_rawOut_sig (io_rawOut_sig)
);
endmodule
hardware/generated/genesys2-soc-verilog/DivSqrtRecFN_small.sv
+61
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@@ -0,0 +1,61 @@
// Generated by CIRCT firtool-1.151.0
module DivSqrtRecFN_small(
input clock,
reset,
output io_inReady,
input io_inValid,
io_sqrtOp,
input [32:0] io_a,
io_b,
input [2:0] io_roundingMode,
output io_outValid_div,
io_outValid_sqrt,
output [32:0] io_out,
output [4:0] io_exceptionFlags
);
wire [2:0] _divSqrtRecFNToRaw_io_roundingModeOut;
wire _divSqrtRecFNToRaw_io_invalidExc;
wire _divSqrtRecFNToRaw_io_infiniteExc;
wire _divSqrtRecFNToRaw_io_rawOut_isNaN;
wire _divSqrtRecFNToRaw_io_rawOut_isInf;
wire _divSqrtRecFNToRaw_io_rawOut_isZero;
wire _divSqrtRecFNToRaw_io_rawOut_sign;
wire [9:0] _divSqrtRecFNToRaw_io_rawOut_sExp;
wire [26:0] _divSqrtRecFNToRaw_io_rawOut_sig;
DivSqrtRecFNToRaw_small divSqrtRecFNToRaw (
.clock (clock),
.reset (reset),
.io_inReady (io_inReady),
.io_inValid (io_inValid),
.io_sqrtOp (io_sqrtOp),
.io_a (io_a),
.io_b (io_b),
.io_roundingMode (io_roundingMode),
.io_rawOutValid_div (io_outValid_div),
.io_rawOutValid_sqrt (io_outValid_sqrt),
.io_roundingModeOut (_divSqrtRecFNToRaw_io_roundingModeOut),
.io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),
.io_rawOut_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),
.io_rawOut_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),
.io_rawOut_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),
.io_rawOut_sign (_divSqrtRecFNToRaw_io_rawOut_sign),
.io_rawOut_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),
.io_rawOut_sig (_divSqrtRecFNToRaw_io_rawOut_sig)
);
RoundRawFNToRecFN roundRawFNToRecFN (
.io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),
.io_in_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),
.io_in_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),
.io_in_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),
.io_in_sign (_divSqrtRecFNToRaw_io_rawOut_sign),
.io_in_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),
.io_in_sig (_divSqrtRecFNToRaw_io_rawOut_sig),
.io_roundingMode (_divSqrtRecFNToRaw_io_roundingModeOut),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule
hardware/generated/genesys2-soc-verilog/DivSqrtRecFN_small_1.sv
+61
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@@ -0,0 +1,61 @@
// Generated by CIRCT firtool-1.151.0
module DivSqrtRecFN_small_1(
input clock,
reset,
output io_inReady,
input io_inValid,
io_sqrtOp,
input [64:0] io_a,
io_b,
input [2:0] io_roundingMode,
output io_outValid_div,
io_outValid_sqrt,
output [64:0] io_out,
output [4:0] io_exceptionFlags
);
wire [2:0] _divSqrtRecFNToRaw_io_roundingModeOut;
wire _divSqrtRecFNToRaw_io_invalidExc;
wire _divSqrtRecFNToRaw_io_infiniteExc;
wire _divSqrtRecFNToRaw_io_rawOut_isNaN;
wire _divSqrtRecFNToRaw_io_rawOut_isInf;
wire _divSqrtRecFNToRaw_io_rawOut_isZero;
wire _divSqrtRecFNToRaw_io_rawOut_sign;
wire [12:0] _divSqrtRecFNToRaw_io_rawOut_sExp;
wire [55:0] _divSqrtRecFNToRaw_io_rawOut_sig;
DivSqrtRecFNToRaw_small_1 divSqrtRecFNToRaw (
.clock (clock),
.reset (reset),
.io_inReady (io_inReady),
.io_inValid (io_inValid),
.io_sqrtOp (io_sqrtOp),
.io_a (io_a),
.io_b (io_b),
.io_roundingMode (io_roundingMode),
.io_rawOutValid_div (io_outValid_div),
.io_rawOutValid_sqrt (io_outValid_sqrt),
.io_roundingModeOut (_divSqrtRecFNToRaw_io_roundingModeOut),
.io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),
.io_rawOut_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),
.io_rawOut_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),
.io_rawOut_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),
.io_rawOut_sign (_divSqrtRecFNToRaw_io_rawOut_sign),
.io_rawOut_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),
.io_rawOut_sig (_divSqrtRecFNToRaw_io_rawOut_sig)
);
RoundRawFNToRecFN_1 roundRawFNToRecFN (
.io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),
.io_in_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),
.io_in_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),
.io_in_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),
.io_in_sign (_divSqrtRecFNToRaw_io_rawOut_sign),
.io_in_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),
.io_in_sig (_divSqrtRecFNToRaw_io_rawOut_sig),
.io_roundingMode (_divSqrtRecFNToRaw_io_roundingModeOut),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule
hardware/generated/genesys2-soc-verilog/ErrorDeviceWrapper.sv
+104
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@@ -0,0 +1,104 @@
// Generated by CIRCT firtool-1.151.0
module ErrorDeviceWrapper(
input clock,
reset,
output auto_buffer_in_a_ready,
input auto_buffer_in_a_valid,
input [2:0] auto_buffer_in_a_bits_opcode,
auto_buffer_in_a_bits_param,
input [3:0] auto_buffer_in_a_bits_size,
input [1:0] auto_buffer_in_a_bits_source,
input [13:0] auto_buffer_in_a_bits_address,
input [7:0] auto_buffer_in_a_bits_mask,
input [63:0] auto_buffer_in_a_bits_data,
input auto_buffer_in_a_bits_corrupt,
auto_buffer_in_d_ready,
output auto_buffer_in_d_valid,
output [2:0] auto_buffer_in_d_bits_opcode,
output [1:0] auto_buffer_in_d_bits_param,
output [3:0] auto_buffer_in_d_bits_size,
output [1:0] auto_buffer_in_d_bits_source,
output auto_buffer_in_d_bits_sink,
auto_buffer_in_d_bits_denied,
output [63:0] auto_buffer_in_d_bits_data,
output auto_buffer_in_d_bits_corrupt
);
wire _buffer_auto_out_a_valid;
wire [2:0] _buffer_auto_out_a_bits_opcode;
wire [2:0] _buffer_auto_out_a_bits_param;
wire [3:0] _buffer_auto_out_a_bits_size;
wire [1:0] _buffer_auto_out_a_bits_source;
wire [13:0] _buffer_auto_out_a_bits_address;
wire [7:0] _buffer_auto_out_a_bits_mask;
wire [63:0] _buffer_auto_out_a_bits_data;
wire _buffer_auto_out_a_bits_corrupt;
wire _buffer_auto_out_d_ready;
wire _error_auto_in_a_ready;
wire _error_auto_in_d_valid;
wire [2:0] _error_auto_in_d_bits_opcode;
wire [3:0] _error_auto_in_d_bits_size;
wire [1:0] _error_auto_in_d_bits_source;
wire _error_auto_in_d_bits_corrupt;
TLError error (
.clock (clock),
.reset (reset),
.auto_in_a_ready (_error_auto_in_a_ready),
.auto_in_a_valid (_buffer_auto_out_a_valid),
.auto_in_a_bits_opcode (_buffer_auto_out_a_bits_opcode),
.auto_in_a_bits_param (_buffer_auto_out_a_bits_param),
.auto_in_a_bits_size (_buffer_auto_out_a_bits_size),
.auto_in_a_bits_source (_buffer_auto_out_a_bits_source),
.auto_in_a_bits_address (_buffer_auto_out_a_bits_address),
.auto_in_a_bits_mask (_buffer_auto_out_a_bits_mask),
.auto_in_a_bits_data (_buffer_auto_out_a_bits_data),
.auto_in_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt),
.auto_in_d_ready (_buffer_auto_out_d_ready),
.auto_in_d_valid (_error_auto_in_d_valid),
.auto_in_d_bits_opcode (_error_auto_in_d_bits_opcode),
.auto_in_d_bits_size (_error_auto_in_d_bits_size),
.auto_in_d_bits_source (_error_auto_in_d_bits_source),
.auto_in_d_bits_corrupt (_error_auto_in_d_bits_corrupt)
);
TLBuffer_a14d64s2k1z4u buffer (
.clock (clock),
.reset (reset),
.auto_in_a_ready (auto_buffer_in_a_ready),
.auto_in_a_valid (auto_buffer_in_a_valid),
.auto_in_a_bits_opcode (auto_buffer_in_a_bits_opcode),
.auto_in_a_bits_param (auto_buffer_in_a_bits_param),
.auto_in_a_bits_size (auto_buffer_in_a_bits_size),
.auto_in_a_bits_source (auto_buffer_in_a_bits_source),
.auto_in_a_bits_address (auto_buffer_in_a_bits_address),
.auto_in_a_bits_mask (auto_buffer_in_a_bits_mask),
.auto_in_a_bits_data (auto_buffer_in_a_bits_data),
.auto_in_a_bits_corrupt (auto_buffer_in_a_bits_corrupt),
.auto_in_d_ready (auto_buffer_in_d_ready),
.auto_in_d_valid (auto_buffer_in_d_valid),
.auto_in_d_bits_opcode (auto_buffer_in_d_bits_opcode),
.auto_in_d_bits_param (auto_buffer_in_d_bits_param),
.auto_in_d_bits_size (auto_buffer_in_d_bits_size),
.auto_in_d_bits_source (auto_buffer_in_d_bits_source),
.auto_in_d_bits_sink (auto_buffer_in_d_bits_sink),
.auto_in_d_bits_denied (auto_buffer_in_d_bits_denied),
.auto_in_d_bits_data (auto_buffer_in_d_bits_data),
.auto_in_d_bits_corrupt (auto_buffer_in_d_bits_corrupt),
.auto_out_a_ready (_error_auto_in_a_ready),
.auto_out_a_valid (_buffer_auto_out_a_valid),
.auto_out_a_bits_opcode (_buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_buffer_auto_out_a_bits_param),
.auto_out_a_bits_size (_buffer_auto_out_a_bits_size),
.auto_out_a_bits_source (_buffer_auto_out_a_bits_source),
.auto_out_a_bits_address (_buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask (_buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data (_buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready (_buffer_auto_out_d_ready),
.auto_out_d_valid (_error_auto_in_d_valid),
.auto_out_d_bits_opcode (_error_auto_in_d_bits_opcode),
.auto_out_d_bits_size (_error_auto_in_d_bits_size),
.auto_out_d_bits_source (_error_auto_in_d_bits_source),
.auto_out_d_bits_corrupt (_error_auto_in_d_bits_corrupt)
);
endmodule
hardware/generated/genesys2-soc-verilog/FPGAGPSClockSinkDomain.sv
+131
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@@ -0,0 +1,131 @@
// Generated by CIRCT firtool-1.151.0
module FPGAGPSClockSinkDomain(
output auto_tl2apb_in_a_ready,
input auto_tl2apb_in_a_valid,
input [2:0] auto_tl2apb_in_a_bits_opcode,
auto_tl2apb_in_a_bits_param,
input [1:0] auto_tl2apb_in_a_bits_size,
input [6:0] auto_tl2apb_in_a_bits_source,
input [28:0] auto_tl2apb_in_a_bits_address,
input auto_tl2apb_in_a_bits_user_amba_prot_bufferable,
auto_tl2apb_in_a_bits_user_amba_prot_modifiable,
auto_tl2apb_in_a_bits_user_amba_prot_readalloc,
auto_tl2apb_in_a_bits_user_amba_prot_writealloc,
auto_tl2apb_in_a_bits_user_amba_prot_privileged,
auto_tl2apb_in_a_bits_user_amba_prot_secure,
auto_tl2apb_in_a_bits_user_amba_prot_fetch,
input [3:0] auto_tl2apb_in_a_bits_mask,
input [31:0] auto_tl2apb_in_a_bits_data,
input auto_tl2apb_in_a_bits_corrupt,
auto_tl2apb_in_d_ready,
output auto_tl2apb_in_d_valid,
output [2:0] auto_tl2apb_in_d_bits_opcode,
output [1:0] auto_tl2apb_in_d_bits_param,
auto_tl2apb_in_d_bits_size,
output [6:0] auto_tl2apb_in_d_bits_source,
output auto_tl2apb_in_d_bits_sink,
auto_tl2apb_in_d_bits_denied,
output [31:0] auto_tl2apb_in_d_bits_data,
output auto_tl2apb_in_d_bits_corrupt,
auto_dev_pps_out_out,
input [3:0] auto_dev_rf_data_in,
input auto_dev_afe_clock_in,
auto_dev_tracking_clock_in,
auto_dev_acq_clock_in,
output auto_dev_int_out_0,
auto_dev_int_out_1,
auto_dev_int_out_2,
auto_dev_int_out_3,
auto_dev_int_out_4,
auto_dev_int_out_5,
auto_dev_int_out_6,
auto_dev_int_out_7,
auto_dev_int_out_8,
auto_dev_int_out_9,
input auto_clock_in_clock,
auto_clock_in_reset
);
wire _tl2apb_auto_out_psel;
wire _tl2apb_auto_out_penable;
wire _tl2apb_auto_out_pwrite;
wire [28:0] _tl2apb_auto_out_paddr;
wire [31:0] _tl2apb_auto_out_pwdata;
wire _dev_auto_in_pready;
wire _dev_auto_in_pslverr;
wire [31:0] _dev_auto_in_prdata;
APBGpsBlock dev (
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_pps_out_out (auto_dev_pps_out_out),
.auto_rf_data_in (auto_dev_rf_data_in),
.auto_afe_clock_in (auto_dev_afe_clock_in),
.auto_tracking_clock_in (auto_dev_tracking_clock_in),
.auto_acq_clock_in (auto_dev_acq_clock_in),
.auto_in_psel (_tl2apb_auto_out_psel),
.auto_in_penable (_tl2apb_auto_out_penable),
.auto_in_pwrite (_tl2apb_auto_out_pwrite),
.auto_in_paddr (_tl2apb_auto_out_paddr),
.auto_in_pwdata (_tl2apb_auto_out_pwdata),
.auto_in_pready (_dev_auto_in_pready),
.auto_in_pslverr (_dev_auto_in_pslverr),
.auto_in_prdata (_dev_auto_in_prdata),
.auto_int_out_0 (auto_dev_int_out_0),
.auto_int_out_1 (auto_dev_int_out_1),
.auto_int_out_2 (auto_dev_int_out_2),
.auto_int_out_3 (auto_dev_int_out_3),
.auto_int_out_4 (auto_dev_int_out_4),
.auto_int_out_5 (auto_dev_int_out_5),
.auto_int_out_6 (auto_dev_int_out_6),
.auto_int_out_7 (auto_dev_int_out_7),
.auto_int_out_8 (auto_dev_int_out_8),
.auto_int_out_9 (auto_dev_int_out_9)
);
TLToAPB tl2apb (
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_a_ready (auto_tl2apb_in_a_ready),
.auto_in_a_valid (auto_tl2apb_in_a_valid),
.auto_in_a_bits_opcode (auto_tl2apb_in_a_bits_opcode),
.auto_in_a_bits_param (auto_tl2apb_in_a_bits_param),
.auto_in_a_bits_size (auto_tl2apb_in_a_bits_size),
.auto_in_a_bits_source (auto_tl2apb_in_a_bits_source),
.auto_in_a_bits_address (auto_tl2apb_in_a_bits_address),
.auto_in_a_bits_user_amba_prot_bufferable
(auto_tl2apb_in_a_bits_user_amba_prot_bufferable),
.auto_in_a_bits_user_amba_prot_modifiable
(auto_tl2apb_in_a_bits_user_amba_prot_modifiable),
.auto_in_a_bits_user_amba_prot_readalloc
(auto_tl2apb_in_a_bits_user_amba_prot_readalloc),
.auto_in_a_bits_user_amba_prot_writealloc
(auto_tl2apb_in_a_bits_user_amba_prot_writealloc),
.auto_in_a_bits_user_amba_prot_privileged
(auto_tl2apb_in_a_bits_user_amba_prot_privileged),
.auto_in_a_bits_user_amba_prot_secure
(auto_tl2apb_in_a_bits_user_amba_prot_secure),
.auto_in_a_bits_user_amba_prot_fetch
(auto_tl2apb_in_a_bits_user_amba_prot_fetch),
.auto_in_a_bits_mask (auto_tl2apb_in_a_bits_mask),
.auto_in_a_bits_data (auto_tl2apb_in_a_bits_data),
.auto_in_a_bits_corrupt (auto_tl2apb_in_a_bits_corrupt),
.auto_in_d_ready (auto_tl2apb_in_d_ready),
.auto_in_d_valid (auto_tl2apb_in_d_valid),
.auto_in_d_bits_opcode (auto_tl2apb_in_d_bits_opcode),
.auto_in_d_bits_param (auto_tl2apb_in_d_bits_param),
.auto_in_d_bits_size (auto_tl2apb_in_d_bits_size),
.auto_in_d_bits_source (auto_tl2apb_in_d_bits_source),
.auto_in_d_bits_sink (auto_tl2apb_in_d_bits_sink),
.auto_in_d_bits_denied (auto_tl2apb_in_d_bits_denied),
.auto_in_d_bits_data (auto_tl2apb_in_d_bits_data),
.auto_in_d_bits_corrupt (auto_tl2apb_in_d_bits_corrupt),
.auto_out_psel (_tl2apb_auto_out_psel),
.auto_out_penable (_tl2apb_auto_out_penable),
.auto_out_pwrite (_tl2apb_auto_out_pwrite),
.auto_out_paddr (_tl2apb_auto_out_paddr),
.auto_out_pwdata (_tl2apb_auto_out_pwdata),
.auto_out_pready (_dev_auto_in_pready),
.auto_out_pslverr (_dev_auto_in_pslverr),
.auto_out_prdata (_dev_auto_in_prdata)
);
endmodule
hardware/generated/genesys2-soc-verilog/FPGASPIClockSinkDomain.sv
+50
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@@ -0,0 +1,50 @@
// Generated by CIRCT firtool-1.151.0
module FPGASPIClockSinkDomain(
output auto_dev_in_a_ready,
input auto_dev_in_a_valid,
input [2:0] auto_dev_in_a_bits_opcode,
input [1:0] auto_dev_in_a_bits_size,
input [5:0] auto_dev_in_a_bits_source,
input [28:0] auto_dev_in_a_bits_address,
input [7:0] auto_dev_in_a_bits_mask,
input [63:0] auto_dev_in_a_bits_data,
input auto_dev_in_d_ready,
output auto_dev_in_d_valid,
output [2:0] auto_dev_in_d_bits_opcode,
output [1:0] auto_dev_in_d_bits_size,
output [5:0] auto_dev_in_d_bits_source,
output [63:0] auto_dev_in_d_bits_data,
output [3:0] auto_dev_dq_oe_out,
auto_dev_dq_out_out,
input [3:0] auto_dev_dq_in_in,
output auto_dev_csn_out,
auto_dev_sck_out,
input auto_clock_in_clock,
auto_clock_in_reset
);
TLFpgaSPI dev (
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_a_ready (auto_dev_in_a_ready),
.auto_in_a_valid (auto_dev_in_a_valid),
.auto_in_a_bits_opcode (auto_dev_in_a_bits_opcode),
.auto_in_a_bits_size (auto_dev_in_a_bits_size),
.auto_in_a_bits_source (auto_dev_in_a_bits_source),
.auto_in_a_bits_address (auto_dev_in_a_bits_address),
.auto_in_a_bits_mask (auto_dev_in_a_bits_mask),
.auto_in_a_bits_data (auto_dev_in_a_bits_data),
.auto_in_d_ready (auto_dev_in_d_ready),
.auto_in_d_valid (auto_dev_in_d_valid),
.auto_in_d_bits_opcode (auto_dev_in_d_bits_opcode),
.auto_in_d_bits_size (auto_dev_in_d_bits_size),
.auto_in_d_bits_source (auto_dev_in_d_bits_source),
.auto_in_d_bits_data (auto_dev_in_d_bits_data),
.auto_dq_oe_out (auto_dev_dq_oe_out),
.auto_dq_out_out (auto_dev_dq_out_out),
.auto_dq_in_in (auto_dev_dq_in_in),
.auto_csn_out (auto_dev_csn_out),
.auto_sck_out (auto_dev_sck_out)
);
endmodule
hardware/generated/genesys2-soc-verilog/FPGAUARTClockSinkDomain.sv
+44
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@@ -0,0 +1,44 @@
// Generated by CIRCT firtool-1.151.0
module FPGAUARTClockSinkDomain(
output auto_dev_in_a_ready,
input auto_dev_in_a_valid,
input [2:0] auto_dev_in_a_bits_opcode,
input [1:0] auto_dev_in_a_bits_size,
input [5:0] auto_dev_in_a_bits_source,
input [28:0] auto_dev_in_a_bits_address,
input [7:0] auto_dev_in_a_bits_mask,
input [63:0] auto_dev_in_a_bits_data,
input auto_dev_in_d_ready,
output auto_dev_in_d_valid,
output [2:0] auto_dev_in_d_bits_opcode,
output [1:0] auto_dev_in_d_bits_size,
output [5:0] auto_dev_in_d_bits_source,
output [63:0] auto_dev_in_d_bits_data,
output auto_dev_txd_out,
input auto_dev_rxd_in,
auto_clock_in_clock,
auto_clock_in_reset
);
TLFpgaUART dev (
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_a_ready (auto_dev_in_a_ready),
.auto_in_a_valid (auto_dev_in_a_valid),
.auto_in_a_bits_opcode (auto_dev_in_a_bits_opcode),
.auto_in_a_bits_size (auto_dev_in_a_bits_size),
.auto_in_a_bits_source (auto_dev_in_a_bits_source),
.auto_in_a_bits_address (auto_dev_in_a_bits_address),
.auto_in_a_bits_mask (auto_dev_in_a_bits_mask),
.auto_in_a_bits_data (auto_dev_in_a_bits_data),
.auto_in_d_ready (auto_dev_in_d_ready),
.auto_in_d_valid (auto_dev_in_d_valid),
.auto_in_d_bits_opcode (auto_dev_in_d_bits_opcode),
.auto_in_d_bits_size (auto_dev_in_d_bits_size),
.auto_in_d_bits_source (auto_dev_in_d_bits_source),
.auto_in_d_bits_data (auto_dev_in_d_bits_data),
.auto_txd_out (auto_dev_txd_out),
.auto_rxd_in (auto_dev_rxd_in)
);
endmodule
hardware/generated/genesys2-soc-verilog/FPToFP.sv
+92
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@@ -0,0 +1,92 @@
// Generated by CIRCT firtool-1.151.0
module FPToFP(
input clock,
reset,
io_in_valid,
io_in_bits_ren2,
input [1:0] io_in_bits_typeTagOut,
input io_in_bits_wflags,
input [2:0] io_in_bits_rm,
input [64:0] io_in_bits_in1,
io_in_bits_in2,
output [64:0] io_out_bits_data,
output [4:0] io_out_bits_exc,
input io_lt
);
wire [32:0] _narrower_io_out;
wire [4:0] _narrower_io_exceptionFlags;
reg in_pipe_v;
reg in_pipe_b_ren2;
reg [1:0] in_pipe_b_typeTagOut;
reg in_pipe_b_wflags;
reg [2:0] in_pipe_b_rm;
reg [64:0] in_pipe_b_in1;
reg [64:0] in_pipe_b_in2;
wire isnan1 = &(in_pipe_b_in1[63:61]);
wire isnan2 = &(in_pipe_b_in2[63:61]);
wire _GEN = in_pipe_b_wflags & ~in_pipe_b_ren2;
wire [64:0] fsgnjMux_data =
_GEN
? ((&(in_pipe_b_in1[63:61])) ? 65'hE008000000000000 : in_pipe_b_in1)
: in_pipe_b_wflags
? (isnan1 & isnan2
? 65'hE008000000000000
: isnan2 | in_pipe_b_rm[0] != io_lt & ~isnan1
? in_pipe_b_in1
: in_pipe_b_in2)
: {in_pipe_b_rm[1]
? in_pipe_b_in1[64] ^ in_pipe_b_in2[64]
: in_pipe_b_rm[0] ^ in_pipe_b_in2[64],
in_pipe_b_in1[63:0]};
reg [64:0] io_out_pipe_b_data;
reg [4:0] io_out_pipe_b_exc;
always @(posedge clock) begin
if (reset)
in_pipe_v <= 1'h0;
else
in_pipe_v <= io_in_valid;
if (io_in_valid) begin
in_pipe_b_ren2 <= io_in_bits_ren2;
in_pipe_b_typeTagOut <= io_in_bits_typeTagOut;
in_pipe_b_wflags <= io_in_bits_wflags;
in_pipe_b_rm <= io_in_bits_rm;
in_pipe_b_in1 <= io_in_bits_in1;
in_pipe_b_in2 <= io_in_bits_in2;
end
if (in_pipe_v) begin
automatic logic _GEN_0 = in_pipe_b_typeTagOut == 2'h0;
automatic logic [8:0] _mux_data_expOut_commonCase_T = fsgnjMux_data[60:52] - 9'h100;
io_out_pipe_b_data <=
_GEN_0
? (_GEN
? {fsgnjMux_data[64:33], _narrower_io_out}
: {fsgnjMux_data[64:33],
fsgnjMux_data[64],
fsgnjMux_data[63:61] == 3'h0 | fsgnjMux_data[63:61] > 3'h5
? {fsgnjMux_data[63:61], _mux_data_expOut_commonCase_T[5:0]}
: _mux_data_expOut_commonCase_T,
fsgnjMux_data[51:29]})
: fsgnjMux_data;
io_out_pipe_b_exc <=
_GEN & _GEN_0
? _narrower_io_exceptionFlags
: _GEN
? {(&(in_pipe_b_in1[63:61])) & ~(in_pipe_b_in1[51]), 4'h0}
: in_pipe_b_wflags
? {(&(in_pipe_b_in1[63:61])) & ~(in_pipe_b_in1[51])
| (&(in_pipe_b_in2[63:61])) & ~(in_pipe_b_in2[51]),
4'h0}
: 5'h0;
end
end // always @(posedge)
RecFNToRecFN narrower (
.io_in (in_pipe_b_in1),
.io_roundingMode (in_pipe_b_rm),
.io_out (_narrower_io_out),
.io_exceptionFlags (_narrower_io_exceptionFlags)
);
assign io_out_bits_data = io_out_pipe_b_data;
assign io_out_bits_exc = io_out_pipe_b_exc;
endmodule
hardware/generated/genesys2-soc-verilog/FPToInt.sv
+259
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@@ -0,0 +1,259 @@
// Generated by CIRCT firtool-1.151.0
module FPToInt(
input clock,
io_in_valid,
io_in_bits_ren2,
input [1:0] io_in_bits_typeTagOut,
input io_in_bits_wflags,
input [2:0] io_in_bits_rm,
input [1:0] io_in_bits_typ,
io_in_bits_fmt,
input [64:0] io_in_bits_in1,
io_in_bits_in2,
output [2:0] io_out_bits_in_rm,
output [64:0] io_out_bits_in_in1,
io_out_bits_in_in2,
output io_out_bits_lt,
output [63:0] io_out_bits_store,
io_out_bits_toint,
output [4:0] io_out_bits_exc
);
wire [63:0] toint;
wire _narrow_io_signedOut_T;
wire intType;
wire [2:0] _narrow_io_intExceptionFlags;
wire [63:0] _conv_io_out;
wire [2:0] _conv_io_intExceptionFlags;
wire _dcmp_io_lt;
wire _dcmp_io_eq;
wire [4:0] _dcmp_io_exceptionFlags;
reg in_ren2;
reg [1:0] in_typeTagOut;
reg in_wflags;
reg [2:0] in_rm;
reg [1:0] in_typ;
reg [1:0] in_fmt;
reg [64:0] in_in1;
reg [64:0] in_in2;
wire [12:0] _GEN = {1'h0, in_in1[63:52]};
wire [52:0] _toint_ieee_unrecoded_denormFract_T_1 =
{1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52];
wire toint_ieee_prevUnrecoded_rawIn_isSpecial = &{in_in1[52], in_in1[30]};
wire toint_ieee_prevUnrecoded_rawIn_isInf =
toint_ieee_prevUnrecoded_rawIn_isSpecial & ~(in_in1[29]);
wire toint_ieee_prevUnrecoded_isSubnormal =
$signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82;
wire [23:0] _toint_ieee_prevUnrecoded_denormFract_T_1 =
{1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23];
wire toint_ieee_unrecoded_rawIn_isSpecial_1 = &(in_in1[63:62]);
wire toint_ieee_unrecoded_rawIn_1_isInf =
toint_ieee_unrecoded_rawIn_isSpecial_1 & ~(in_in1[61]);
wire toint_ieee_unrecoded_isSubnormal_1 = $signed(_GEN) < 13'sh402;
wire [52:0] _toint_ieee_unrecoded_denormFract_T_3 =
{1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52];
wire [51:0] toint_ieee_unrecoded_fractOut_1 =
toint_ieee_unrecoded_isSubnormal_1
? _toint_ieee_unrecoded_denormFract_T_3[51:0]
: toint_ieee_unrecoded_rawIn_1_isInf ? 52'h0 : in_in1[51:0];
wire toint_ieee_prevUnrecoded_rawIn_isSpecial_1 = &{in_in1[52], in_in1[30]};
wire toint_ieee_prevUnrecoded_rawIn_1_isInf =
toint_ieee_prevUnrecoded_rawIn_isSpecial_1 & ~(in_in1[29]);
wire toint_ieee_prevUnrecoded_isSubnormal_1 =
$signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82;
wire [23:0] _toint_ieee_prevUnrecoded_denormFract_T_3 =
{1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23];
wire [63:0] toint_ieee =
in_typeTagOut[0]
? {in_in1[64],
(toint_ieee_unrecoded_isSubnormal_1 ? 11'h0 : in_in1[62:52] + 11'h3FF)
| {11{toint_ieee_unrecoded_rawIn_isSpecial_1 & in_in1[61]
| toint_ieee_unrecoded_rawIn_1_isInf}},
toint_ieee_unrecoded_fractOut_1[51:32],
(&(in_in1[63:61]))
? {in_in1[31],
(toint_ieee_prevUnrecoded_isSubnormal_1 ? 8'h0 : in_in1[30:23] + 8'h7F)
| {8{toint_ieee_prevUnrecoded_rawIn_isSpecial_1 & in_in1[29]
| toint_ieee_prevUnrecoded_rawIn_1_isInf}},
toint_ieee_prevUnrecoded_isSubnormal_1
? _toint_ieee_prevUnrecoded_denormFract_T_3[22:0]
: toint_ieee_prevUnrecoded_rawIn_1_isInf ? 23'h0 : in_in1[22:0]}
: toint_ieee_unrecoded_fractOut_1[31:0]}
: {2{(&(in_in1[63:61]))
? {in_in1[31],
(toint_ieee_prevUnrecoded_isSubnormal ? 8'h0 : in_in1[30:23] + 8'h7F)
| {8{toint_ieee_prevUnrecoded_rawIn_isSpecial & in_in1[29]
| toint_ieee_prevUnrecoded_rawIn_isInf}},
toint_ieee_prevUnrecoded_isSubnormal
? _toint_ieee_prevUnrecoded_denormFract_T_1[22:0]
: toint_ieee_prevUnrecoded_rawIn_isInf ? 23'h0 : in_in1[22:0]}
: $signed(_GEN) < 13'sh402
? _toint_ieee_unrecoded_denormFract_T_1[31:0]
: (&(in_in1[63:62])) & ~(in_in1[61]) ? 32'h0 : in_in1[31:0]}};
wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_1 =
{1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52];
wire io_out_bits_store_prevUnrecoded_rawIn_isSpecial = &{in_in1[52], in_in1[30]};
wire io_out_bits_store_prevUnrecoded_rawIn_isInf =
io_out_bits_store_prevUnrecoded_rawIn_isSpecial & ~(in_in1[29]);
wire io_out_bits_store_prevUnrecoded_isSubnormal =
$signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82;
wire [23:0] _io_out_bits_store_prevUnrecoded_denormFract_T_1 =
{1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23];
wire io_out_bits_store_unrecoded_rawIn_isSpecial_1 = &(in_in1[63:62]);
wire io_out_bits_store_unrecoded_rawIn_1_isInf =
io_out_bits_store_unrecoded_rawIn_isSpecial_1 & ~(in_in1[61]);
wire io_out_bits_store_unrecoded_isSubnormal_1 = $signed(_GEN) < 13'sh402;
wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_3 =
{1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52];
wire [51:0] io_out_bits_store_unrecoded_fractOut_1 =
io_out_bits_store_unrecoded_isSubnormal_1
? _io_out_bits_store_unrecoded_denormFract_T_3[51:0]
: io_out_bits_store_unrecoded_rawIn_1_isInf ? 52'h0 : in_in1[51:0];
wire io_out_bits_store_prevUnrecoded_rawIn_isSpecial_1 =
&{in_in1[52], in_in1[30]};
wire io_out_bits_store_prevUnrecoded_rawIn_1_isInf =
io_out_bits_store_prevUnrecoded_rawIn_isSpecial_1 & ~(in_in1[29]);
wire io_out_bits_store_prevUnrecoded_isSubnormal_1 =
$signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82;
wire [23:0] _io_out_bits_store_prevUnrecoded_denormFract_T_3 =
{1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23];
wire [8:0] _classify_out_expOut_commonCase_T = in_in1[60:52] - 9'h100;
wire [8:0] classify_out_expOut =
in_in1[63:61] == 3'h0 | in_in1[63:61] > 3'h5
? {in_in1[63:61], _classify_out_expOut_commonCase_T[5:0]}
: _classify_out_expOut_commonCase_T;
wire _classify_out_isNormal_T = classify_out_expOut[8:7] == 2'h1;
wire classify_out_isSubnormal =
classify_out_expOut[8:6] == 3'h1 | _classify_out_isNormal_T
& classify_out_expOut[6:0] < 7'h2;
wire classify_out_isNormal =
_classify_out_isNormal_T & (|(classify_out_expOut[6:1]))
| classify_out_expOut[8:7] == 2'h2;
wire classify_out_isZero = classify_out_expOut[8:6] == 3'h0;
wire classify_out_isInf =
(&(classify_out_expOut[8:7])) & ~(classify_out_expOut[6]);
wire classify_out_isNaN = &(classify_out_expOut[8:6]);
wire _classify_out_isNormal_T_4 = in_in1[63:62] == 2'h1;
wire classify_out_isSubnormal_1 =
in_in1[63:61] == 3'h1 | _classify_out_isNormal_T_4 & in_in1[61:52] < 10'h2;
wire classify_out_isNormal_1 =
_classify_out_isNormal_T_4 & (|(in_in1[61:53])) | in_in1[63:62] == 2'h2;
wire classify_out_isZero_1 = in_in1[63:61] == 3'h0;
wire classify_out_isInf_1 = (&(in_in1[63:62])) & ~(in_in1[61]);
wire classify_out_isNaN_1 = &(in_in1[63:61]);
assign intType = in_wflags ? ~in_ren2 & in_typ[1] : ~(in_rm[0]) & in_fmt[0];
assign _narrow_io_signedOut_T = in_typ[0];
wire excSign = in_in1[64] & in_in1[63:61] != 3'h7;
wire invalid = _conv_io_intExceptionFlags[2] | _narrow_io_intExceptionFlags[1];
assign toint =
in_wflags
? (in_ren2
? {63'h0, |(~(in_rm[1:0]) & {_dcmp_io_lt, _dcmp_io_eq})}
| {toint_ieee[63:32], 32'h0}
: ~(in_typ[1]) & invalid
? {_conv_io_out[63:32], ~_narrow_io_signedOut_T == excSign, {31{~excSign}}}
: _conv_io_out)
: in_rm[0]
? {54'h0,
in_typeTagOut[0]
? {classify_out_isNaN_1 & in_in1[51],
classify_out_isNaN_1 & ~(in_in1[51]),
classify_out_isInf_1 & ~(in_in1[64]),
classify_out_isNormal_1 & ~(in_in1[64]),
classify_out_isSubnormal_1 & ~(in_in1[64]),
classify_out_isZero_1 & ~(in_in1[64]),
classify_out_isZero_1 & in_in1[64],
classify_out_isSubnormal_1 & in_in1[64],
classify_out_isNormal_1 & in_in1[64],
classify_out_isInf_1 & in_in1[64]}
: {classify_out_isNaN & in_in1[51],
classify_out_isNaN & ~(in_in1[51]),
classify_out_isInf & ~(in_in1[64]),
classify_out_isNormal & ~(in_in1[64]),
classify_out_isSubnormal & ~(in_in1[64]),
classify_out_isZero & ~(in_in1[64]),
classify_out_isZero & in_in1[64],
classify_out_isSubnormal & in_in1[64],
classify_out_isNormal & in_in1[64],
classify_out_isInf & in_in1[64]}} | {toint_ieee[63:32], 32'h0}
: toint_ieee;
always @(posedge clock) begin
if (io_in_valid) begin
in_ren2 <= io_in_bits_ren2;
in_typeTagOut <= io_in_bits_typeTagOut;
in_wflags <= io_in_bits_wflags;
in_rm <= io_in_bits_rm;
in_typ <= io_in_bits_typ;
in_fmt <= io_in_bits_fmt;
in_in1 <= io_in_bits_in1;
in_in2 <= io_in_bits_in2;
end
end // always @(posedge)
CompareRecFN dcmp (
.io_a (in_in1),
.io_b (in_in2),
.io_signaling (~(in_rm[1])),
.io_lt (_dcmp_io_lt),
.io_eq (_dcmp_io_eq),
.io_exceptionFlags (_dcmp_io_exceptionFlags)
);
RecFNToIN conv (
.io_in (in_in1),
.io_roundingMode (in_rm),
.io_signedOut (~_narrow_io_signedOut_T),
.io_out (_conv_io_out),
.io_intExceptionFlags (_conv_io_intExceptionFlags)
);
RecFNToIN_1 narrow (
.io_in (in_in1),
.io_roundingMode (in_rm),
.io_signedOut (~_narrow_io_signedOut_T),
.io_intExceptionFlags (_narrow_io_intExceptionFlags)
);
assign io_out_bits_in_rm = in_rm;
assign io_out_bits_in_in1 = in_in1;
assign io_out_bits_in_in2 = in_in2;
assign io_out_bits_lt =
_dcmp_io_lt | $signed(in_in1) < 65'sh0 & $signed(in_in2) > -65'sh1;
assign io_out_bits_store =
in_typeTagOut[0]
? {in_in1[64],
(io_out_bits_store_unrecoded_isSubnormal_1 ? 11'h0 : in_in1[62:52] + 11'h3FF)
| {11{io_out_bits_store_unrecoded_rawIn_isSpecial_1 & in_in1[61]
| io_out_bits_store_unrecoded_rawIn_1_isInf}},
io_out_bits_store_unrecoded_fractOut_1[51:32],
(&(in_in1[63:61]))
? {in_in1[31],
(io_out_bits_store_prevUnrecoded_isSubnormal_1
? 8'h0
: in_in1[30:23] + 8'h7F)
| {8{io_out_bits_store_prevUnrecoded_rawIn_isSpecial_1 & in_in1[29]
| io_out_bits_store_prevUnrecoded_rawIn_1_isInf}},
io_out_bits_store_prevUnrecoded_isSubnormal_1
? _io_out_bits_store_prevUnrecoded_denormFract_T_3[22:0]
: io_out_bits_store_prevUnrecoded_rawIn_1_isInf ? 23'h0 : in_in1[22:0]}
: io_out_bits_store_unrecoded_fractOut_1[31:0]}
: {2{(&(in_in1[63:61]))
? {in_in1[31],
(io_out_bits_store_prevUnrecoded_isSubnormal
? 8'h0
: in_in1[30:23] + 8'h7F)
| {8{io_out_bits_store_prevUnrecoded_rawIn_isSpecial & in_in1[29]
| io_out_bits_store_prevUnrecoded_rawIn_isInf}},
io_out_bits_store_prevUnrecoded_isSubnormal
? _io_out_bits_store_prevUnrecoded_denormFract_T_1[22:0]
: io_out_bits_store_prevUnrecoded_rawIn_isInf ? 23'h0 : in_in1[22:0]}
: $signed(_GEN) < 13'sh402
? _io_out_bits_store_unrecoded_denormFract_T_1[31:0]
: (&(in_in1[63:62])) & ~(in_in1[61]) ? 32'h0 : in_in1[31:0]}};
assign io_out_bits_toint = intType ? toint : {{32{toint[31]}}, toint[31:0]};
assign io_out_bits_exc =
in_wflags
? (in_ren2
? _dcmp_io_exceptionFlags
: in_typ[1]
? {|(_conv_io_intExceptionFlags[2:1]), 3'h0, _conv_io_intExceptionFlags[0]}
: {invalid, 3'h0, ~invalid & _conv_io_intExceptionFlags[0]})
: 5'h0;
endmodule
hardware/generated/genesys2-soc-verilog/FPU.sv
+725
View File
@@ -0,0 +1,725 @@
// Generated by CIRCT firtool-1.151.0
// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifndef PRINTF_COND_
`ifdef PRINTF_COND
`define PRINTF_COND_ (`PRINTF_COND)
`else // PRINTF_COND
`define PRINTF_COND_ 1
`endif // PRINTF_COND
`endif // not def PRINTF_COND_
module FPU(
input clock,
reset,
input [31:0] io_inst,
input [63:0] io_fromint_data,
input [2:0] io_fcsr_rm,
output io_fcsr_flags_valid,
output [4:0] io_fcsr_flags_bits,
output [63:0] io_store_data,
io_toint_data,
input io_ll_resp_val,
input [2:0] io_ll_resp_type,
input [4:0] io_ll_resp_tag,
input [63:0] io_ll_resp_data,
input io_valid,
output io_fcsr_rdy,
io_nack_mem,
io_illegal_rm,
input io_killx,
io_killm,
output io_dec_wen,
io_dec_ren1,
io_dec_ren2,
io_dec_ren3,
io_sboard_set,
io_sboard_clr,
output [4:0] io_sboard_clra
);
wire divSqrt_inFlight;
wire [4:0] divSqrt_flags;
wire [64:0] divSqrt_wdata;
wire divSqrt_wen;
wire divSqrt_typeTag;
wire _divSqrt_1_io_inReady;
wire _divSqrt_1_io_outValid_div;
wire _divSqrt_1_io_outValid_sqrt;
wire [64:0] _divSqrt_1_io_out;
wire [4:0] _divSqrt_1_io_exceptionFlags;
wire _divSqrt_io_inReady;
wire _divSqrt_io_outValid_div;
wire _divSqrt_io_outValid_sqrt;
wire [32:0] _divSqrt_io_out;
wire [4:0] _divSqrt_io_exceptionFlags;
wire [64:0] _dfma_io_out_bits_data;
wire [4:0] _dfma_io_out_bits_exc;
wire [64:0] _fpmu_io_out_bits_data;
wire [4:0] _fpmu_io_out_bits_exc;
wire [64:0] _ifpu_io_out_bits_data;
wire [4:0] _ifpu_io_out_bits_exc;
wire [2:0] _fpiu_io_out_bits_in_rm;
wire [64:0] _fpiu_io_out_bits_in_in1;
wire [64:0] _fpiu_io_out_bits_in_in2;
wire _fpiu_io_out_bits_lt;
wire [4:0] _fpiu_io_out_bits_exc;
wire [64:0] _sfma_io_out_bits_data;
wire [4:0] _sfma_io_out_bits_exc;
wire [64:0] _regfile_ext_R0_data;
wire [64:0] _regfile_ext_R1_data;
wire [64:0] _regfile_ext_R2_data;
wire _fp_decoder_io_sigs_ren1;
wire _fp_decoder_io_sigs_ren2;
wire _fp_decoder_io_sigs_ren3;
wire _fp_decoder_io_sigs_swap12;
wire _fp_decoder_io_sigs_swap23;
wire [1:0] _fp_decoder_io_sigs_typeTagIn;
wire [1:0] _fp_decoder_io_sigs_typeTagOut;
wire _fp_decoder_io_sigs_fromint;
wire _fp_decoder_io_sigs_toint;
wire _fp_decoder_io_sigs_fastpipe;
wire _fp_decoder_io_sigs_fma;
wire _fp_decoder_io_sigs_div;
wire _fp_decoder_io_sigs_sqrt;
wire _fp_decoder_io_sigs_wflags;
reg ex_reg_valid;
reg [31:0] ex_reg_inst;
reg ex_reg_ctrl_ren2;
reg ex_reg_ctrl_ren3;
reg ex_reg_ctrl_swap23;
reg [1:0] ex_reg_ctrl_typeTagIn;
reg [1:0] ex_reg_ctrl_typeTagOut;
reg ex_reg_ctrl_fromint;
reg ex_reg_ctrl_toint;
reg ex_reg_ctrl_fastpipe;
reg ex_reg_ctrl_fma;
reg ex_reg_ctrl_div;
reg ex_reg_ctrl_sqrt;
reg ex_reg_ctrl_wflags;
reg [4:0] ex_ra_0;
reg [4:0] ex_ra_1;
reg [4:0] ex_ra_2;
reg load_wb;
reg [1:0] load_wb_typeTag;
reg [63:0] load_wb_data;
reg [4:0] load_wb_tag;
reg mem_reg_valid;
reg [31:0] mem_reg_inst;
reg wb_reg_valid;
reg [1:0] mem_ctrl_typeTagOut;
reg mem_ctrl_fromint;
reg mem_ctrl_toint;
reg mem_ctrl_fastpipe;
reg mem_ctrl_fma;
reg mem_ctrl_div;
reg mem_ctrl_sqrt;
reg mem_ctrl_wflags;
reg wb_ctrl_toint;
wire [63:0] _wdata_T_2 =
(load_wb_typeTag[0] ? 64'h0 : 64'hFFFFFFFF00000000) | load_wb_data;
wire wdata_rawIn_isZeroExpIn = _wdata_T_2[62:52] == 11'h0;
wire _wdata_rawIn_out_isNaN_T = |(_wdata_T_2[51:0]);
wire [5:0] wdata_rawIn_normDist =
_wdata_T_2[51]
? 6'h0
: _wdata_T_2[50]
? 6'h1
: _wdata_T_2[49]
? 6'h2
: _wdata_T_2[48]
? 6'h3
: _wdata_T_2[47]
? 6'h4
: _wdata_T_2[46]
? 6'h5
: _wdata_T_2[45]
? 6'h6
: _wdata_T_2[44]
? 6'h7
: _wdata_T_2[43]
? 6'h8
: _wdata_T_2[42]
? 6'h9
: _wdata_T_2[41]
? 6'hA
: _wdata_T_2[40]
? 6'hB
: _wdata_T_2[39]
? 6'hC
: _wdata_T_2[38]
? 6'hD
: _wdata_T_2[37]
? 6'hE
: _wdata_T_2[36]
? 6'hF
: _wdata_T_2[35]
? 6'h10
: _wdata_T_2[34]
? 6'h11
: _wdata_T_2[33]
? 6'h12
: _wdata_T_2[32]
? 6'h13
: _wdata_T_2[31]
? 6'h14
: _wdata_T_2[30]
? 6'h15
: _wdata_T_2[29]
? 6'h16
: _wdata_T_2[28]
? 6'h17
: _wdata_T_2[27]
? 6'h18
: _wdata_T_2[26]
? 6'h19
: _wdata_T_2[25]
? 6'h1A
: _wdata_T_2[24]
? 6'h1B
: _wdata_T_2[23]
? 6'h1C
: _wdata_T_2[22]
? 6'h1D
: _wdata_T_2[21]
? 6'h1E
: _wdata_T_2[20]
? 6'h1F
: _wdata_T_2[19]
? 6'h20
: _wdata_T_2[18]
? 6'h21
: _wdata_T_2[17]
? 6'h22
: _wdata_T_2[16]
? 6'h23
: _wdata_T_2[15]
? 6'h24
: _wdata_T_2[14]
? 6'h25
: _wdata_T_2[13]
? 6'h26
: _wdata_T_2[12]
? 6'h27
: _wdata_T_2[11]
? 6'h28
: _wdata_T_2[10]
? 6'h29
: _wdata_T_2[9]
? 6'h2A
: _wdata_T_2[8]
? 6'h2B
: _wdata_T_2[7]
? 6'h2C
: _wdata_T_2[6]
? 6'h2D
: _wdata_T_2[5]
? 6'h2E
: _wdata_T_2[4]
? 6'h2F
: _wdata_T_2[3]
? 6'h30
: _wdata_T_2[2]
? 6'h31
: {5'h19,
~(_wdata_T_2[1])};
wire [114:0] _wdata_rawIn_subnormFract_T =
{63'h0, _wdata_T_2[51:0]} << wdata_rawIn_normDist;
wire [11:0] _wdata_rawIn_adjustedExp_T_4 =
(wdata_rawIn_isZeroExpIn ? {6'h3F, ~wdata_rawIn_normDist} : {1'h0, _wdata_T_2[62:52]})
+ {10'h100, wdata_rawIn_isZeroExpIn ? 2'h2 : 2'h1};
wire [51:0] _wdata_T_10 =
wdata_rawIn_isZeroExpIn
? {_wdata_rawIn_subnormFract_T[50:0], 1'h0}
: _wdata_T_2[51:0];
wire [2:0] _wdata_T_4 =
wdata_rawIn_isZeroExpIn & ~_wdata_rawIn_out_isNaN_T
? 3'h0
: _wdata_rawIn_adjustedExp_T_4[11:9];
wire _GEN =
_wdata_T_4[0] | (&(_wdata_rawIn_adjustedExp_T_4[11:10])) & _wdata_rawIn_out_isNaN_T;
wire wdata_rawIn_isZeroExpIn_1 = _wdata_T_2[30:23] == 8'h0;
wire _wdata_rawIn_out_isNaN_T_2 = |(_wdata_T_2[22:0]);
wire [4:0] wdata_rawIn_normDist_1 =
_wdata_T_2[22]
? 5'h0
: _wdata_T_2[21]
? 5'h1
: _wdata_T_2[20]
? 5'h2
: _wdata_T_2[19]
? 5'h3
: _wdata_T_2[18]
? 5'h4
: _wdata_T_2[17]
? 5'h5
: _wdata_T_2[16]
? 5'h6
: _wdata_T_2[15]
? 5'h7
: _wdata_T_2[14]
? 5'h8
: _wdata_T_2[13]
? 5'h9
: _wdata_T_2[12]
? 5'hA
: _wdata_T_2[11]
? 5'hB
: _wdata_T_2[10]
? 5'hC
: _wdata_T_2[9]
? 5'hD
: _wdata_T_2[8]
? 5'hE
: _wdata_T_2[7]
? 5'hF
: _wdata_T_2[6]
? 5'h10
: _wdata_T_2[5]
? 5'h11
: _wdata_T_2[4]
? 5'h12
: _wdata_T_2[3]
? 5'h13
: _wdata_T_2[2]
? 5'h14
: _wdata_T_2[1]
? 5'h15
: 5'h16;
wire [53:0] _wdata_rawIn_subnormFract_T_2 =
{31'h0, _wdata_T_2[22:0]} << wdata_rawIn_normDist_1;
wire [8:0] _wdata_rawIn_adjustedExp_T_9 =
(wdata_rawIn_isZeroExpIn_1
? {4'hF, ~wdata_rawIn_normDist_1}
: {1'h0, _wdata_T_2[30:23]}) + {7'h20, wdata_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1};
wire [2:0] _wdata_T_13 =
wdata_rawIn_isZeroExpIn_1 & ~_wdata_rawIn_out_isNaN_T_2
? 3'h0
: _wdata_rawIn_adjustedExp_T_9[8:6];
wire [60:0] _GEN_0 =
(&{_wdata_T_4[2:1], _GEN})
? {&(_wdata_T_10[51:32]),
_wdata_rawIn_adjustedExp_T_4[7:1],
_wdata_T_13[2],
_wdata_T_10[51:32],
_wdata_T_2[31],
_wdata_T_13[1],
_wdata_T_13[0] | (&(_wdata_rawIn_adjustedExp_T_9[8:7]))
& _wdata_rawIn_out_isNaN_T_2,
_wdata_rawIn_adjustedExp_T_9[5:0],
wdata_rawIn_isZeroExpIn_1
? {_wdata_rawIn_subnormFract_T_2[21:0], 1'h0}
: _wdata_T_2[22:0]}
: {_wdata_rawIn_adjustedExp_T_4[8:0], _wdata_T_10};
wire curOK =
{_wdata_T_4[2:1], _GEN} != 3'h7 | _GEN_0[60] == (&(_GEN_0[51:32]));
wire _GEN_1 = load_wb & ~reset;
wire [2:0] ex_rm = (&(ex_reg_inst[14:12])) ? io_fcsr_rm : ex_reg_inst[14:12];
wire _dfma_io_in_valid_T = ex_reg_valid & ex_reg_ctrl_fma;
wire _write_port_busy_T_16 = ex_reg_ctrl_typeTagOut == 2'h0;
wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode =
{_regfile_ext_R2_data[52], _regfile_ext_R2_data[30:29]};
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 =
{3'h0, _regfile_ext_R2_data[52], _regfile_ext_R2_data[30:23]} + 12'h700;
wire [64:0] fpmu_io_in_bits_in1 =
ex_reg_ctrl_typeTagIn[0] | (&(_regfile_ext_R2_data[64:60]))
? (ex_reg_ctrl_typeTagIn[0]
? _regfile_ext_R2_data
: {_regfile_ext_R2_data[31],
fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0
| fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5
? {_regfile_ext_R2_data[52],
_regfile_ext_R2_data[30:29],
_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[8:0]}
: _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2,
_regfile_ext_R2_data[22:0],
29'h0})
: 65'hE008000000000000;
wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode =
{_regfile_ext_R1_data[52], _regfile_ext_R1_data[30:29]};
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 =
{3'h0, _regfile_ext_R1_data[52], _regfile_ext_R1_data[30:23]} + 12'h700;
wire [64:0] fpmu_io_in_bits_in2 =
ex_reg_ctrl_typeTagIn[0] | (&(_regfile_ext_R1_data[64:60]))
? (ex_reg_ctrl_typeTagIn[0]
? _regfile_ext_R1_data
: {_regfile_ext_R1_data[31],
fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0
| fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5
? {_regfile_ext_R1_data[52],
_regfile_ext_R1_data[30:29],
_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[8:0]}
: _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2,
_regfile_ext_R1_data[22:0],
29'h0})
: 65'hE008000000000000;
reg [4:0] divSqrt_waddr;
wire _divSqrt_io_inValid_T = mem_ctrl_typeTagOut == 2'h0;
wire _divSqrt_io_inValid_T_2 = mem_ctrl_typeTagOut == 2'h1;
reg [2:0] wen;
reg [4:0] wbInfo_0_rd;
reg wbInfo_0_typeTag;
reg [1:0] wbInfo_0_pipeid;
reg [4:0] wbInfo_1_rd;
reg wbInfo_1_typeTag;
reg [1:0] wbInfo_1_pipeid;
reg [4:0] wbInfo_2_rd;
reg wbInfo_2_typeTag;
reg [1:0] wbInfo_2_pipeid;
reg write_port_busy;
wire [4:0] waddr = divSqrt_wen ? divSqrt_waddr : wbInfo_0_rd;
wire [3:0][64:0] _GEN_2 =
{{_dfma_io_out_bits_data},
{_sfma_io_out_bits_data},
{_ifpu_io_out_bits_data},
{_fpmu_io_out_bits_data}};
wire [64:0] _wdata_T_29 = divSqrt_wen ? divSqrt_wdata : _GEN_2[wbInfo_0_pipeid];
wire [64:0] wdata_1 =
(divSqrt_wen ? divSqrt_typeTag : wbInfo_0_typeTag)
? _wdata_T_29
: {12'hFFF, _wdata_T_29[31], 20'hFFFFF, _wdata_T_29[32], _wdata_T_29[30:0]};
wire [3:0][4:0] _GEN_3 =
{{_dfma_io_out_bits_exc},
{_sfma_io_out_bits_exc},
{_ifpu_io_out_bits_exc},
{_fpmu_io_out_bits_exc}};
wire frfWriteBundle_1_wrenf = wen[0] | divSqrt_wen;
wire curOK_1 = wdata_1[63:61] != 3'h7 | wdata_1[60] == (&(wdata_1[51:32]));
wire _GEN_4 = frfWriteBundle_1_wrenf & ~reset;
`ifndef SYNTHESIS
always @(posedge clock) begin
if ((`PRINTF_COND_) & _GEN_1 & ~curOK)
$fwrite(32'h80000002,
"Assertion failed\n at FPU.scala:823 assert(consistent(wdata))\n");
if ((`PRINTF_COND_) & _GEN_4 & ~curOK_1)
$fwrite(32'h80000002,
"Assertion failed\n at FPU.scala:970 assert(consistent(wdata))\n");
end // always @(posedge)
`endif // not def SYNTHESIS
wire wb_toint_valid = wb_reg_valid & wb_ctrl_toint;
reg [4:0] wb_toint_exc;
wire _divSqrt_inValid_T = mem_ctrl_div | mem_ctrl_sqrt;
wire io_nack_mem_0 =
write_port_busy | _divSqrt_inValid_T & (|wen) | divSqrt_inFlight;
reg io_sboard_set_REG;
wire divSqrt_inValid =
mem_reg_valid & _divSqrt_inValid_T & ~divSqrt_inFlight;
reg divSqrt_killed;
wire [8:0] _divSqrt_io_a_expOut_commonCase_T =
_fpiu_io_out_bits_in_in1[60:52] - 9'h100;
wire [8:0] _divSqrt_io_b_expOut_commonCase_T =
_fpiu_io_out_bits_in_in2[60:52] - 9'h100;
assign divSqrt_typeTag = _divSqrt_1_io_outValid_div | _divSqrt_1_io_outValid_sqrt;
assign divSqrt_wen =
divSqrt_typeTag
? ~divSqrt_killed
: (_divSqrt_io_outValid_div | _divSqrt_io_outValid_sqrt) & ~divSqrt_killed;
assign divSqrt_wdata =
divSqrt_typeTag
? ({65{_divSqrt_1_io_out[63:61] != 3'h7}} | 65'h1EFEFFFFFFFFFFFFF)
& _divSqrt_1_io_out
: {32'h0, _divSqrt_io_out};
assign divSqrt_flags =
divSqrt_typeTag ? _divSqrt_1_io_exceptionFlags : _divSqrt_io_exceptionFlags;
assign divSqrt_inFlight =
~divSqrt_killed & (~_divSqrt_1_io_inReady | ~_divSqrt_io_inReady);
always @(posedge clock) begin
automatic logic [2:0] memLatencyMask;
automatic logic mem_wen;
automatic logic [1:0] _GEN_5;
memLatencyMask =
{1'h0,
{1'h0, mem_ctrl_fastpipe | mem_ctrl_fromint}
| {mem_ctrl_fma & _divSqrt_io_inValid_T, 1'h0}}
| {mem_ctrl_fma & _divSqrt_io_inValid_T_2, 2'h0};
mem_wen = mem_reg_valid & (mem_ctrl_fma | mem_ctrl_fastpipe | mem_ctrl_fromint);
_GEN_5 = {1'h0, mem_ctrl_fromint};
if (reset) begin
ex_reg_valid <= 1'h0;
mem_reg_valid <= 1'h0;
wb_reg_valid <= 1'h0;
wen <= 3'h0;
divSqrt_killed <= 1'h1;
end
else begin
automatic logic _killm_T = io_killm | io_nack_mem_0;
ex_reg_valid <= io_valid;
mem_reg_valid <= ex_reg_valid & ~(io_killx | mem_reg_valid & _killm_T);
wb_reg_valid <= mem_reg_valid & ~_killm_T;
wen <= {3{mem_wen & ~_killm_T}} & memLatencyMask | {1'h0, wen[2:1]};
divSqrt_killed <= divSqrt_inValid & _killm_T;
end
if (io_valid) begin
ex_reg_inst <= io_inst;
ex_reg_ctrl_ren2 <= _fp_decoder_io_sigs_ren2;
ex_reg_ctrl_ren3 <= _fp_decoder_io_sigs_ren3;
ex_reg_ctrl_swap23 <= _fp_decoder_io_sigs_swap23;
ex_reg_ctrl_typeTagIn <= _fp_decoder_io_sigs_typeTagIn;
ex_reg_ctrl_typeTagOut <= _fp_decoder_io_sigs_typeTagOut;
ex_reg_ctrl_fromint <= _fp_decoder_io_sigs_fromint;
ex_reg_ctrl_toint <= _fp_decoder_io_sigs_toint;
ex_reg_ctrl_fastpipe <= _fp_decoder_io_sigs_fastpipe;
ex_reg_ctrl_fma <= _fp_decoder_io_sigs_fma;
ex_reg_ctrl_div <= _fp_decoder_io_sigs_div;
ex_reg_ctrl_sqrt <= _fp_decoder_io_sigs_sqrt;
ex_reg_ctrl_wflags <= _fp_decoder_io_sigs_wflags;
if (_fp_decoder_io_sigs_ren2 & _fp_decoder_io_sigs_swap12)
ex_ra_0 <= io_inst[24:20];
else if (_fp_decoder_io_sigs_ren1 & ~_fp_decoder_io_sigs_swap12)
ex_ra_0 <= io_inst[19:15];
if (_fp_decoder_io_sigs_ren2 & ~_fp_decoder_io_sigs_swap12
& ~_fp_decoder_io_sigs_swap23)
ex_ra_1 <= io_inst[24:20];
else if (_fp_decoder_io_sigs_ren1 & _fp_decoder_io_sigs_swap12)
ex_ra_1 <= io_inst[19:15];
if (_fp_decoder_io_sigs_ren3)
ex_ra_2 <= io_inst[31:27];
else if (_fp_decoder_io_sigs_ren2 & _fp_decoder_io_sigs_swap23)
ex_ra_2 <= io_inst[24:20];
end
load_wb <= io_ll_resp_val;
if (io_ll_resp_val) begin
load_wb_typeTag <= io_ll_resp_type[1:0] - 2'h2;
load_wb_data <= io_ll_resp_data;
load_wb_tag <= io_ll_resp_tag;
end
if (ex_reg_valid) begin
mem_reg_inst <= ex_reg_inst;
mem_ctrl_typeTagOut <= ex_reg_ctrl_typeTagOut;
mem_ctrl_fromint <= ex_reg_ctrl_fromint;
mem_ctrl_toint <= ex_reg_ctrl_toint;
mem_ctrl_fastpipe <= ex_reg_ctrl_fastpipe;
mem_ctrl_fma <= ex_reg_ctrl_fma;
mem_ctrl_div <= ex_reg_ctrl_div;
mem_ctrl_sqrt <= ex_reg_ctrl_sqrt;
mem_ctrl_wflags <= ex_reg_ctrl_wflags;
write_port_busy <=
|{mem_wen
& (|(({1'h0, {ex_reg_ctrl_fastpipe, 1'h0} | {ex_reg_ctrl_fromint, 1'h0}}
| {ex_reg_ctrl_fma & _write_port_busy_T_16, 2'h0}) & memLatencyMask)),
(ex_reg_ctrl_fastpipe | ex_reg_ctrl_fromint) & wen[2]};
end
if (mem_reg_valid)
wb_ctrl_toint <= mem_ctrl_toint;
if (divSqrt_inValid)
divSqrt_waddr <= mem_reg_inst[11:7];
if (mem_wen & ~write_port_busy & memLatencyMask[0]) begin
wbInfo_0_rd <= mem_reg_inst[11:7];
wbInfo_0_typeTag <= mem_ctrl_typeTagOut[0];
wbInfo_0_pipeid <=
_GEN_5 | {mem_ctrl_fma & _divSqrt_io_inValid_T, 1'h0}
| {2{mem_ctrl_fma & _divSqrt_io_inValid_T_2}};
end
else if (wen[1]) begin
wbInfo_0_rd <= wbInfo_1_rd;
wbInfo_0_typeTag <= wbInfo_1_typeTag;
wbInfo_0_pipeid <= wbInfo_1_pipeid;
end
if (mem_wen & ~write_port_busy & memLatencyMask[1]) begin
wbInfo_1_rd <= mem_reg_inst[11:7];
wbInfo_1_typeTag <= mem_ctrl_typeTagOut[0];
wbInfo_1_pipeid <=
_GEN_5 | {mem_ctrl_fma & _divSqrt_io_inValid_T, 1'h0}
| {2{mem_ctrl_fma & _divSqrt_io_inValid_T_2}};
end
else if (wen[2]) begin
wbInfo_1_rd <= wbInfo_2_rd;
wbInfo_1_typeTag <= wbInfo_2_typeTag;
wbInfo_1_pipeid <= wbInfo_2_pipeid;
end
if (mem_wen & ~write_port_busy & memLatencyMask[2]) begin
wbInfo_2_rd <= mem_reg_inst[11:7];
wbInfo_2_typeTag <= mem_ctrl_typeTagOut[0];
wbInfo_2_pipeid <=
_GEN_5 | {mem_ctrl_fma & _divSqrt_io_inValid_T, 1'h0}
| {2{mem_ctrl_fma & _divSqrt_io_inValid_T_2}};
end
if (mem_ctrl_toint)
wb_toint_exc <= _fpiu_io_out_bits_exc;
io_sboard_set_REG <=
mem_ctrl_fma & _divSqrt_io_inValid_T_2 | mem_ctrl_div | mem_ctrl_sqrt;
end // always @(posedge)
FPUDecoder fp_decoder (
.io_inst (io_inst),
.io_sigs_wen (io_dec_wen),
.io_sigs_ren1 (_fp_decoder_io_sigs_ren1),
.io_sigs_ren2 (_fp_decoder_io_sigs_ren2),
.io_sigs_ren3 (_fp_decoder_io_sigs_ren3),
.io_sigs_swap12 (_fp_decoder_io_sigs_swap12),
.io_sigs_swap23 (_fp_decoder_io_sigs_swap23),
.io_sigs_typeTagIn (_fp_decoder_io_sigs_typeTagIn),
.io_sigs_typeTagOut (_fp_decoder_io_sigs_typeTagOut),
.io_sigs_fromint (_fp_decoder_io_sigs_fromint),
.io_sigs_toint (_fp_decoder_io_sigs_toint),
.io_sigs_fastpipe (_fp_decoder_io_sigs_fastpipe),
.io_sigs_fma (_fp_decoder_io_sigs_fma),
.io_sigs_div (_fp_decoder_io_sigs_div),
.io_sigs_sqrt (_fp_decoder_io_sigs_sqrt),
.io_sigs_wflags (_fp_decoder_io_sigs_wflags)
);
regfile_32x65 regfile_ext (
.R0_addr (ex_ra_2),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_regfile_ext_R0_data),
.R1_addr (ex_ra_1),
.R1_en (1'h1),
.R1_clk (clock),
.R1_data (_regfile_ext_R1_data),
.R2_addr (ex_ra_0),
.R2_en (1'h1),
.R2_clk (clock),
.R2_data (_regfile_ext_R2_data),
.W0_addr (waddr),
.W0_en (frfWriteBundle_1_wrenf),
.W0_clk (clock),
.W0_data (wdata_1),
.W1_addr (load_wb_tag),
.W1_en (load_wb),
.W1_clk (clock),
.W1_data ({_wdata_T_2[63], _wdata_T_4[2:1], _GEN, _GEN_0})
);
FPUFMAPipe_l3_f32 sfma (
.clock (clock),
.reset (reset),
.io_in_valid (_dfma_io_in_valid_T & _write_port_busy_T_16),
.io_in_bits_ren3 (ex_reg_ctrl_ren3),
.io_in_bits_swap23 (ex_reg_ctrl_swap23),
.io_in_bits_rm (ex_rm),
.io_in_bits_fmaCmd
({ex_reg_inst[3], ex_reg_inst[2] | ~ex_reg_ctrl_ren3 & ex_reg_inst[27]}),
.io_in_bits_in1
({32'h0,
{_regfile_ext_R2_data[31], _regfile_ext_R2_data[52], _regfile_ext_R2_data[30:0]}
| ((&(_regfile_ext_R2_data[64:60])) ? 33'h0 : 33'hE0400000)}),
.io_in_bits_in2
({32'h0,
{_regfile_ext_R1_data[31], _regfile_ext_R1_data[52], _regfile_ext_R1_data[30:0]}
| ((&(_regfile_ext_R1_data[64:60])) ? 33'h0 : 33'hE0400000)}),
.io_in_bits_in3
({32'h0,
{_regfile_ext_R0_data[31], _regfile_ext_R0_data[52], _regfile_ext_R0_data[30:0]}
| ((&(_regfile_ext_R0_data[64:60])) ? 33'h0 : 33'hE0400000)}),
.io_out_bits_data (_sfma_io_out_bits_data),
.io_out_bits_exc (_sfma_io_out_bits_exc)
);
FPToInt fpiu (
.clock (clock),
.io_in_valid
(ex_reg_valid
& (ex_reg_ctrl_toint | ex_reg_ctrl_div | ex_reg_ctrl_sqrt | ex_reg_ctrl_fastpipe
& ex_reg_ctrl_wflags)),
.io_in_bits_ren2 (ex_reg_ctrl_ren2),
.io_in_bits_typeTagOut (ex_reg_ctrl_typeTagOut),
.io_in_bits_wflags (ex_reg_ctrl_wflags),
.io_in_bits_rm (ex_rm),
.io_in_bits_typ (ex_reg_inst[21:20]),
.io_in_bits_fmt (ex_reg_inst[26:25]),
.io_in_bits_in1 (fpmu_io_in_bits_in1),
.io_in_bits_in2 (fpmu_io_in_bits_in2),
.io_out_bits_in_rm (_fpiu_io_out_bits_in_rm),
.io_out_bits_in_in1 (_fpiu_io_out_bits_in_in1),
.io_out_bits_in_in2 (_fpiu_io_out_bits_in_in2),
.io_out_bits_lt (_fpiu_io_out_bits_lt),
.io_out_bits_store (io_store_data),
.io_out_bits_toint (io_toint_data),
.io_out_bits_exc (_fpiu_io_out_bits_exc)
);
IntToFP ifpu (
.clock (clock),
.reset (reset),
.io_in_valid (ex_reg_valid & ex_reg_ctrl_fromint),
.io_in_bits_typeTagIn (ex_reg_ctrl_typeTagIn),
.io_in_bits_wflags (ex_reg_ctrl_wflags),
.io_in_bits_rm (ex_rm),
.io_in_bits_typ (ex_reg_inst[21:20]),
.io_in_bits_in1 (io_fromint_data),
.io_out_bits_data (_ifpu_io_out_bits_data),
.io_out_bits_exc (_ifpu_io_out_bits_exc)
);
FPToFP fpmu (
.clock (clock),
.reset (reset),
.io_in_valid (ex_reg_valid & ex_reg_ctrl_fastpipe),
.io_in_bits_ren2 (ex_reg_ctrl_ren2),
.io_in_bits_typeTagOut (ex_reg_ctrl_typeTagOut),
.io_in_bits_wflags (ex_reg_ctrl_wflags),
.io_in_bits_rm (ex_rm),
.io_in_bits_in1 (fpmu_io_in_bits_in1),
.io_in_bits_in2 (fpmu_io_in_bits_in2),
.io_out_bits_data (_fpmu_io_out_bits_data),
.io_out_bits_exc (_fpmu_io_out_bits_exc),
.io_lt (_fpiu_io_out_bits_lt)
);
FPUFMAPipe_l4_f64 dfma (
.clock (clock),
.reset (reset),
.io_in_valid (_dfma_io_in_valid_T & ex_reg_ctrl_typeTagOut == 2'h1),
.io_in_bits_ren3 (ex_reg_ctrl_ren3),
.io_in_bits_swap23 (ex_reg_ctrl_swap23),
.io_in_bits_rm (ex_rm),
.io_in_bits_fmaCmd
({ex_reg_inst[3], ex_reg_inst[2] | ~ex_reg_ctrl_ren3 & ex_reg_inst[27]}),
.io_in_bits_in1 (_regfile_ext_R2_data),
.io_in_bits_in2 (_regfile_ext_R1_data),
.io_in_bits_in3 (_regfile_ext_R0_data),
.io_out_bits_data (_dfma_io_out_bits_data),
.io_out_bits_exc (_dfma_io_out_bits_exc)
);
DivSqrtRecFN_small divSqrt (
.clock (clock),
.reset (divSqrt_killed),
.io_inReady (_divSqrt_io_inReady),
.io_inValid (divSqrt_inValid & _divSqrt_io_inValid_T),
.io_sqrtOp (mem_ctrl_sqrt),
.io_a
({_fpiu_io_out_bits_in_in1[64],
_fpiu_io_out_bits_in_in1[63:61] == 3'h0 | _fpiu_io_out_bits_in_in1[63:61] > 3'h5
? {_fpiu_io_out_bits_in_in1[63:61], _divSqrt_io_a_expOut_commonCase_T[5:0]}
: _divSqrt_io_a_expOut_commonCase_T,
_fpiu_io_out_bits_in_in1[51:29]}),
.io_b
({_fpiu_io_out_bits_in_in2[64],
_fpiu_io_out_bits_in_in2[63:61] == 3'h0 | _fpiu_io_out_bits_in_in2[63:61] > 3'h5
? {_fpiu_io_out_bits_in_in2[63:61], _divSqrt_io_b_expOut_commonCase_T[5:0]}
: _divSqrt_io_b_expOut_commonCase_T,
_fpiu_io_out_bits_in_in2[51:29]}),
.io_roundingMode (_fpiu_io_out_bits_in_rm),
.io_outValid_div (_divSqrt_io_outValid_div),
.io_outValid_sqrt (_divSqrt_io_outValid_sqrt),
.io_out (_divSqrt_io_out),
.io_exceptionFlags (_divSqrt_io_exceptionFlags)
);
DivSqrtRecFN_small_1 divSqrt_1 (
.clock (clock),
.reset (divSqrt_killed),
.io_inReady (_divSqrt_1_io_inReady),
.io_inValid (divSqrt_inValid & _divSqrt_io_inValid_T_2),
.io_sqrtOp (mem_ctrl_sqrt),
.io_a (_fpiu_io_out_bits_in_in1),
.io_b (_fpiu_io_out_bits_in_in2),
.io_roundingMode (_fpiu_io_out_bits_in_rm),
.io_outValid_div (_divSqrt_1_io_outValid_div),
.io_outValid_sqrt (_divSqrt_1_io_outValid_sqrt),
.io_out (_divSqrt_1_io_out),
.io_exceptionFlags (_divSqrt_1_io_exceptionFlags)
);
assign io_fcsr_flags_valid = wb_toint_valid | divSqrt_wen | wen[0];
assign io_fcsr_flags_bits =
(wb_toint_valid ? wb_toint_exc : 5'h0) | (divSqrt_wen ? divSqrt_flags : 5'h0)
| (wen[0] ? _GEN_3[wbInfo_0_pipeid] : 5'h0);
assign io_fcsr_rdy =
~((|{ex_reg_valid & ex_reg_ctrl_wflags | mem_reg_valid & mem_ctrl_wflags
| wb_toint_valid,
wen}) | divSqrt_inFlight);
assign io_nack_mem = io_nack_mem_0;
assign io_illegal_rm =
io_inst[14:12] == 3'h5 | io_inst[14:12] == 3'h6 | (&(io_inst[14:12]))
& io_fcsr_rm > 3'h4;
assign io_dec_ren1 = _fp_decoder_io_sigs_ren1;
assign io_dec_ren2 = _fp_decoder_io_sigs_ren2;
assign io_dec_ren3 = _fp_decoder_io_sigs_ren3;
assign io_sboard_set = wb_reg_valid & io_sboard_set_REG;
assign io_sboard_clr = divSqrt_wen | wen[0] & (&wbInfo_0_pipeid);
assign io_sboard_clra = waddr;
endmodule
hardware/generated/genesys2-soc-verilog/FPUDecoder.sv
+670
View File
@@ -0,0 +1,670 @@
// Generated by CIRCT firtool-1.151.0
module FPUDecoder(
input [31:0] io_inst,
output io_sigs_wen,
io_sigs_ren1,
io_sigs_ren2,
io_sigs_ren3,
io_sigs_swap12,
io_sigs_swap23,
output [1:0] io_sigs_typeTagIn,
io_sigs_typeTagOut,
output io_sigs_fromint,
io_sigs_toint,
io_sigs_fastpipe,
io_sigs_fma,
io_sigs_div,
io_sigs_sqrt,
io_sigs_wflags
);
wire [29:0] decoder_decoded_invInputs = ~(io_inst[31:2]);
wire decoder_4 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[2],
decoder_decoded_invInputs[3],
io_inst[6]};
wire decoder_decoded_andMatrixOutputs_0_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[27],
decoder_decoded_invInputs[28],
decoder_decoded_invInputs[29]};
wire decoder_6 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[26],
decoder_decoded_invInputs[27],
decoder_decoded_invInputs[28],
decoder_decoded_invInputs[29]};
wire decoder_5 =
&{io_inst[0],
io_inst[1],
io_inst[2],
decoder_decoded_invInputs[1],
decoder_decoded_invInputs[2],
io_inst[5],
decoder_decoded_invInputs[4],
io_inst[13],
decoder_decoded_invInputs[12]};
wire decoder_decoded_andMatrixOutputs_16_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[2],
decoder_decoded_invInputs[3],
io_inst[6],
io_inst[25],
decoder_decoded_invInputs[24]};
wire decoder_decoded_andMatrixOutputs_20_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
io_inst[25],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[27],
decoder_decoded_invInputs[28],
decoder_decoded_invInputs[29]};
wire decoder_decoded_andMatrixOutputs_9_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[10],
decoder_decoded_invInputs[12],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[26],
io_inst[29],
decoder_decoded_invInputs[28]};
wire decoder_decoded_andMatrixOutputs_27_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[11],
decoder_decoded_invInputs[12],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[26],
io_inst[29],
decoder_decoded_invInputs[28]};
wire decoder_decoded_andMatrixOutputs_22_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[11],
decoder_decoded_invInputs[12],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[26],
io_inst[29],
decoder_decoded_invInputs[28],
decoder_decoded_invInputs[29]};
wire decoder_decoded_andMatrixOutputs_14_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[10],
decoder_decoded_invInputs[12],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[26],
io_inst[29],
decoder_decoded_invInputs[28],
decoder_decoded_invInputs[29]};
wire decoder_decoded_andMatrixOutputs_19_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[10],
decoder_decoded_invInputs[12],
io_inst[25],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[26],
io_inst[29],
decoder_decoded_invInputs[28]};
wire decoder_decoded_andMatrixOutputs_10_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[11],
decoder_decoded_invInputs[12],
io_inst[25],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[26],
io_inst[29],
decoder_decoded_invInputs[28]};
wire decoder_decoded_andMatrixOutputs_21_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[11],
decoder_decoded_invInputs[12],
io_inst[25],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[26],
io_inst[29],
decoder_decoded_invInputs[28],
decoder_decoded_invInputs[29]};
wire decoder_decoded_andMatrixOutputs_7_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
io_inst[20],
decoder_decoded_invInputs[19],
decoder_decoded_invInputs[20],
decoder_decoded_invInputs[21],
decoder_decoded_invInputs[22],
decoder_decoded_invInputs[23],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[26],
decoder_decoded_invInputs[27],
io_inst[30]};
wire decoder_decoded_andMatrixOutputs_1_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
io_inst[20],
decoder_decoded_invInputs[19],
decoder_decoded_invInputs[20],
decoder_decoded_invInputs[21],
decoder_decoded_invInputs[22],
decoder_decoded_invInputs[23],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[26],
decoder_decoded_invInputs[27],
io_inst[30],
decoder_decoded_invInputs[29]};
wire decoder_decoded_andMatrixOutputs_5_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[18],
decoder_decoded_invInputs[19],
decoder_decoded_invInputs[20],
decoder_decoded_invInputs[21],
decoder_decoded_invInputs[22],
io_inst[25],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[26],
decoder_decoded_invInputs[27],
io_inst[30]};
wire decoder_decoded_andMatrixOutputs_12_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[18],
decoder_decoded_invInputs[19],
decoder_decoded_invInputs[20],
decoder_decoded_invInputs[21],
decoder_decoded_invInputs[22],
io_inst[25],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[26],
decoder_decoded_invInputs[27],
io_inst[30],
decoder_decoded_invInputs[29]};
wire decoder_14 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[18],
decoder_decoded_invInputs[19],
decoder_decoded_invInputs[20],
decoder_decoded_invInputs[21],
decoder_decoded_invInputs[22],
decoder_decoded_invInputs[24],
io_inst[27],
io_inst[28],
decoder_decoded_invInputs[27],
io_inst[30],
decoder_decoded_invInputs[29]};
wire decoder_decoded_andMatrixOutputs_6_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[18],
decoder_decoded_invInputs[19],
decoder_decoded_invInputs[20],
decoder_decoded_invInputs[21],
decoder_decoded_invInputs[22],
io_inst[25],
decoder_decoded_invInputs[24],
io_inst[27],
io_inst[28],
decoder_decoded_invInputs[27],
io_inst[30],
decoder_decoded_invInputs[29]};
wire decoder_decoded_andMatrixOutputs_32_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[10],
decoder_decoded_invInputs[12],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[26],
io_inst[29],
decoder_decoded_invInputs[28],
io_inst[31]};
wire decoder_decoded_andMatrixOutputs_29_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[11],
decoder_decoded_invInputs[12],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[26],
io_inst[29],
decoder_decoded_invInputs[28],
io_inst[31]};
wire decoder_decoded_andMatrixOutputs_4_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[20],
decoder_decoded_invInputs[21],
decoder_decoded_invInputs[22],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[26],
decoder_decoded_invInputs[27],
io_inst[30],
io_inst[31]};
wire decoder_decoded_andMatrixOutputs_30_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[20],
decoder_decoded_invInputs[21],
decoder_decoded_invInputs[22],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
io_inst[28],
decoder_decoded_invInputs[27],
io_inst[30],
io_inst[31]};
wire decoder_decoded_andMatrixOutputs_2_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[11],
decoder_decoded_invInputs[12],
decoder_decoded_invInputs[18],
decoder_decoded_invInputs[19],
decoder_decoded_invInputs[20],
decoder_decoded_invInputs[21],
decoder_decoded_invInputs[22],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[26],
io_inst[29],
io_inst[30],
io_inst[31]};
wire decoder_decoded_andMatrixOutputs_13_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[11],
decoder_decoded_invInputs[12],
decoder_decoded_invInputs[18],
decoder_decoded_invInputs[19],
decoder_decoded_invInputs[20],
decoder_decoded_invInputs[21],
decoder_decoded_invInputs[22],
io_inst[25],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[26],
io_inst[29],
io_inst[30],
io_inst[31]};
wire decoder_decoded_andMatrixOutputs_15_2 =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[10],
decoder_decoded_invInputs[11],
decoder_decoded_invInputs[12],
decoder_decoded_invInputs[18],
decoder_decoded_invInputs[19],
decoder_decoded_invInputs[20],
decoder_decoded_invInputs[21],
decoder_decoded_invInputs[22],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
io_inst[28],
io_inst[29],
io_inst[30],
io_inst[31]};
assign io_sigs_wen =
|{decoder_4,
decoder_decoded_andMatrixOutputs_0_2,
&{io_inst[0],
io_inst[1],
io_inst[2],
decoder_decoded_invInputs[1],
decoder_decoded_invInputs[2],
decoder_decoded_invInputs[3],
decoder_decoded_invInputs[4],
io_inst[13],
decoder_decoded_invInputs[12]},
decoder_decoded_andMatrixOutputs_22_2,
decoder_decoded_andMatrixOutputs_14_2,
decoder_decoded_andMatrixOutputs_1_2,
decoder_decoded_andMatrixOutputs_12_2,
decoder_14,
decoder_decoded_andMatrixOutputs_30_2,
decoder_decoded_andMatrixOutputs_15_2};
assign io_sigs_ren1 =
|{decoder_4,
decoder_decoded_andMatrixOutputs_0_2,
decoder_decoded_andMatrixOutputs_9_2,
decoder_decoded_andMatrixOutputs_27_2,
decoder_decoded_andMatrixOutputs_22_2,
decoder_decoded_andMatrixOutputs_7_2,
decoder_decoded_andMatrixOutputs_5_2,
decoder_14,
decoder_decoded_andMatrixOutputs_4_2,
decoder_decoded_andMatrixOutputs_2_2};
assign io_sigs_ren2 =
|{decoder_4,
decoder_decoded_andMatrixOutputs_0_2,
decoder_5,
decoder_decoded_andMatrixOutputs_9_2,
decoder_decoded_andMatrixOutputs_27_2,
decoder_decoded_andMatrixOutputs_22_2};
assign io_sigs_ren3 = decoder_4;
assign io_sigs_swap12 = decoder_5;
assign io_sigs_swap23 = decoder_6;
assign io_sigs_typeTagIn =
{1'h0,
|{decoder_5,
decoder_decoded_andMatrixOutputs_16_2,
decoder_decoded_andMatrixOutputs_20_2,
decoder_decoded_andMatrixOutputs_19_2,
decoder_decoded_andMatrixOutputs_10_2,
decoder_decoded_andMatrixOutputs_21_2,
decoder_decoded_andMatrixOutputs_1_2,
decoder_decoded_andMatrixOutputs_6_2,
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[20],
decoder_decoded_invInputs[21],
decoder_decoded_invInputs[22],
io_inst[25],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[27],
io_inst[30],
io_inst[31]},
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[10],
decoder_decoded_invInputs[11],
decoder_decoded_invInputs[12],
decoder_decoded_invInputs[18],
decoder_decoded_invInputs[19],
decoder_decoded_invInputs[20],
decoder_decoded_invInputs[21],
decoder_decoded_invInputs[22],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[26],
io_inst[29],
io_inst[30],
io_inst[31]},
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[10],
decoder_decoded_invInputs[11],
decoder_decoded_invInputs[12],
decoder_decoded_invInputs[18],
decoder_decoded_invInputs[19],
decoder_decoded_invInputs[20],
decoder_decoded_invInputs[21],
decoder_decoded_invInputs[22],
io_inst[25],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
io_inst[29],
io_inst[30],
io_inst[31]},
decoder_decoded_andMatrixOutputs_13_2}};
assign io_sigs_typeTagOut =
{1'h0,
|{&{io_inst[0],
io_inst[1],
io_inst[2],
decoder_decoded_invInputs[1],
decoder_decoded_invInputs[2],
io_inst[5],
decoder_decoded_invInputs[4],
io_inst[12],
io_inst[13],
decoder_decoded_invInputs[12]},
decoder_decoded_andMatrixOutputs_16_2,
decoder_decoded_andMatrixOutputs_20_2,
decoder_decoded_andMatrixOutputs_19_2,
decoder_decoded_andMatrixOutputs_10_2,
decoder_decoded_andMatrixOutputs_21_2,
decoder_decoded_andMatrixOutputs_12_2,
decoder_decoded_andMatrixOutputs_6_2,
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[20],
decoder_decoded_invInputs[21],
decoder_decoded_invInputs[22],
io_inst[25],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
io_inst[28],
decoder_decoded_invInputs[27],
io_inst[30],
io_inst[31]},
decoder_decoded_andMatrixOutputs_13_2,
decoder_decoded_andMatrixOutputs_15_2}};
assign io_sigs_fromint =
|{decoder_decoded_andMatrixOutputs_30_2, decoder_decoded_andMatrixOutputs_15_2};
assign io_sigs_toint =
|{decoder_5,
decoder_decoded_andMatrixOutputs_32_2,
decoder_decoded_andMatrixOutputs_29_2,
decoder_decoded_andMatrixOutputs_4_2,
decoder_decoded_andMatrixOutputs_2_2};
assign io_sigs_fastpipe =
|{decoder_decoded_andMatrixOutputs_22_2,
decoder_decoded_andMatrixOutputs_14_2,
decoder_decoded_andMatrixOutputs_1_2,
decoder_decoded_andMatrixOutputs_12_2};
assign io_sigs_fma =
|{decoder_4,
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[27],
decoder_decoded_invInputs[28],
decoder_decoded_invInputs[29]},
decoder_6};
assign io_sigs_div =
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[24],
io_inst[27],
io_inst[28],
decoder_decoded_invInputs[27],
decoder_decoded_invInputs[28],
decoder_decoded_invInputs[29]};
assign io_sigs_sqrt = decoder_14;
assign io_sigs_wflags =
|{decoder_4,
decoder_decoded_andMatrixOutputs_0_2,
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[11],
decoder_decoded_invInputs[12],
decoder_decoded_invInputs[24],
io_inst[27],
decoder_decoded_invInputs[26],
io_inst[29],
decoder_decoded_invInputs[28],
decoder_decoded_invInputs[29]},
decoder_decoded_andMatrixOutputs_7_2,
decoder_decoded_andMatrixOutputs_5_2,
decoder_14,
decoder_decoded_andMatrixOutputs_32_2,
decoder_decoded_andMatrixOutputs_29_2,
&{io_inst[0],
io_inst[1],
decoder_decoded_invInputs[0],
decoder_decoded_invInputs[1],
io_inst[4],
decoder_decoded_invInputs[3],
io_inst[6],
decoder_decoded_invInputs[20],
decoder_decoded_invInputs[21],
decoder_decoded_invInputs[22],
decoder_decoded_invInputs[24],
decoder_decoded_invInputs[25],
decoder_decoded_invInputs[27],
io_inst[30],
io_inst[31]}};
endmodule
hardware/generated/genesys2-soc-verilog/FPUFMAPipe_l3_f32.sv
+51
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@@ -0,0 +1,51 @@
// Generated by CIRCT firtool-1.151.0
module FPUFMAPipe_l3_f32(
input clock,
reset,
io_in_valid,
io_in_bits_ren3,
io_in_bits_swap23,
input [2:0] io_in_bits_rm,
input [1:0] io_in_bits_fmaCmd,
input [64:0] io_in_bits_in1,
io_in_bits_in2,
io_in_bits_in3,
output [64:0] io_out_bits_data,
output [4:0] io_out_bits_exc
);
wire [32:0] _fma_io_out;
reg valid;
reg [2:0] in_rm;
reg [1:0] in_fmaCmd;
reg [64:0] in_in1;
reg [64:0] in_in2;
reg [64:0] in_in3;
always @(posedge clock) begin
valid <= io_in_valid;
if (io_in_valid) begin
in_rm <= io_in_bits_rm;
in_fmaCmd <= io_in_bits_fmaCmd;
in_in1 <= io_in_bits_in1;
in_in2 <= io_in_bits_swap23 ? 65'h80000000 : io_in_bits_in2;
in_in3 <=
io_in_bits_ren3 | io_in_bits_swap23
? io_in_bits_in3
: {32'h0, io_in_bits_in1[32] ^ io_in_bits_in2[32], 32'h0};
end
end // always @(posedge)
MulAddRecFNPipe_l2_e8_s24 fma (
.clock (clock),
.reset (reset),
.io_validin (valid),
.io_op (in_fmaCmd),
.io_a (in_in1[32:0]),
.io_b (in_in2[32:0]),
.io_c (in_in3[32:0]),
.io_roundingMode (in_rm),
.io_out (_fma_io_out),
.io_exceptionFlags (io_out_bits_exc)
);
assign io_out_bits_data = {32'h0, _fma_io_out};
endmodule
hardware/generated/genesys2-soc-verilog/FPUFMAPipe_l4_f64.sv
+62
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@@ -0,0 +1,62 @@
// Generated by CIRCT firtool-1.151.0
module FPUFMAPipe_l4_f64(
input clock,
reset,
io_in_valid,
io_in_bits_ren3,
io_in_bits_swap23,
input [2:0] io_in_bits_rm,
input [1:0] io_in_bits_fmaCmd,
input [64:0] io_in_bits_in1,
io_in_bits_in2,
io_in_bits_in3,
output [64:0] io_out_bits_data,
output [4:0] io_out_bits_exc
);
wire [64:0] _fma_io_out;
wire [4:0] _fma_io_exceptionFlags;
wire _fma_io_validout;
reg valid;
reg [2:0] in_rm;
reg [1:0] in_fmaCmd;
reg [64:0] in_in1;
reg [64:0] in_in2;
reg [64:0] in_in3;
reg [64:0] io_out_pipe_b_data;
reg [4:0] io_out_pipe_b_exc;
always @(posedge clock) begin
valid <= io_in_valid;
if (io_in_valid) begin
in_rm <= io_in_bits_rm;
in_fmaCmd <= io_in_bits_fmaCmd;
in_in1 <= io_in_bits_in1;
in_in2 <= io_in_bits_swap23 ? 65'h8000000000000000 : io_in_bits_in2;
in_in3 <=
io_in_bits_ren3 | io_in_bits_swap23
? io_in_bits_in3
: {io_in_bits_in1[64] ^ io_in_bits_in2[64], 64'h0};
end
if (_fma_io_validout) begin
io_out_pipe_b_data <=
({65{_fma_io_out[63:61] != 3'h7}} | 65'h1EFEFFFFFFFFFFFFF) & _fma_io_out;
io_out_pipe_b_exc <= _fma_io_exceptionFlags;
end
end // always @(posedge)
MulAddRecFNPipe_l2_e11_s53 fma (
.clock (clock),
.reset (reset),
.io_validin (valid),
.io_op (in_fmaCmd),
.io_a (in_in1),
.io_b (in_in2),
.io_c (in_in3),
.io_roundingMode (in_rm),
.io_out (_fma_io_out),
.io_exceptionFlags (_fma_io_exceptionFlags),
.io_validout (_fma_io_validout)
);
assign io_out_bits_data = io_out_pipe_b_data;
assign io_out_bits_exc = io_out_pipe_b_exc;
endmodule
hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_1.sv
+12
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@@ -0,0 +1,12 @@
// Generated by CIRCT firtool-1.151.0
module FixedClockBroadcast_1(
input auto_anon_in_clock,
auto_anon_in_reset,
output auto_anon_out_clock,
auto_anon_out_reset
);
assign auto_anon_out_clock = auto_anon_in_clock;
assign auto_anon_out_reset = auto_anon_in_reset;
endmodule
hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_3.sv
+20
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@@ -0,0 +1,20 @@
// Generated by CIRCT firtool-1.151.0
module FixedClockBroadcast_3(
input auto_anon_in_clock,
auto_anon_in_reset,
output auto_anon_out_2_clock,
auto_anon_out_2_reset,
auto_anon_out_1_clock,
auto_anon_out_1_reset,
auto_anon_out_0_clock,
auto_anon_out_0_reset
);
assign auto_anon_out_2_clock = auto_anon_in_clock;
assign auto_anon_out_2_reset = auto_anon_in_reset;
assign auto_anon_out_1_clock = auto_anon_in_clock;
assign auto_anon_out_1_reset = auto_anon_in_reset;
assign auto_anon_out_0_clock = auto_anon_in_clock;
assign auto_anon_out_0_reset = auto_anon_in_reset;
endmodule
hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_5.sv
+28
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@@ -0,0 +1,28 @@
// Generated by CIRCT firtool-1.151.0
module FixedClockBroadcast_5(
input auto_anon_in_clock,
auto_anon_in_reset,
output auto_anon_out_4_clock,
auto_anon_out_4_reset,
auto_anon_out_3_clock,
auto_anon_out_3_reset,
auto_anon_out_2_clock,
auto_anon_out_2_reset,
auto_anon_out_1_clock,
auto_anon_out_1_reset,
auto_anon_out_0_clock,
auto_anon_out_0_reset
);
assign auto_anon_out_4_clock = auto_anon_in_clock;
assign auto_anon_out_4_reset = auto_anon_in_reset;
assign auto_anon_out_3_clock = auto_anon_in_clock;
assign auto_anon_out_3_reset = auto_anon_in_reset;
assign auto_anon_out_2_clock = auto_anon_in_clock;
assign auto_anon_out_2_reset = auto_anon_in_reset;
assign auto_anon_out_1_clock = auto_anon_in_clock;
assign auto_anon_out_1_reset = auto_anon_in_reset;
assign auto_anon_out_0_clock = auto_anon_in_clock;
assign auto_anon_out_0_reset = auto_anon_in_reset;
endmodule
hardware/generated/genesys2-soc-verilog/FrontBus.sv
+256
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@@ -0,0 +1,256 @@
// Generated by CIRCT firtool-1.151.0
module FrontBus(
output auto_coupler_from_debug_sb_widget_anon_in_a_ready,
input auto_coupler_from_debug_sb_widget_anon_in_a_valid,
input [2:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode,
input [3:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_size,
input [31:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_address,
input [7:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_data,
input auto_coupler_from_debug_sb_widget_anon_in_d_ready,
output auto_coupler_from_debug_sb_widget_anon_in_d_valid,
output [2:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode,
output [1:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_param,
output [3:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_size,
output auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink,
auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied,
output [7:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_data,
output auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt,
input auto_fbus_clock_groups_in_member_fbus_0_clock,
auto_fbus_clock_groups_in_member_fbus_0_reset,
auto_bus_xing_out_a_ready,
output auto_bus_xing_out_a_valid,
output [2:0] auto_bus_xing_out_a_bits_opcode,
auto_bus_xing_out_a_bits_param,
output [3:0] auto_bus_xing_out_a_bits_size,
output auto_bus_xing_out_a_bits_source,
output [31:0] auto_bus_xing_out_a_bits_address,
output auto_bus_xing_out_a_bits_user_amba_prot_bufferable,
auto_bus_xing_out_a_bits_user_amba_prot_modifiable,
auto_bus_xing_out_a_bits_user_amba_prot_readalloc,
auto_bus_xing_out_a_bits_user_amba_prot_writealloc,
auto_bus_xing_out_a_bits_user_amba_prot_privileged,
auto_bus_xing_out_a_bits_user_amba_prot_secure,
auto_bus_xing_out_a_bits_user_amba_prot_fetch,
output [7:0] auto_bus_xing_out_a_bits_mask,
output [63:0] auto_bus_xing_out_a_bits_data,
output auto_bus_xing_out_a_bits_corrupt,
auto_bus_xing_out_d_ready,
input auto_bus_xing_out_d_valid,
input [2:0] auto_bus_xing_out_d_bits_opcode,
input [1:0] auto_bus_xing_out_d_bits_param,
input [3:0] auto_bus_xing_out_d_bits_size,
input auto_bus_xing_out_d_bits_sink,
auto_bus_xing_out_d_bits_denied,
input [63:0] auto_bus_xing_out_d_bits_data,
input auto_bus_xing_out_d_bits_corrupt
);
wire _coupler_from_debug_sb_auto_tl_out_a_valid;
wire [2:0] _coupler_from_debug_sb_auto_tl_out_a_bits_opcode;
wire [3:0] _coupler_from_debug_sb_auto_tl_out_a_bits_size;
wire [31:0] _coupler_from_debug_sb_auto_tl_out_a_bits_address;
wire [7:0] _coupler_from_debug_sb_auto_tl_out_a_bits_mask;
wire [63:0] _coupler_from_debug_sb_auto_tl_out_a_bits_data;
wire _coupler_from_debug_sb_auto_tl_out_d_ready;
wire _buffer_auto_in_a_ready;
wire _buffer_auto_in_d_valid;
wire [2:0] _buffer_auto_in_d_bits_opcode;
wire [1:0] _buffer_auto_in_d_bits_param;
wire [3:0] _buffer_auto_in_d_bits_size;
wire _buffer_auto_in_d_bits_sink;
wire _buffer_auto_in_d_bits_denied;
wire [63:0] _buffer_auto_in_d_bits_data;
wire _buffer_auto_in_d_bits_corrupt;
wire _fbus_xbar_auto_anon_in_a_ready;
wire _fbus_xbar_auto_anon_in_d_valid;
wire [2:0] _fbus_xbar_auto_anon_in_d_bits_opcode;
wire [1:0] _fbus_xbar_auto_anon_in_d_bits_param;
wire [3:0] _fbus_xbar_auto_anon_in_d_bits_size;
wire _fbus_xbar_auto_anon_in_d_bits_sink;
wire _fbus_xbar_auto_anon_in_d_bits_denied;
wire [63:0] _fbus_xbar_auto_anon_in_d_bits_data;
wire _fbus_xbar_auto_anon_in_d_bits_corrupt;
wire _fbus_xbar_auto_anon_out_a_valid;
wire [2:0] _fbus_xbar_auto_anon_out_a_bits_opcode;
wire [3:0] _fbus_xbar_auto_anon_out_a_bits_size;
wire [31:0] _fbus_xbar_auto_anon_out_a_bits_address;
wire [7:0] _fbus_xbar_auto_anon_out_a_bits_mask;
wire [63:0] _fbus_xbar_auto_anon_out_a_bits_data;
wire _fbus_xbar_auto_anon_out_d_ready;
wire _fixedClockNode_auto_anon_out_clock;
wire _fixedClockNode_auto_anon_out_reset;
wire _clockGroup_auto_out_clock;
wire _clockGroup_auto_out_reset;
wire _fbus_clock_groups_auto_out_member_pbus_0_clock;
wire _fbus_clock_groups_auto_out_member_pbus_0_reset;
ClockGroupAggregator_pbus fbus_clock_groups (
.auto_in_member_pbus_0_clock (auto_fbus_clock_groups_in_member_fbus_0_clock),
.auto_in_member_pbus_0_reset (auto_fbus_clock_groups_in_member_fbus_0_reset),
.auto_out_member_pbus_0_clock (_fbus_clock_groups_auto_out_member_pbus_0_clock),
.auto_out_member_pbus_0_reset (_fbus_clock_groups_auto_out_member_pbus_0_reset)
);
ClockGroup clockGroup (
.auto_in_member_sbus_0_clock (_fbus_clock_groups_auto_out_member_pbus_0_clock),
.auto_in_member_sbus_0_reset (_fbus_clock_groups_auto_out_member_pbus_0_reset),
.auto_out_clock (_clockGroup_auto_out_clock),
.auto_out_reset (_clockGroup_auto_out_reset)
);
FixedClockBroadcast_1 fixedClockNode (
.auto_anon_in_clock (_clockGroup_auto_out_clock),
.auto_anon_in_reset (_clockGroup_auto_out_reset),
.auto_anon_out_clock (_fixedClockNode_auto_anon_out_clock),
.auto_anon_out_reset (_fixedClockNode_auto_anon_out_reset)
);
TLXbar_fbus_i1_o1_a32d64s1k1z4u fbus_xbar (
.auto_anon_in_a_ready (_fbus_xbar_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_coupler_from_debug_sb_auto_tl_out_a_valid),
.auto_anon_in_a_bits_opcode (_coupler_from_debug_sb_auto_tl_out_a_bits_opcode),
.auto_anon_in_a_bits_size (_coupler_from_debug_sb_auto_tl_out_a_bits_size),
.auto_anon_in_a_bits_address (_coupler_from_debug_sb_auto_tl_out_a_bits_address),
.auto_anon_in_a_bits_mask (_coupler_from_debug_sb_auto_tl_out_a_bits_mask),
.auto_anon_in_a_bits_data (_coupler_from_debug_sb_auto_tl_out_a_bits_data),
.auto_anon_in_d_ready (_coupler_from_debug_sb_auto_tl_out_d_ready),
.auto_anon_in_d_valid (_fbus_xbar_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_fbus_xbar_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_fbus_xbar_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_fbus_xbar_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_sink (_fbus_xbar_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_fbus_xbar_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_fbus_xbar_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_fbus_xbar_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (_buffer_auto_in_a_ready),
.auto_anon_out_a_valid (_fbus_xbar_auto_anon_out_a_valid),
.auto_anon_out_a_bits_opcode (_fbus_xbar_auto_anon_out_a_bits_opcode),
.auto_anon_out_a_bits_size (_fbus_xbar_auto_anon_out_a_bits_size),
.auto_anon_out_a_bits_address (_fbus_xbar_auto_anon_out_a_bits_address),
.auto_anon_out_a_bits_mask (_fbus_xbar_auto_anon_out_a_bits_mask),
.auto_anon_out_a_bits_data (_fbus_xbar_auto_anon_out_a_bits_data),
.auto_anon_out_d_ready (_fbus_xbar_auto_anon_out_d_ready),
.auto_anon_out_d_valid (_buffer_auto_in_d_valid),
.auto_anon_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode),
.auto_anon_out_d_bits_param (_buffer_auto_in_d_bits_param),
.auto_anon_out_d_bits_size (_buffer_auto_in_d_bits_size),
.auto_anon_out_d_bits_sink (_buffer_auto_in_d_bits_sink),
.auto_anon_out_d_bits_denied (_buffer_auto_in_d_bits_denied),
.auto_anon_out_d_bits_data (_buffer_auto_in_d_bits_data),
.auto_anon_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt)
);
TLBuffer_a32d64s1k1z4u buffer (
.clock (_fixedClockNode_auto_anon_out_clock),
.reset (_fixedClockNode_auto_anon_out_reset),
.auto_in_a_ready (_buffer_auto_in_a_ready),
.auto_in_a_valid (_fbus_xbar_auto_anon_out_a_valid),
.auto_in_a_bits_opcode (_fbus_xbar_auto_anon_out_a_bits_opcode),
.auto_in_a_bits_param (3'h0),
.auto_in_a_bits_size (_fbus_xbar_auto_anon_out_a_bits_size),
.auto_in_a_bits_source (1'h0),
.auto_in_a_bits_address (_fbus_xbar_auto_anon_out_a_bits_address),
.auto_in_a_bits_user_amba_prot_bufferable (1'h0),
.auto_in_a_bits_user_amba_prot_modifiable (1'h0),
.auto_in_a_bits_user_amba_prot_readalloc (1'h0),
.auto_in_a_bits_user_amba_prot_writealloc (1'h0),
.auto_in_a_bits_user_amba_prot_privileged (1'h1),
.auto_in_a_bits_user_amba_prot_secure (1'h1),
.auto_in_a_bits_user_amba_prot_fetch (1'h0),
.auto_in_a_bits_mask (_fbus_xbar_auto_anon_out_a_bits_mask),
.auto_in_a_bits_data (_fbus_xbar_auto_anon_out_a_bits_data),
.auto_in_a_bits_corrupt (1'h0),
.auto_in_d_ready (_fbus_xbar_auto_anon_out_d_ready),
.auto_in_d_valid (_buffer_auto_in_d_valid),
.auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_buffer_auto_in_d_bits_param),
.auto_in_d_bits_size (_buffer_auto_in_d_bits_size),
.auto_in_d_bits_source (/* unused */),
.auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied),
.auto_in_d_bits_data (_buffer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt),
.auto_out_a_ready (auto_bus_xing_out_a_ready),
.auto_out_a_valid (auto_bus_xing_out_a_valid),
.auto_out_a_bits_opcode (auto_bus_xing_out_a_bits_opcode),
.auto_out_a_bits_param (auto_bus_xing_out_a_bits_param),
.auto_out_a_bits_size (auto_bus_xing_out_a_bits_size),
.auto_out_a_bits_source (auto_bus_xing_out_a_bits_source),
.auto_out_a_bits_address (auto_bus_xing_out_a_bits_address),
.auto_out_a_bits_user_amba_prot_bufferable
(auto_bus_xing_out_a_bits_user_amba_prot_bufferable),
.auto_out_a_bits_user_amba_prot_modifiable
(auto_bus_xing_out_a_bits_user_amba_prot_modifiable),
.auto_out_a_bits_user_amba_prot_readalloc
(auto_bus_xing_out_a_bits_user_amba_prot_readalloc),
.auto_out_a_bits_user_amba_prot_writealloc
(auto_bus_xing_out_a_bits_user_amba_prot_writealloc),
.auto_out_a_bits_user_amba_prot_privileged
(auto_bus_xing_out_a_bits_user_amba_prot_privileged),
.auto_out_a_bits_user_amba_prot_secure
(auto_bus_xing_out_a_bits_user_amba_prot_secure),
.auto_out_a_bits_user_amba_prot_fetch
(auto_bus_xing_out_a_bits_user_amba_prot_fetch),
.auto_out_a_bits_mask (auto_bus_xing_out_a_bits_mask),
.auto_out_a_bits_data (auto_bus_xing_out_a_bits_data),
.auto_out_a_bits_corrupt (auto_bus_xing_out_a_bits_corrupt),
.auto_out_d_ready (auto_bus_xing_out_d_ready),
.auto_out_d_valid (auto_bus_xing_out_d_valid),
.auto_out_d_bits_opcode (auto_bus_xing_out_d_bits_opcode),
.auto_out_d_bits_param (auto_bus_xing_out_d_bits_param),
.auto_out_d_bits_size (auto_bus_xing_out_d_bits_size),
.auto_out_d_bits_source (1'h0),
.auto_out_d_bits_sink (auto_bus_xing_out_d_bits_sink),
.auto_out_d_bits_denied (auto_bus_xing_out_d_bits_denied),
.auto_out_d_bits_data (auto_bus_xing_out_d_bits_data),
.auto_out_d_bits_corrupt (auto_bus_xing_out_d_bits_corrupt)
);
TLInterconnectCoupler_fbus_from_debug_sb coupler_from_debug_sb (
.clock (_fixedClockNode_auto_anon_out_clock),
.reset (_fixedClockNode_auto_anon_out_reset),
.auto_widget_anon_in_a_ready
(auto_coupler_from_debug_sb_widget_anon_in_a_ready),
.auto_widget_anon_in_a_valid
(auto_coupler_from_debug_sb_widget_anon_in_a_valid),
.auto_widget_anon_in_a_bits_opcode
(auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode),
.auto_widget_anon_in_a_bits_size
(auto_coupler_from_debug_sb_widget_anon_in_a_bits_size),
.auto_widget_anon_in_a_bits_address
(auto_coupler_from_debug_sb_widget_anon_in_a_bits_address),
.auto_widget_anon_in_a_bits_data
(auto_coupler_from_debug_sb_widget_anon_in_a_bits_data),
.auto_widget_anon_in_d_ready
(auto_coupler_from_debug_sb_widget_anon_in_d_ready),
.auto_widget_anon_in_d_valid
(auto_coupler_from_debug_sb_widget_anon_in_d_valid),
.auto_widget_anon_in_d_bits_opcode
(auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode),
.auto_widget_anon_in_d_bits_param
(auto_coupler_from_debug_sb_widget_anon_in_d_bits_param),
.auto_widget_anon_in_d_bits_size
(auto_coupler_from_debug_sb_widget_anon_in_d_bits_size),
.auto_widget_anon_in_d_bits_sink
(auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink),
.auto_widget_anon_in_d_bits_denied
(auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied),
.auto_widget_anon_in_d_bits_data
(auto_coupler_from_debug_sb_widget_anon_in_d_bits_data),
.auto_widget_anon_in_d_bits_corrupt
(auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt),
.auto_tl_out_a_ready (_fbus_xbar_auto_anon_in_a_ready),
.auto_tl_out_a_valid (_coupler_from_debug_sb_auto_tl_out_a_valid),
.auto_tl_out_a_bits_opcode
(_coupler_from_debug_sb_auto_tl_out_a_bits_opcode),
.auto_tl_out_a_bits_size (_coupler_from_debug_sb_auto_tl_out_a_bits_size),
.auto_tl_out_a_bits_address
(_coupler_from_debug_sb_auto_tl_out_a_bits_address),
.auto_tl_out_a_bits_mask (_coupler_from_debug_sb_auto_tl_out_a_bits_mask),
.auto_tl_out_a_bits_data (_coupler_from_debug_sb_auto_tl_out_a_bits_data),
.auto_tl_out_d_ready (_coupler_from_debug_sb_auto_tl_out_d_ready),
.auto_tl_out_d_valid (_fbus_xbar_auto_anon_in_d_valid),
.auto_tl_out_d_bits_opcode (_fbus_xbar_auto_anon_in_d_bits_opcode),
.auto_tl_out_d_bits_param (_fbus_xbar_auto_anon_in_d_bits_param),
.auto_tl_out_d_bits_size (_fbus_xbar_auto_anon_in_d_bits_size),
.auto_tl_out_d_bits_sink (_fbus_xbar_auto_anon_in_d_bits_sink),
.auto_tl_out_d_bits_denied (_fbus_xbar_auto_anon_in_d_bits_denied),
.auto_tl_out_d_bits_data (_fbus_xbar_auto_anon_in_d_bits_data),
.auto_tl_out_d_bits_corrupt (_fbus_xbar_auto_anon_in_d_bits_corrupt)
);
endmodule
hardware/generated/genesys2-soc-verilog/Frontend.sv
+265
View File
@@ -0,0 +1,265 @@
// Generated by CIRCT firtool-1.151.0
// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifndef PRINTF_COND_
`ifdef PRINTF_COND
`define PRINTF_COND_ (`PRINTF_COND)
`else // PRINTF_COND
`define PRINTF_COND_ 1
`endif // PRINTF_COND
`endif // not def PRINTF_COND_
module Frontend(
input clock,
reset,
auto_icache_master_out_a_ready,
output auto_icache_master_out_a_valid,
output [31:0] auto_icache_master_out_a_bits_address,
output auto_icache_master_out_a_bits_user_amba_prot_readalloc,
auto_icache_master_out_a_bits_user_amba_prot_writealloc,
input auto_icache_master_out_d_valid,
input [2:0] auto_icache_master_out_d_bits_opcode,
input [3:0] auto_icache_master_out_d_bits_size,
input [63:0] auto_icache_master_out_d_bits_data,
input auto_icache_master_out_d_bits_corrupt,
io_cpu_might_request,
io_cpu_req_valid,
input [33:0] io_cpu_req_bits_pc,
input io_cpu_req_bits_speculative,
io_cpu_resp_ready,
output io_cpu_resp_valid,
output [33:0] io_cpu_resp_bits_pc,
output [31:0] io_cpu_resp_bits_data,
output io_cpu_resp_bits_xcpt_pf_inst,
io_cpu_resp_bits_xcpt_gf_inst,
io_cpu_resp_bits_xcpt_ae_inst,
io_cpu_resp_bits_replay,
input io_cpu_btb_update_valid,
io_cpu_bht_update_valid,
io_cpu_flush_icache,
io_ptw_status_debug,
io_ptw_pmp_0_cfg_l,
input [1:0] io_ptw_pmp_0_cfg_a,
input io_ptw_pmp_0_cfg_x,
input [29:0] io_ptw_pmp_0_addr,
input [31:0] io_ptw_pmp_0_mask,
input io_ptw_pmp_1_cfg_l,
input [1:0] io_ptw_pmp_1_cfg_a,
input io_ptw_pmp_1_cfg_x,
input [29:0] io_ptw_pmp_1_addr,
input [31:0] io_ptw_pmp_1_mask,
input io_ptw_pmp_2_cfg_l,
input [1:0] io_ptw_pmp_2_cfg_a,
input io_ptw_pmp_2_cfg_x,
input [29:0] io_ptw_pmp_2_addr,
input [31:0] io_ptw_pmp_2_mask,
input io_ptw_pmp_3_cfg_l,
input [1:0] io_ptw_pmp_3_cfg_a,
input io_ptw_pmp_3_cfg_x,
input [29:0] io_ptw_pmp_3_addr,
input [31:0] io_ptw_pmp_3_mask,
input io_ptw_pmp_4_cfg_l,
input [1:0] io_ptw_pmp_4_cfg_a,
input io_ptw_pmp_4_cfg_x,
input [29:0] io_ptw_pmp_4_addr,
input [31:0] io_ptw_pmp_4_mask,
input io_ptw_pmp_5_cfg_l,
input [1:0] io_ptw_pmp_5_cfg_a,
input io_ptw_pmp_5_cfg_x,
input [29:0] io_ptw_pmp_5_addr,
input [31:0] io_ptw_pmp_5_mask,
input io_ptw_pmp_6_cfg_l,
input [1:0] io_ptw_pmp_6_cfg_a,
input io_ptw_pmp_6_cfg_x,
input [29:0] io_ptw_pmp_6_addr,
input [31:0] io_ptw_pmp_6_mask,
input io_ptw_pmp_7_cfg_l,
input [1:0] io_ptw_pmp_7_cfg_a,
input io_ptw_pmp_7_cfg_x,
input [29:0] io_ptw_pmp_7_addr,
input [31:0] io_ptw_pmp_7_mask,
input [63:0] io_ptw_customCSRs_csrs_0_value
);
wire [32:0] _io_cpu_npc_T;
wire fq_io_enq_valid;
wire [31:0] _tlb_io_resp_paddr;
wire _tlb_io_resp_pf_inst;
wire _tlb_io_resp_ae_inst;
wire _tlb_io_resp_cacheable;
wire _fq_io_enq_ready;
wire [4:0] _fq_io_mask;
wire _icache_io_resp_valid;
wire [31:0] _icache_io_resp_bits_data;
wire _icache_io_resp_bits_ae;
wire _GEN =
~(io_cpu_req_valid | io_cpu_flush_icache | io_cpu_bht_update_valid
| io_cpu_btb_update_valid) | io_cpu_might_request;
reg s1_valid;
reg s2_valid;
wire s0_valid =
io_cpu_req_valid | ~(_fq_io_mask[2]) | ~(_fq_io_mask[3]) & (~s1_valid | ~s2_valid)
| ~(_fq_io_mask[4]) & ~s1_valid & ~s2_valid;
reg [33:0] s1_pc;
reg s1_speculative;
reg [33:0] s2_pc;
reg s2_tlb_resp_pf_inst;
reg s2_tlb_resp_ae_inst;
reg s2_tlb_resp_cacheable;
wire _s2_xcpt_T = s2_tlb_resp_ae_inst | s2_tlb_resp_pf_inst;
reg s2_speculative;
wire [33:0] _ntpc_T = {s1_pc[33:2], 2'h0} + 34'h4;
reg s2_replay_REG;
wire s2_replay =
s2_valid & ~(_fq_io_enq_ready & fq_io_enq_valid) | s2_replay_REG;
wire icache_io_s2_kill =
s2_speculative & ~(s2_tlb_resp_cacheable & ~(io_ptw_customCSRs_csrs_0_value[3]))
| _s2_xcpt_T;
reg fq_io_enq_valid_REG;
assign fq_io_enq_valid =
fq_io_enq_valid_REG & s2_valid & (_icache_io_resp_valid | icache_io_s2_kill);
assign _io_cpu_npc_T =
io_cpu_req_valid ? io_cpu_req_bits_pc[33:1] : s2_replay ? s2_pc[33:1] : _ntpc_T[33:1];
wire _GEN_0 =
s2_speculative & io_ptw_customCSRs_csrs_0_value[3] & ~icache_io_s2_kill;
`ifndef SYNTHESIS
always @(posedge clock) begin
if ((`PRINTF_COND_) & ~reset & ~_GEN)
$fwrite(32'h80000002,
"Assertion failed\n at Frontend.scala:96 assert(!(io.cpu.req.valid || io.cpu.sfence.valid || io.cpu.flush_icache || io.cpu.bht_update.valid || io.cpu.btb_update.valid) || io.cpu.might_request)\n");
if ((`PRINTF_COND_) & ~reset & _GEN_0)
$fwrite(32'h80000002,
"Assertion failed\n at Frontend.scala:194 assert(!(s2_speculative && io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill && !icache.io.s2_kill))\n");
end // always @(posedge)
`endif // not def SYNTHESIS
always @(posedge clock) begin
if (~reset) begin
end
s1_valid <= s0_valid;
s1_pc <= {_io_cpu_npc_T, 1'h0};
s1_speculative <=
io_cpu_req_valid
? io_cpu_req_bits_speculative
: s2_replay ? s2_speculative : s1_speculative | s2_valid & ~s2_speculative;
if (~s2_replay) begin
s2_tlb_resp_pf_inst <= _tlb_io_resp_pf_inst;
s2_tlb_resp_ae_inst <= _tlb_io_resp_ae_inst;
s2_tlb_resp_cacheable <= _tlb_io_resp_cacheable;
end
fq_io_enq_valid_REG <= s1_valid;
if (reset) begin
s2_valid <= 1'h0;
s2_pc <= 34'h10000;
s2_speculative <= 1'h0;
s2_replay_REG <= 1'h1;
end
else begin
s2_valid <= ~s2_replay & ~io_cpu_req_valid;
if (~s2_replay) begin
s2_pc <= s1_pc;
s2_speculative <= s1_speculative;
end
s2_replay_REG <= s2_replay & ~s0_valid;
end
end // always @(posedge)
ICache icache (
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (auto_icache_master_out_a_ready),
.auto_master_out_a_valid (auto_icache_master_out_a_valid),
.auto_master_out_a_bits_address
(auto_icache_master_out_a_bits_address),
.auto_master_out_a_bits_user_amba_prot_readalloc
(auto_icache_master_out_a_bits_user_amba_prot_readalloc),
.auto_master_out_a_bits_user_amba_prot_writealloc
(auto_icache_master_out_a_bits_user_amba_prot_writealloc),
.auto_master_out_d_valid (auto_icache_master_out_d_valid),
.auto_master_out_d_bits_opcode
(auto_icache_master_out_d_bits_opcode),
.auto_master_out_d_bits_size
(auto_icache_master_out_d_bits_size),
.auto_master_out_d_bits_data
(auto_icache_master_out_d_bits_data),
.auto_master_out_d_bits_corrupt
(auto_icache_master_out_d_bits_corrupt),
.io_req_valid (s0_valid),
.io_req_bits_addr ({_io_cpu_npc_T[31:0], 1'h0}),
.io_s1_paddr (_tlb_io_resp_paddr),
.io_s1_kill (io_cpu_req_valid | s2_replay),
.io_s2_kill (icache_io_s2_kill),
.io_s2_cacheable (s2_tlb_resp_cacheable),
.io_resp_valid (_icache_io_resp_valid),
.io_resp_bits_data (_icache_io_resp_bits_data),
.io_resp_bits_ae (_icache_io_resp_bits_ae),
.io_invalidate (io_cpu_flush_icache)
);
ShiftQueue fq (
.clock (clock),
.reset (reset | io_cpu_req_valid),
.io_enq_ready (_fq_io_enq_ready),
.io_enq_valid (fq_io_enq_valid),
.io_enq_bits_pc (s2_pc),
.io_enq_bits_data (_icache_io_resp_bits_data),
.io_enq_bits_xcpt_pf_inst (s2_tlb_resp_pf_inst),
.io_enq_bits_xcpt_ae_inst
(_icache_io_resp_valid & _icache_io_resp_bits_ae | s2_tlb_resp_ae_inst),
.io_enq_bits_replay (icache_io_s2_kill & ~_icache_io_resp_valid & ~_s2_xcpt_T),
.io_deq_ready (io_cpu_resp_ready),
.io_deq_valid (io_cpu_resp_valid),
.io_deq_bits_pc (io_cpu_resp_bits_pc),
.io_deq_bits_data (io_cpu_resp_bits_data),
.io_deq_bits_xcpt_pf_inst (io_cpu_resp_bits_xcpt_pf_inst),
.io_deq_bits_xcpt_ae_inst (io_cpu_resp_bits_xcpt_ae_inst),
.io_deq_bits_replay (io_cpu_resp_bits_replay),
.io_mask (_fq_io_mask)
);
ITLB tlb (
.io_req_bits_vaddr (s1_pc),
.io_resp_paddr (_tlb_io_resp_paddr),
.io_resp_pf_inst (_tlb_io_resp_pf_inst),
.io_resp_ae_inst (_tlb_io_resp_ae_inst),
.io_resp_cacheable (_tlb_io_resp_cacheable),
.io_ptw_status_debug (io_ptw_status_debug),
.io_ptw_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l),
.io_ptw_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a),
.io_ptw_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x),
.io_ptw_pmp_0_addr (io_ptw_pmp_0_addr),
.io_ptw_pmp_0_mask (io_ptw_pmp_0_mask),
.io_ptw_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l),
.io_ptw_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a),
.io_ptw_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x),
.io_ptw_pmp_1_addr (io_ptw_pmp_1_addr),
.io_ptw_pmp_1_mask (io_ptw_pmp_1_mask),
.io_ptw_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l),
.io_ptw_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a),
.io_ptw_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x),
.io_ptw_pmp_2_addr (io_ptw_pmp_2_addr),
.io_ptw_pmp_2_mask (io_ptw_pmp_2_mask),
.io_ptw_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l),
.io_ptw_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a),
.io_ptw_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x),
.io_ptw_pmp_3_addr (io_ptw_pmp_3_addr),
.io_ptw_pmp_3_mask (io_ptw_pmp_3_mask),
.io_ptw_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l),
.io_ptw_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a),
.io_ptw_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x),
.io_ptw_pmp_4_addr (io_ptw_pmp_4_addr),
.io_ptw_pmp_4_mask (io_ptw_pmp_4_mask),
.io_ptw_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l),
.io_ptw_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a),
.io_ptw_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x),
.io_ptw_pmp_5_addr (io_ptw_pmp_5_addr),
.io_ptw_pmp_5_mask (io_ptw_pmp_5_mask),
.io_ptw_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l),
.io_ptw_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a),
.io_ptw_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x),
.io_ptw_pmp_6_addr (io_ptw_pmp_6_addr),
.io_ptw_pmp_6_mask (io_ptw_pmp_6_mask),
.io_ptw_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l),
.io_ptw_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a),
.io_ptw_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x),
.io_ptw_pmp_7_addr (io_ptw_pmp_7_addr),
.io_ptw_pmp_7_mask (io_ptw_pmp_7_mask)
);
assign io_cpu_resp_bits_xcpt_gf_inst = 1'h0;
endmodule
hardware/generated/genesys2-soc-verilog/HellaCacheArbiter.sv
+123
View File
@@ -0,0 +1,123 @@
// Generated by CIRCT firtool-1.151.0
module HellaCacheArbiter(
input clock,
output io_requestor_0_req_ready,
input io_requestor_0_req_valid,
input [33:0] io_requestor_0_req_bits_addr,
input [6:0] io_requestor_0_req_bits_tag,
input [4:0] io_requestor_0_req_bits_cmd,
input [1:0] io_requestor_0_req_bits_size,
input io_requestor_0_req_bits_signed,
io_requestor_0_s1_kill,
input [63:0] io_requestor_0_s1_data_data,
output io_requestor_0_s2_nack,
io_requestor_0_resp_valid,
output [6:0] io_requestor_0_resp_bits_tag,
output [1:0] io_requestor_0_resp_bits_size,
output [63:0] io_requestor_0_resp_bits_data,
output io_requestor_0_resp_bits_replay,
io_requestor_0_resp_bits_has_data,
output [63:0] io_requestor_0_resp_bits_data_word_bypass,
output io_requestor_0_replay_next,
io_requestor_0_s2_xcpt_ma_ld,
io_requestor_0_s2_xcpt_ma_st,
io_requestor_0_s2_xcpt_pf_ld,
io_requestor_0_s2_xcpt_pf_st,
io_requestor_0_s2_xcpt_ae_ld,
io_requestor_0_s2_xcpt_ae_st,
io_requestor_0_ordered,
io_requestor_0_perf_grant,
io_requestor_1_req_ready,
input io_requestor_1_req_valid,
input [33:0] io_requestor_1_req_bits_addr,
input [4:0] io_requestor_1_req_bits_cmd,
input [1:0] io_requestor_1_req_bits_size,
input io_requestor_1_s1_kill,
input [63:0] io_requestor_1_s1_data_data,
input [7:0] io_requestor_1_s1_data_mask,
output io_requestor_1_s2_nack,
io_requestor_1_resp_valid,
output [63:0] io_requestor_1_resp_bits_data_raw,
input io_mem_req_ready,
output io_mem_req_valid,
output [33:0] io_mem_req_bits_addr,
output [6:0] io_mem_req_bits_tag,
output [4:0] io_mem_req_bits_cmd,
output [1:0] io_mem_req_bits_size,
output io_mem_req_bits_signed,
output [1:0] io_mem_req_bits_dprv,
output io_mem_req_bits_no_xcpt,
io_mem_s1_kill,
output [63:0] io_mem_s1_data_data,
output [7:0] io_mem_s1_data_mask,
input io_mem_s2_nack,
io_mem_resp_valid,
input [6:0] io_mem_resp_bits_tag,
input [1:0] io_mem_resp_bits_size,
input [63:0] io_mem_resp_bits_data,
input io_mem_resp_bits_replay,
io_mem_resp_bits_has_data,
input [63:0] io_mem_resp_bits_data_word_bypass,
io_mem_resp_bits_data_raw,
input io_mem_replay_next,
io_mem_s2_xcpt_ma_ld,
io_mem_s2_xcpt_ma_st,
io_mem_s2_xcpt_pf_ld,
io_mem_s2_xcpt_pf_st,
io_mem_s2_xcpt_ae_ld,
io_mem_s2_xcpt_ae_st,
io_mem_ordered,
io_mem_perf_grant
);
reg s1_id;
reg s2_id;
always @(posedge clock) begin
s1_id <= ~io_requestor_0_req_valid;
s2_id <= s1_id;
end // always @(posedge)
assign io_requestor_0_req_ready = io_mem_req_ready;
assign io_requestor_0_s2_nack = io_mem_s2_nack & ~s2_id;
assign io_requestor_0_resp_valid = io_mem_resp_valid & ~(io_mem_resp_bits_tag[0]);
assign io_requestor_0_resp_bits_tag = {1'h0, io_mem_resp_bits_tag[6:1]};
assign io_requestor_0_resp_bits_size = io_mem_resp_bits_size;
assign io_requestor_0_resp_bits_data = io_mem_resp_bits_data;
assign io_requestor_0_resp_bits_replay = io_mem_resp_bits_replay;
assign io_requestor_0_resp_bits_has_data = io_mem_resp_bits_has_data;
assign io_requestor_0_resp_bits_data_word_bypass = io_mem_resp_bits_data_word_bypass;
assign io_requestor_0_replay_next = io_mem_replay_next;
assign io_requestor_0_s2_xcpt_ma_ld = io_mem_s2_xcpt_ma_ld;
assign io_requestor_0_s2_xcpt_ma_st = io_mem_s2_xcpt_ma_st;
assign io_requestor_0_s2_xcpt_pf_ld = io_mem_s2_xcpt_pf_ld;
assign io_requestor_0_s2_xcpt_pf_st = io_mem_s2_xcpt_pf_st;
assign io_requestor_0_s2_xcpt_ae_ld = io_mem_s2_xcpt_ae_ld;
assign io_requestor_0_s2_xcpt_ae_st = io_mem_s2_xcpt_ae_st;
assign io_requestor_0_ordered = io_mem_ordered;
assign io_requestor_0_perf_grant = io_mem_perf_grant;
assign io_requestor_1_req_ready = io_mem_req_ready & ~io_requestor_0_req_valid;
assign io_requestor_1_s2_nack = io_mem_s2_nack & s2_id;
assign io_requestor_1_resp_valid = io_mem_resp_valid & io_mem_resp_bits_tag[0];
assign io_requestor_1_resp_bits_data_raw = io_mem_resp_bits_data_raw;
assign io_mem_req_valid = io_requestor_0_req_valid | io_requestor_1_req_valid;
assign io_mem_req_bits_addr =
io_requestor_0_req_valid
? io_requestor_0_req_bits_addr
: io_requestor_1_req_bits_addr;
assign io_mem_req_bits_tag =
io_requestor_0_req_valid ? {io_requestor_0_req_bits_tag[5:0], 1'h0} : 7'h1;
assign io_mem_req_bits_cmd =
io_requestor_0_req_valid ? io_requestor_0_req_bits_cmd : io_requestor_1_req_bits_cmd;
assign io_mem_req_bits_size =
io_requestor_0_req_valid
? io_requestor_0_req_bits_size
: io_requestor_1_req_bits_size;
assign io_mem_req_bits_signed =
io_requestor_0_req_valid & io_requestor_0_req_bits_signed;
assign io_mem_req_bits_dprv = {2{io_requestor_0_req_valid}};
assign io_mem_req_bits_no_xcpt = ~io_requestor_0_req_valid;
assign io_mem_s1_kill = s1_id ? io_requestor_1_s1_kill : io_requestor_0_s1_kill;
assign io_mem_s1_data_data =
s1_id ? io_requestor_1_s1_data_data : io_requestor_0_s1_data_data;
assign io_mem_s1_data_mask = s1_id ? io_requestor_1_s1_data_mask : 8'h0;
endmodule
hardware/generated/genesys2-soc-verilog/HierarchicalElementResetDomain.sv
+144
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@@ -0,0 +1,144 @@
// Generated by CIRCT firtool-1.151.0
module HierarchicalElementResetDomain(
output auto_rockettile_buffer_in_a_ready,
input auto_rockettile_buffer_in_a_valid,
input [2:0] auto_rockettile_buffer_in_a_bits_opcode,
auto_rockettile_buffer_in_a_bits_param,
auto_rockettile_buffer_in_a_bits_size,
input [1:0] auto_rockettile_buffer_in_a_bits_source,
input [31:0] auto_rockettile_buffer_in_a_bits_address,
input [7:0] auto_rockettile_buffer_in_a_bits_mask,
input [63:0] auto_rockettile_buffer_in_a_bits_data,
input auto_rockettile_buffer_in_d_ready,
output auto_rockettile_buffer_in_d_valid,
output [2:0] auto_rockettile_buffer_in_d_bits_opcode,
auto_rockettile_buffer_in_d_bits_size,
output [1:0] auto_rockettile_buffer_in_d_bits_source,
output [63:0] auto_rockettile_buffer_in_d_bits_data,
input auto_rockettile_buffer_out_a_ready,
output auto_rockettile_buffer_out_a_valid,
output [2:0] auto_rockettile_buffer_out_a_bits_opcode,
auto_rockettile_buffer_out_a_bits_param,
output [3:0] auto_rockettile_buffer_out_a_bits_size,
output auto_rockettile_buffer_out_a_bits_source,
output [31:0] auto_rockettile_buffer_out_a_bits_address,
output auto_rockettile_buffer_out_a_bits_user_amba_prot_bufferable,
auto_rockettile_buffer_out_a_bits_user_amba_prot_modifiable,
auto_rockettile_buffer_out_a_bits_user_amba_prot_readalloc,
auto_rockettile_buffer_out_a_bits_user_amba_prot_writealloc,
auto_rockettile_buffer_out_a_bits_user_amba_prot_privileged,
auto_rockettile_buffer_out_a_bits_user_amba_prot_secure,
auto_rockettile_buffer_out_a_bits_user_amba_prot_fetch,
output [7:0] auto_rockettile_buffer_out_a_bits_mask,
output [63:0] auto_rockettile_buffer_out_a_bits_data,
output auto_rockettile_buffer_out_a_bits_corrupt,
auto_rockettile_buffer_out_d_ready,
input auto_rockettile_buffer_out_d_valid,
input [2:0] auto_rockettile_buffer_out_d_bits_opcode,
input [1:0] auto_rockettile_buffer_out_d_bits_param,
input [3:0] auto_rockettile_buffer_out_d_bits_size,
input auto_rockettile_buffer_out_d_bits_source,
auto_rockettile_buffer_out_d_bits_sink,
auto_rockettile_buffer_out_d_bits_denied,
input [63:0] auto_rockettile_buffer_out_d_bits_data,
input auto_rockettile_buffer_out_d_bits_corrupt,
output auto_rockettile_wfi_out_0,
input auto_rockettile_int_local_in_2_0,
auto_rockettile_int_local_in_1_0,
auto_rockettile_int_local_in_1_1,
auto_rockettile_int_local_in_0_0,
auto_clock_in_clock,
auto_clock_in_reset
);
RocketTile rockettile (
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_buffer_in_a_ready (auto_rockettile_buffer_in_a_ready),
.auto_buffer_in_a_valid (auto_rockettile_buffer_in_a_valid),
.auto_buffer_in_a_bits_opcode
(auto_rockettile_buffer_in_a_bits_opcode),
.auto_buffer_in_a_bits_param
(auto_rockettile_buffer_in_a_bits_param),
.auto_buffer_in_a_bits_size
(auto_rockettile_buffer_in_a_bits_size),
.auto_buffer_in_a_bits_source
(auto_rockettile_buffer_in_a_bits_source),
.auto_buffer_in_a_bits_address
(auto_rockettile_buffer_in_a_bits_address),
.auto_buffer_in_a_bits_mask
(auto_rockettile_buffer_in_a_bits_mask),
.auto_buffer_in_a_bits_data
(auto_rockettile_buffer_in_a_bits_data),
.auto_buffer_in_d_ready (auto_rockettile_buffer_in_d_ready),
.auto_buffer_in_d_valid (auto_rockettile_buffer_in_d_valid),
.auto_buffer_in_d_bits_opcode
(auto_rockettile_buffer_in_d_bits_opcode),
.auto_buffer_in_d_bits_size
(auto_rockettile_buffer_in_d_bits_size),
.auto_buffer_in_d_bits_source
(auto_rockettile_buffer_in_d_bits_source),
.auto_buffer_in_d_bits_data
(auto_rockettile_buffer_in_d_bits_data),
.auto_buffer_out_a_ready
(auto_rockettile_buffer_out_a_ready),
.auto_buffer_out_a_valid
(auto_rockettile_buffer_out_a_valid),
.auto_buffer_out_a_bits_opcode
(auto_rockettile_buffer_out_a_bits_opcode),
.auto_buffer_out_a_bits_param
(auto_rockettile_buffer_out_a_bits_param),
.auto_buffer_out_a_bits_size
(auto_rockettile_buffer_out_a_bits_size),
.auto_buffer_out_a_bits_source
(auto_rockettile_buffer_out_a_bits_source),
.auto_buffer_out_a_bits_address
(auto_rockettile_buffer_out_a_bits_address),
.auto_buffer_out_a_bits_user_amba_prot_bufferable
(auto_rockettile_buffer_out_a_bits_user_amba_prot_bufferable),
.auto_buffer_out_a_bits_user_amba_prot_modifiable
(auto_rockettile_buffer_out_a_bits_user_amba_prot_modifiable),
.auto_buffer_out_a_bits_user_amba_prot_readalloc
(auto_rockettile_buffer_out_a_bits_user_amba_prot_readalloc),
.auto_buffer_out_a_bits_user_amba_prot_writealloc
(auto_rockettile_buffer_out_a_bits_user_amba_prot_writealloc),
.auto_buffer_out_a_bits_user_amba_prot_privileged
(auto_rockettile_buffer_out_a_bits_user_amba_prot_privileged),
.auto_buffer_out_a_bits_user_amba_prot_secure
(auto_rockettile_buffer_out_a_bits_user_amba_prot_secure),
.auto_buffer_out_a_bits_user_amba_prot_fetch
(auto_rockettile_buffer_out_a_bits_user_amba_prot_fetch),
.auto_buffer_out_a_bits_mask
(auto_rockettile_buffer_out_a_bits_mask),
.auto_buffer_out_a_bits_data
(auto_rockettile_buffer_out_a_bits_data),
.auto_buffer_out_a_bits_corrupt
(auto_rockettile_buffer_out_a_bits_corrupt),
.auto_buffer_out_d_ready
(auto_rockettile_buffer_out_d_ready),
.auto_buffer_out_d_valid
(auto_rockettile_buffer_out_d_valid),
.auto_buffer_out_d_bits_opcode
(auto_rockettile_buffer_out_d_bits_opcode),
.auto_buffer_out_d_bits_param
(auto_rockettile_buffer_out_d_bits_param),
.auto_buffer_out_d_bits_size
(auto_rockettile_buffer_out_d_bits_size),
.auto_buffer_out_d_bits_source
(auto_rockettile_buffer_out_d_bits_source),
.auto_buffer_out_d_bits_sink
(auto_rockettile_buffer_out_d_bits_sink),
.auto_buffer_out_d_bits_denied
(auto_rockettile_buffer_out_d_bits_denied),
.auto_buffer_out_d_bits_data
(auto_rockettile_buffer_out_d_bits_data),
.auto_buffer_out_d_bits_corrupt
(auto_rockettile_buffer_out_d_bits_corrupt),
.auto_wfi_out_0 (auto_rockettile_wfi_out_0),
.auto_int_local_in_2_0 (auto_rockettile_int_local_in_2_0),
.auto_int_local_in_1_0 (auto_rockettile_int_local_in_1_0),
.auto_int_local_in_1_1 (auto_rockettile_int_local_in_1_1),
.auto_int_local_in_0_0 (auto_rockettile_int_local_in_0_0)
);
endmodule
hardware/generated/genesys2-soc-verilog/IBuf.sv
+132
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@@ -0,0 +1,132 @@
// Generated by CIRCT firtool-1.151.0
// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifndef PRINTF_COND_
`ifdef PRINTF_COND
`define PRINTF_COND_ (`PRINTF_COND)
`else // PRINTF_COND
`define PRINTF_COND_ 1
`endif // PRINTF_COND
`endif // not def PRINTF_COND_
module IBuf(
input clock,
reset,
output io_imem_ready,
input io_imem_valid,
input [33:0] io_imem_bits_pc,
input [31:0] io_imem_bits_data,
input io_imem_bits_xcpt_pf_inst,
io_imem_bits_xcpt_gf_inst,
io_imem_bits_xcpt_ae_inst,
io_imem_bits_replay,
io_kill,
output [33:0] io_pc,
input io_inst_0_ready,
output io_inst_0_valid,
io_inst_0_bits_xcpt0_pf_inst,
io_inst_0_bits_xcpt0_gf_inst,
io_inst_0_bits_xcpt0_ae_inst,
io_inst_0_bits_xcpt1_pf_inst,
io_inst_0_bits_xcpt1_gf_inst,
io_inst_0_bits_xcpt1_ae_inst,
io_inst_0_bits_replay,
io_inst_0_bits_rvc,
output [31:0] io_inst_0_bits_inst_bits,
output [4:0] io_inst_0_bits_inst_rd,
io_inst_0_bits_inst_rs1,
io_inst_0_bits_inst_rs2,
io_inst_0_bits_inst_rs3,
output [31:0] io_inst_0_bits_raw
);
wire [1:0] nReady;
wire _exp_io_rvc;
reg nBufValid;
reg [33:0] buf_pc;
reg [31:0] buf_data;
reg buf_xcpt_pf_inst;
reg buf_xcpt_gf_inst;
reg buf_xcpt_ae_inst;
reg buf_replay;
wire [1:0] _GEN = {1'h0, io_imem_bits_pc[1]};
wire [1:0] _nIC_T_2 = 2'h2 - _GEN;
wire [1:0] _GEN_0 = {1'h0, nBufValid};
wire [1:0] _nICReady_T = nReady - _GEN_0;
wire _nBufValid_T = nReady >= _GEN_0;
wire [1:0] _nBufValid_T_6 = _nIC_T_2 - _nICReady_T;
wire [190:0] _icData_T_4 =
{63'h0,
{4{io_imem_bits_data[31:16]}},
io_imem_bits_data,
{2{io_imem_bits_data[15:0]}}} << {185'h0, _GEN_0 - 2'h2 - _GEN, 4'h0};
wire [62:0] _icMask_T_2 = 63'hFFFFFFFF << {58'h0, nBufValid, 4'h0};
wire [31:0] inst =
_icData_T_4[95:64] & _icMask_T_2[31:0] | buf_data & ~(_icMask_T_2[31:0]);
wire [3:0] _valid_T = 4'h1 << (io_imem_valid ? _nIC_T_2 : 2'h0) + _GEN_0;
wire [1:0] _valid_T_1 = _valid_T[1:0] - 2'h1;
wire [1:0] _bufMask_T_1 = (2'h1 << _GEN_0) - 2'h1;
wire [1:0] buf_replay_0 = buf_replay ? _bufMask_T_1 : 2'h0;
wire [1:0] ic_replay =
buf_replay_0 | (io_imem_bits_replay ? _valid_T_1 & ~_bufMask_T_1 : 2'h0);
wire full_insn = _exp_io_rvc | _valid_T_1[1] | buf_replay_0[0];
wire [2:0] _io_inst_0_bits_xcpt1_WIRE_1 =
_exp_io_rvc
? 3'h0
: {_bufMask_T_1[1] ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst,
_bufMask_T_1[1] ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst,
_bufMask_T_1[1] ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst};
assign nReady = full_insn ? (_exp_io_rvc ? 2'h1 : 2'h2) : 2'h0;
always @(posedge clock) begin
automatic logic _GEN_1;
_GEN_1 = io_imem_valid & _nBufValid_T & _nICReady_T < _nIC_T_2 & ~(_nBufValid_T_6[1]);
if (reset)
nBufValid <= 1'h0;
else
nBufValid <=
~io_kill
& (io_inst_0_ready
? (_GEN_1
? _nBufValid_T_6[0]
: ~(_nBufValid_T | ~nBufValid) & nBufValid - nReady[0])
: nBufValid);
if (io_inst_0_ready & _GEN_1) begin
automatic logic [63:0] _buf_data_T_1 =
{{2{io_imem_bits_data[31:16]}}, io_imem_bits_data}
>> {58'h0, _GEN + _nICReady_T, 4'h0};
buf_pc <=
{io_imem_bits_pc[33:2], 2'h0}
| {32'h0, io_imem_bits_pc[1:0] + {_nICReady_T[0], 1'h0}};
buf_data <= {16'h0, _buf_data_T_1[15:0]};
buf_xcpt_pf_inst <= io_imem_bits_xcpt_pf_inst;
buf_xcpt_gf_inst <= io_imem_bits_xcpt_gf_inst;
buf_xcpt_ae_inst <= io_imem_bits_xcpt_ae_inst;
buf_replay <= io_imem_bits_replay;
end
end // always @(posedge)
RVCExpander exp (
.io_in (inst),
.io_out_bits (io_inst_0_bits_inst_bits),
.io_out_rd (io_inst_0_bits_inst_rd),
.io_out_rs1 (io_inst_0_bits_inst_rs1),
.io_out_rs2 (io_inst_0_bits_inst_rs2),
.io_out_rs3 (io_inst_0_bits_inst_rs3),
.io_rvc (_exp_io_rvc)
);
assign io_imem_ready =
io_inst_0_ready & _nBufValid_T & (_nICReady_T >= _nIC_T_2 | ~(_nBufValid_T_6[1]));
assign io_pc = nBufValid ? buf_pc : io_imem_bits_pc;
assign io_inst_0_valid = _valid_T_1[0] & full_insn;
assign io_inst_0_bits_xcpt0_pf_inst =
_bufMask_T_1[0] ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst;
assign io_inst_0_bits_xcpt0_gf_inst =
_bufMask_T_1[0] ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst;
assign io_inst_0_bits_xcpt0_ae_inst =
_bufMask_T_1[0] ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst;
assign io_inst_0_bits_xcpt1_pf_inst = _io_inst_0_bits_xcpt1_WIRE_1[2];
assign io_inst_0_bits_xcpt1_gf_inst = _io_inst_0_bits_xcpt1_WIRE_1[1];
assign io_inst_0_bits_xcpt1_ae_inst = _io_inst_0_bits_xcpt1_WIRE_1[0];
assign io_inst_0_bits_replay = ic_replay[0] | ~_exp_io_rvc & ic_replay[1];
assign io_inst_0_bits_rvc = _exp_io_rvc;
assign io_inst_0_bits_raw = inst;
endmodule
hardware/generated/genesys2-soc-verilog/ICache.sv
+160
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@@ -0,0 +1,160 @@
// Generated by CIRCT firtool-1.151.0
// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifndef PRINTF_COND_
`ifdef PRINTF_COND
`define PRINTF_COND_ (`PRINTF_COND)
`else // PRINTF_COND
`define PRINTF_COND_ 1
`endif // PRINTF_COND
`endif // not def PRINTF_COND_
module ICache(
input clock,
reset,
auto_master_out_a_ready,
output auto_master_out_a_valid,
output [31:0] auto_master_out_a_bits_address,
output auto_master_out_a_bits_user_amba_prot_readalloc,
auto_master_out_a_bits_user_amba_prot_writealloc,
input auto_master_out_d_valid,
input [2:0] auto_master_out_d_bits_opcode,
input [3:0] auto_master_out_d_bits_size,
input [63:0] auto_master_out_d_bits_data,
input auto_master_out_d_bits_corrupt,
io_req_valid,
input [32:0] io_req_bits_addr,
input [31:0] io_s1_paddr,
input io_s1_kill,
io_s2_kill,
io_s2_cacheable,
output io_resp_valid,
output [31:0] io_resp_bits_data,
output io_resp_bits_ae,
input io_invalidate
);
wire rockettile_icache_data_arrays_1_dout_1_en;
wire wen_1;
wire rockettile_icache_data_arrays_0_dout_en;
wire wen;
wire rockettile_icache_tag_array_tag_rdata_en;
wire [5:0] rockettile_icache_tag_array_tag_rdata_addr;
wire io_req_ready;
wire [31:0] _rockettile_icache_data_arrays_1_ext_RW0_rdata;
wire [31:0] _rockettile_icache_data_arrays_0_ext_RW0_rdata;
wire [20:0] _rockettile_icache_tag_array_ext_RW0_rdata;
wire s0_valid = io_req_ready & io_req_valid;
reg s1_valid;
reg s2_valid;
reg s2_hit;
reg invalidated;
reg refill_valid;
wire s2_miss = s2_valid & ~s2_hit & ~io_s2_kill;
reg s2_request_refill_REG;
wire s2_request_refill = s2_miss & s2_request_refill_REG;
reg [31:0] refill_paddr;
wire refill_one_beat =
auto_master_out_d_valid & auto_master_out_d_bits_opcode[0];
assign io_req_ready = ~refill_one_beat;
wire [26:0] _r_beats1_decode_T = 27'hFFF << auto_master_out_d_bits_size;
wire [8:0] r_beats1 =
auto_master_out_d_bits_opcode[0] ? ~(_r_beats1_decode_T[11:3]) : 9'h0;
reg [8:0] r_counter;
wire [8:0] _r_counter1_T = r_counter - 9'h1;
wire [8:0] refill_cnt = r_beats1 & ~_r_counter1_T;
wire refill_done = refill_one_beat & (r_counter == 9'h1 | r_beats1 == 9'h0);
assign rockettile_icache_tag_array_tag_rdata_addr = io_req_bits_addr[11:6];
assign rockettile_icache_tag_array_tag_rdata_en = ~refill_done & s0_valid;
reg accruedRefillError;
wire refillError =
auto_master_out_d_bits_corrupt | (|refill_cnt) & accruedRefillError;
reg [63:0] vb_array;
assign wen = refill_one_beat & ~invalidated;
wire [8:0] _mem_idx_T_6 = {refill_paddr[11:6], 3'h0};
assign rockettile_icache_data_arrays_0_dout_en =
~wen & s0_valid & ~(io_req_bits_addr[2]);
assign wen_1 = refill_one_beat & ~invalidated;
assign rockettile_icache_data_arrays_1_dout_1_en =
~wen_1 & s0_valid & io_req_bits_addr[2];
reg [31:0] s2_dout_0;
reg s2_tl_error;
always @(posedge clock) begin
automatic logic _s1_can_request_refill_T = s2_miss | refill_valid;
automatic logic [63:0] _s1_vb_T_1 = vb_array >> io_s1_paddr[11:6];
automatic logic tagMatch;
tagMatch =
_s1_vb_T_1[0]
& _rockettile_icache_tag_array_ext_RW0_rdata[19:0] == io_s1_paddr[31:12];
if (reset) begin
s1_valid <= 1'h0;
s2_valid <= 1'h0;
refill_valid <= 1'h0;
r_counter <= 9'h0;
vb_array <= 64'h0;
end
else begin
s1_valid <= s0_valid;
s2_valid <= s1_valid & ~io_s1_kill;
refill_valid <=
~refill_done & (auto_master_out_a_ready & s2_request_refill | refill_valid);
if (auto_master_out_d_valid)
r_counter <= r_counter == 9'h0 ? r_beats1 : _r_counter1_T;
if (io_invalidate)
vb_array <= 64'h0;
else if (refill_one_beat) begin
automatic logic [127:0] _vb_array_T_3 = 128'h1 << refill_paddr[11:6];
vb_array <=
refill_done & ~invalidated
? vb_array | _vb_array_T_3[63:0]
: ~(~vb_array | _vb_array_T_3[63:0]);
end
end
s2_hit <= tagMatch;
invalidated <= refill_valid & (io_invalidate | invalidated);
s2_request_refill_REG <= ~_s1_can_request_refill_T;
if (s1_valid & ~_s1_can_request_refill_T)
refill_paddr <= io_s1_paddr;
if (refill_one_beat)
accruedRefillError <= refillError;
if (s1_valid) begin
s2_dout_0 <=
io_s1_paddr[2]
? _rockettile_icache_data_arrays_1_ext_RW0_rdata
: _rockettile_icache_data_arrays_0_ext_RW0_rdata;
s2_tl_error <= tagMatch & _rockettile_icache_tag_array_ext_RW0_rdata[20];
end
end // always @(posedge)
rockettile_icache_tag_array_64x21 rockettile_icache_tag_array_ext (
.RW0_addr
(refill_done ? refill_paddr[11:6] : rockettile_icache_tag_array_tag_rdata_addr),
.RW0_en (rockettile_icache_tag_array_tag_rdata_en | refill_done),
.RW0_clk (clock),
.RW0_wmode (refill_one_beat),
.RW0_wdata ({refillError, refill_paddr[31:12]}),
.RW0_rdata (_rockettile_icache_tag_array_ext_RW0_rdata)
);
rockettile_icache_data_arrays_512x32 rockettile_icache_data_arrays_0_ext (
.RW0_addr (refill_one_beat ? _mem_idx_T_6 | refill_cnt : io_req_bits_addr[11:3]),
.RW0_en (rockettile_icache_data_arrays_0_dout_en | wen),
.RW0_clk (clock),
.RW0_wmode (refill_one_beat),
.RW0_wdata (auto_master_out_d_bits_data[31:0]),
.RW0_rdata (_rockettile_icache_data_arrays_0_ext_RW0_rdata)
);
rockettile_icache_data_arrays_512x32 rockettile_icache_data_arrays_1_ext (
.RW0_addr (refill_one_beat ? _mem_idx_T_6 | refill_cnt : io_req_bits_addr[11:3]),
.RW0_en (rockettile_icache_data_arrays_1_dout_1_en | wen_1),
.RW0_clk (clock),
.RW0_wmode (refill_one_beat),
.RW0_wdata (auto_master_out_d_bits_data[63:32]),
.RW0_rdata (_rockettile_icache_data_arrays_1_ext_RW0_rdata)
);
assign auto_master_out_a_valid = s2_request_refill;
assign auto_master_out_a_bits_address = {refill_paddr[31:6], 6'h0};
assign auto_master_out_a_bits_user_amba_prot_readalloc = io_s2_cacheable;
assign auto_master_out_a_bits_user_amba_prot_writealloc = io_s2_cacheable;
assign io_resp_valid = s2_valid & s2_hit;
assign io_resp_bits_data = s2_dout_0;
assign io_resp_bits_ae = s2_tl_error;
endmodule
hardware/generated/genesys2-soc-verilog/INToRecFN.sv
+151
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@@ -0,0 +1,151 @@
// Generated by CIRCT firtool-1.151.0
module INToRecFN(
input io_signedIn,
input [63:0] io_in,
input [2:0] io_roundingMode,
output [32:0] io_out,
output [4:0] io_exceptionFlags
);
wire intAsRawFloat_sign = io_signedIn & io_in[63];
wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? 64'h0 - io_in : io_in;
wire [5:0] intAsRawFloat_adjustedNormDist =
intAsRawFloat_absIn[63]
? 6'h0
: intAsRawFloat_absIn[62]
? 6'h1
: intAsRawFloat_absIn[61]
? 6'h2
: intAsRawFloat_absIn[60]
? 6'h3
: intAsRawFloat_absIn[59]
? 6'h4
: intAsRawFloat_absIn[58]
? 6'h5
: intAsRawFloat_absIn[57]
? 6'h6
: intAsRawFloat_absIn[56]
? 6'h7
: intAsRawFloat_absIn[55]
? 6'h8
: intAsRawFloat_absIn[54]
? 6'h9
: intAsRawFloat_absIn[53]
? 6'hA
: intAsRawFloat_absIn[52]
? 6'hB
: intAsRawFloat_absIn[51]
? 6'hC
: intAsRawFloat_absIn[50]
? 6'hD
: intAsRawFloat_absIn[49]
? 6'hE
: intAsRawFloat_absIn[48]
? 6'hF
: intAsRawFloat_absIn[47]
? 6'h10
: intAsRawFloat_absIn[46]
? 6'h11
: intAsRawFloat_absIn[45]
? 6'h12
: intAsRawFloat_absIn[44]
? 6'h13
: intAsRawFloat_absIn[43]
? 6'h14
: intAsRawFloat_absIn[42]
? 6'h15
: intAsRawFloat_absIn[41]
? 6'h16
: intAsRawFloat_absIn[40]
? 6'h17
: intAsRawFloat_absIn[39]
? 6'h18
: intAsRawFloat_absIn[38]
? 6'h19
: intAsRawFloat_absIn[37]
? 6'h1A
: intAsRawFloat_absIn[36]
? 6'h1B
: intAsRawFloat_absIn[35]
? 6'h1C
: intAsRawFloat_absIn[34]
? 6'h1D
: intAsRawFloat_absIn[33]
? 6'h1E
: intAsRawFloat_absIn[32]
? 6'h1F
: intAsRawFloat_absIn[31]
? 6'h20
: intAsRawFloat_absIn[30]
? 6'h21
: intAsRawFloat_absIn[29]
? 6'h22
: intAsRawFloat_absIn[28]
? 6'h23
: intAsRawFloat_absIn[27]
? 6'h24
: intAsRawFloat_absIn[26]
? 6'h25
: intAsRawFloat_absIn[25]
? 6'h26
: intAsRawFloat_absIn[24]
? 6'h27
: intAsRawFloat_absIn[23]
? 6'h28
: intAsRawFloat_absIn[22]
? 6'h29
: intAsRawFloat_absIn[21]
? 6'h2A
: intAsRawFloat_absIn[20]
? 6'h2B
: intAsRawFloat_absIn[19]
? 6'h2C
: intAsRawFloat_absIn[18]
? 6'h2D
: intAsRawFloat_absIn[17]
? 6'h2E
: intAsRawFloat_absIn[16]
? 6'h2F
: intAsRawFloat_absIn[15]
? 6'h30
: intAsRawFloat_absIn[14]
? 6'h31
: intAsRawFloat_absIn[13]
? 6'h32
: intAsRawFloat_absIn[12]
? 6'h33
: intAsRawFloat_absIn[11]
? 6'h34
: intAsRawFloat_absIn[10]
? 6'h35
: intAsRawFloat_absIn[9]
? 6'h36
: intAsRawFloat_absIn[8]
? 6'h37
: intAsRawFloat_absIn[7]
? 6'h38
: intAsRawFloat_absIn[6]
? 6'h39
: intAsRawFloat_absIn[5]
? 6'h3A
: intAsRawFloat_absIn[4]
? 6'h3B
: intAsRawFloat_absIn[3]
? 6'h3C
: intAsRawFloat_absIn[2]
? 6'h3D
: {5'h1F,
~(intAsRawFloat_absIn[1])};
wire [126:0] _intAsRawFloat_sig_T =
{63'h0, intAsRawFloat_absIn} << intAsRawFloat_adjustedNormDist;
RoundAnyRawFNToRecFN_1 roundAnyRawFNToRecFN (
.io_in_isZero (~(_intAsRawFloat_sig_T[63])),
.io_in_sign (intAsRawFloat_sign),
.io_in_sExp ({3'h2, ~intAsRawFloat_adjustedNormDist}),
.io_in_sig ({1'h0, _intAsRawFloat_sig_T[63:0]}),
.io_roundingMode (io_roundingMode),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule
hardware/generated/genesys2-soc-verilog/INToRecFN_1.sv
+151
View File
@@ -0,0 +1,151 @@
// Generated by CIRCT firtool-1.151.0
module INToRecFN_1(
input io_signedIn,
input [63:0] io_in,
input [2:0] io_roundingMode,
output [64:0] io_out,
output [4:0] io_exceptionFlags
);
wire intAsRawFloat_sign = io_signedIn & io_in[63];
wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? 64'h0 - io_in : io_in;
wire [5:0] intAsRawFloat_adjustedNormDist =
intAsRawFloat_absIn[63]
? 6'h0
: intAsRawFloat_absIn[62]
? 6'h1
: intAsRawFloat_absIn[61]
? 6'h2
: intAsRawFloat_absIn[60]
? 6'h3
: intAsRawFloat_absIn[59]
? 6'h4
: intAsRawFloat_absIn[58]
? 6'h5
: intAsRawFloat_absIn[57]
? 6'h6
: intAsRawFloat_absIn[56]
? 6'h7
: intAsRawFloat_absIn[55]
? 6'h8
: intAsRawFloat_absIn[54]
? 6'h9
: intAsRawFloat_absIn[53]
? 6'hA
: intAsRawFloat_absIn[52]
? 6'hB
: intAsRawFloat_absIn[51]
? 6'hC
: intAsRawFloat_absIn[50]
? 6'hD
: intAsRawFloat_absIn[49]
? 6'hE
: intAsRawFloat_absIn[48]
? 6'hF
: intAsRawFloat_absIn[47]
? 6'h10
: intAsRawFloat_absIn[46]
? 6'h11
: intAsRawFloat_absIn[45]
? 6'h12
: intAsRawFloat_absIn[44]
? 6'h13
: intAsRawFloat_absIn[43]
? 6'h14
: intAsRawFloat_absIn[42]
? 6'h15
: intAsRawFloat_absIn[41]
? 6'h16
: intAsRawFloat_absIn[40]
? 6'h17
: intAsRawFloat_absIn[39]
? 6'h18
: intAsRawFloat_absIn[38]
? 6'h19
: intAsRawFloat_absIn[37]
? 6'h1A
: intAsRawFloat_absIn[36]
? 6'h1B
: intAsRawFloat_absIn[35]
? 6'h1C
: intAsRawFloat_absIn[34]
? 6'h1D
: intAsRawFloat_absIn[33]
? 6'h1E
: intAsRawFloat_absIn[32]
? 6'h1F
: intAsRawFloat_absIn[31]
? 6'h20
: intAsRawFloat_absIn[30]
? 6'h21
: intAsRawFloat_absIn[29]
? 6'h22
: intAsRawFloat_absIn[28]
? 6'h23
: intAsRawFloat_absIn[27]
? 6'h24
: intAsRawFloat_absIn[26]
? 6'h25
: intAsRawFloat_absIn[25]
? 6'h26
: intAsRawFloat_absIn[24]
? 6'h27
: intAsRawFloat_absIn[23]
? 6'h28
: intAsRawFloat_absIn[22]
? 6'h29
: intAsRawFloat_absIn[21]
? 6'h2A
: intAsRawFloat_absIn[20]
? 6'h2B
: intAsRawFloat_absIn[19]
? 6'h2C
: intAsRawFloat_absIn[18]
? 6'h2D
: intAsRawFloat_absIn[17]
? 6'h2E
: intAsRawFloat_absIn[16]
? 6'h2F
: intAsRawFloat_absIn[15]
? 6'h30
: intAsRawFloat_absIn[14]
? 6'h31
: intAsRawFloat_absIn[13]
? 6'h32
: intAsRawFloat_absIn[12]
? 6'h33
: intAsRawFloat_absIn[11]
? 6'h34
: intAsRawFloat_absIn[10]
? 6'h35
: intAsRawFloat_absIn[9]
? 6'h36
: intAsRawFloat_absIn[8]
? 6'h37
: intAsRawFloat_absIn[7]
? 6'h38
: intAsRawFloat_absIn[6]
? 6'h39
: intAsRawFloat_absIn[5]
? 6'h3A
: intAsRawFloat_absIn[4]
? 6'h3B
: intAsRawFloat_absIn[3]
? 6'h3C
: intAsRawFloat_absIn[2]
? 6'h3D
: {5'h1F,
~(intAsRawFloat_absIn[1])};
wire [126:0] _intAsRawFloat_sig_T =
{63'h0, intAsRawFloat_absIn} << intAsRawFloat_adjustedNormDist;
RoundAnyRawFNToRecFN_2 roundAnyRawFNToRecFN (
.io_in_isZero (~(_intAsRawFloat_sig_T[63])),
.io_in_sign (intAsRawFloat_sign),
.io_in_sExp ({3'h2, ~intAsRawFloat_adjustedNormDist}),
.io_in_sig ({1'h0, _intAsRawFloat_sig_T[63:0]}),
.io_roundingMode (io_roundingMode),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule
hardware/generated/genesys2-soc-verilog/ITLB.sv
+318
View File
@@ -0,0 +1,318 @@
// Generated by CIRCT firtool-1.151.0
module ITLB(
input [33:0] io_req_bits_vaddr,
output [31:0] io_resp_paddr,
output io_resp_pf_inst,
io_resp_ae_inst,
io_resp_cacheable,
input io_ptw_status_debug,
io_ptw_pmp_0_cfg_l,
input [1:0] io_ptw_pmp_0_cfg_a,
input io_ptw_pmp_0_cfg_x,
input [29:0] io_ptw_pmp_0_addr,
input [31:0] io_ptw_pmp_0_mask,
input io_ptw_pmp_1_cfg_l,
input [1:0] io_ptw_pmp_1_cfg_a,
input io_ptw_pmp_1_cfg_x,
input [29:0] io_ptw_pmp_1_addr,
input [31:0] io_ptw_pmp_1_mask,
input io_ptw_pmp_2_cfg_l,
input [1:0] io_ptw_pmp_2_cfg_a,
input io_ptw_pmp_2_cfg_x,
input [29:0] io_ptw_pmp_2_addr,
input [31:0] io_ptw_pmp_2_mask,
input io_ptw_pmp_3_cfg_l,
input [1:0] io_ptw_pmp_3_cfg_a,
input io_ptw_pmp_3_cfg_x,
input [29:0] io_ptw_pmp_3_addr,
input [31:0] io_ptw_pmp_3_mask,
input io_ptw_pmp_4_cfg_l,
input [1:0] io_ptw_pmp_4_cfg_a,
input io_ptw_pmp_4_cfg_x,
input [29:0] io_ptw_pmp_4_addr,
input [31:0] io_ptw_pmp_4_mask,
input io_ptw_pmp_5_cfg_l,
input [1:0] io_ptw_pmp_5_cfg_a,
input io_ptw_pmp_5_cfg_x,
input [29:0] io_ptw_pmp_5_addr,
input [31:0] io_ptw_pmp_5_mask,
input io_ptw_pmp_6_cfg_l,
input [1:0] io_ptw_pmp_6_cfg_a,
input io_ptw_pmp_6_cfg_x,
input [29:0] io_ptw_pmp_6_addr,
input [31:0] io_ptw_pmp_6_mask,
input io_ptw_pmp_7_cfg_l,
input [1:0] io_ptw_pmp_7_cfg_a,
input io_ptw_pmp_7_cfg_x,
input [29:0] io_ptw_pmp_7_addr,
input [31:0] io_ptw_pmp_7_mask
);
wire _pma_io_resp_x;
wire _pmp_io_x;
PMPChecker_s2 pmp (
.io_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l),
.io_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a),
.io_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x),
.io_pmp_0_addr (io_ptw_pmp_0_addr),
.io_pmp_0_mask (io_ptw_pmp_0_mask),
.io_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l),
.io_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a),
.io_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x),
.io_pmp_1_addr (io_ptw_pmp_1_addr),
.io_pmp_1_mask (io_ptw_pmp_1_mask),
.io_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l),
.io_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a),
.io_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x),
.io_pmp_2_addr (io_ptw_pmp_2_addr),
.io_pmp_2_mask (io_ptw_pmp_2_mask),
.io_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l),
.io_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a),
.io_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x),
.io_pmp_3_addr (io_ptw_pmp_3_addr),
.io_pmp_3_mask (io_ptw_pmp_3_mask),
.io_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l),
.io_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a),
.io_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x),
.io_pmp_4_addr (io_ptw_pmp_4_addr),
.io_pmp_4_mask (io_ptw_pmp_4_mask),
.io_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l),
.io_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a),
.io_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x),
.io_pmp_5_addr (io_ptw_pmp_5_addr),
.io_pmp_5_mask (io_ptw_pmp_5_mask),
.io_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l),
.io_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a),
.io_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x),
.io_pmp_6_addr (io_ptw_pmp_6_addr),
.io_pmp_6_mask (io_ptw_pmp_6_mask),
.io_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l),
.io_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a),
.io_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x),
.io_pmp_7_addr (io_ptw_pmp_7_addr),
.io_pmp_7_mask (io_ptw_pmp_7_mask),
.io_addr (io_req_bits_vaddr[31:0]),
.io_x (_pmp_io_x)
);
PMAChecker pma (
.io_paddr (io_req_bits_vaddr),
.io_resp_r (/* unused */),
.io_resp_w (/* unused */),
.io_resp_pp (/* unused */),
.io_resp_al (/* unused */),
.io_resp_aa (/* unused */),
.io_resp_x (_pma_io_resp_x),
.io_resp_eff (/* unused */)
);
OptimizationBarrier_TLBEntryData entries_barrier (
.io_x_u (1'h0),
.io_x_ae_ptw (1'h0),
.io_x_ae_final (1'h0),
.io_x_pf (1'h0),
.io_x_gf (1'h0),
.io_x_sw (1'h0),
.io_x_sx (1'h0),
.io_x_sr (1'h0),
.io_x_pw (1'h0),
.io_x_px (1'h0),
.io_x_pr (1'h0),
.io_x_ppp (1'h0),
.io_x_pal (1'h0),
.io_x_paa (1'h0),
.io_x_eff (1'h0),
.io_x_c (1'h0),
.io_y_u (/* unused */),
.io_y_ae_ptw (/* unused */),
.io_y_ae_final (/* unused */),
.io_y_pf (/* unused */),
.io_y_gf (/* unused */),
.io_y_sw (/* unused */),
.io_y_sx (/* unused */),
.io_y_sr (/* unused */),
.io_y_pw (/* unused */),
.io_y_px (/* unused */),
.io_y_pr (/* unused */),
.io_y_ppp (/* unused */),
.io_y_pal (/* unused */),
.io_y_paa (/* unused */),
.io_y_eff (/* unused */),
.io_y_c (/* unused */)
);
OptimizationBarrier_TLBEntryData entries_barrier_1 (
.io_x_u (1'h0),
.io_x_ae_ptw (1'h0),
.io_x_ae_final (1'h0),
.io_x_pf (1'h0),
.io_x_gf (1'h0),
.io_x_sw (1'h0),
.io_x_sx (1'h0),
.io_x_sr (1'h0),
.io_x_pw (1'h0),
.io_x_px (1'h0),
.io_x_pr (1'h0),
.io_x_ppp (1'h0),
.io_x_pal (1'h0),
.io_x_paa (1'h0),
.io_x_eff (1'h0),
.io_x_c (1'h0),
.io_y_u (/* unused */),
.io_y_ae_ptw (/* unused */),
.io_y_ae_final (/* unused */),
.io_y_pf (/* unused */),
.io_y_gf (/* unused */),
.io_y_sw (/* unused */),
.io_y_sx (/* unused */),
.io_y_sr (/* unused */),
.io_y_pw (/* unused */),
.io_y_px (/* unused */),
.io_y_pr (/* unused */),
.io_y_ppp (/* unused */),
.io_y_pal (/* unused */),
.io_y_paa (/* unused */),
.io_y_eff (/* unused */),
.io_y_c (/* unused */)
);
OptimizationBarrier_TLBEntryData entries_barrier_2 (
.io_x_u (1'h0),
.io_x_ae_ptw (1'h0),
.io_x_ae_final (1'h0),
.io_x_pf (1'h0),
.io_x_gf (1'h0),
.io_x_sw (1'h0),
.io_x_sx (1'h0),
.io_x_sr (1'h0),
.io_x_pw (1'h0),
.io_x_px (1'h0),
.io_x_pr (1'h0),
.io_x_ppp (1'h0),
.io_x_pal (1'h0),
.io_x_paa (1'h0),
.io_x_eff (1'h0),
.io_x_c (1'h0),
.io_y_u (/* unused */),
.io_y_ae_ptw (/* unused */),
.io_y_ae_final (/* unused */),
.io_y_pf (/* unused */),
.io_y_gf (/* unused */),
.io_y_sw (/* unused */),
.io_y_sx (/* unused */),
.io_y_sr (/* unused */),
.io_y_pw (/* unused */),
.io_y_px (/* unused */),
.io_y_pr (/* unused */),
.io_y_ppp (/* unused */),
.io_y_pal (/* unused */),
.io_y_paa (/* unused */),
.io_y_eff (/* unused */),
.io_y_c (/* unused */)
);
OptimizationBarrier_TLBEntryData entries_barrier_3 (
.io_x_u (1'h0),
.io_x_ae_ptw (1'h0),
.io_x_ae_final (1'h0),
.io_x_pf (1'h0),
.io_x_gf (1'h0),
.io_x_sw (1'h0),
.io_x_sx (1'h0),
.io_x_sr (1'h0),
.io_x_pw (1'h0),
.io_x_px (1'h0),
.io_x_pr (1'h0),
.io_x_ppp (1'h0),
.io_x_pal (1'h0),
.io_x_paa (1'h0),
.io_x_eff (1'h0),
.io_x_c (1'h0),
.io_y_u (/* unused */),
.io_y_ae_ptw (/* unused */),
.io_y_ae_final (/* unused */),
.io_y_pf (/* unused */),
.io_y_gf (/* unused */),
.io_y_sw (/* unused */),
.io_y_sx (/* unused */),
.io_y_sr (/* unused */),
.io_y_pw (/* unused */),
.io_y_px (/* unused */),
.io_y_pr (/* unused */),
.io_y_ppp (/* unused */),
.io_y_pal (/* unused */),
.io_y_paa (/* unused */),
.io_y_eff (/* unused */),
.io_y_c (/* unused */)
);
OptimizationBarrier_TLBEntryData entries_barrier_4 (
.io_x_u (1'h0),
.io_x_ae_ptw (1'h0),
.io_x_ae_final (1'h0),
.io_x_pf (1'h0),
.io_x_gf (1'h0),
.io_x_sw (1'h0),
.io_x_sx (1'h0),
.io_x_sr (1'h0),
.io_x_pw (1'h0),
.io_x_px (1'h0),
.io_x_pr (1'h0),
.io_x_ppp (1'h0),
.io_x_pal (1'h0),
.io_x_paa (1'h0),
.io_x_eff (1'h0),
.io_x_c (1'h0),
.io_y_u (/* unused */),
.io_y_ae_ptw (/* unused */),
.io_y_ae_final (/* unused */),
.io_y_pf (/* unused */),
.io_y_gf (/* unused */),
.io_y_sw (/* unused */),
.io_y_sx (/* unused */),
.io_y_sr (/* unused */),
.io_y_pw (/* unused */),
.io_y_px (/* unused */),
.io_y_pr (/* unused */),
.io_y_ppp (/* unused */),
.io_y_pal (/* unused */),
.io_y_paa (/* unused */),
.io_y_eff (/* unused */),
.io_y_c (/* unused */)
);
OptimizationBarrier_TLBEntryData entries_barrier_5 (
.io_x_u (1'h0),
.io_x_ae_ptw (1'h0),
.io_x_ae_final (1'h0),
.io_x_pf (1'h0),
.io_x_gf (1'h0),
.io_x_sw (1'h0),
.io_x_sx (1'h0),
.io_x_sr (1'h0),
.io_x_pw (1'h0),
.io_x_px (1'h0),
.io_x_pr (1'h0),
.io_x_ppp (1'h0),
.io_x_pal (1'h0),
.io_x_paa (1'h0),
.io_x_eff (1'h0),
.io_x_c (1'h0),
.io_y_u (/* unused */),
.io_y_ae_ptw (/* unused */),
.io_y_ae_final (/* unused */),
.io_y_pf (/* unused */),
.io_y_gf (/* unused */),
.io_y_sw (/* unused */),
.io_y_sx (/* unused */),
.io_y_sr (/* unused */),
.io_y_pw (/* unused */),
.io_y_px (/* unused */),
.io_y_pr (/* unused */),
.io_y_ppp (/* unused */),
.io_y_pal (/* unused */),
.io_y_paa (/* unused */),
.io_y_eff (/* unused */),
.io_y_c (/* unused */)
);
assign io_resp_paddr = io_req_bits_vaddr[31:0];
assign io_resp_pf_inst = 1'h0;
assign io_resp_ae_inst =
~(_pma_io_resp_x & ~(~io_ptw_status_debug & io_req_bits_vaddr[33:12] == 22'h0)
& _pmp_io_x);
assign io_resp_cacheable = 1'h0;
endmodule
hardware/generated/genesys2-soc-verilog/IntSyncAsyncCrossingSink_n1x1.sv
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// Generated by CIRCT firtool-1.151.0
module IntSyncAsyncCrossingSink_n1x1(
input clock,
auto_in_sync_0,
output auto_out_0
);
SynchronizerShiftReg_w1_d3 chain (
.clock (clock),
.io_d (auto_in_sync_0),
.io_q (auto_out_0)
);
endmodule
hardware/generated/genesys2-soc-verilog/IntSyncCrossingSource_n1x1.sv
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// Generated by CIRCT firtool-1.151.0
module IntSyncCrossingSource_n1x1(
input clock,
reset,
auto_in_0,
output auto_out_sync_0
);
AsyncResetRegVec_w1_i0 reg_0 (
.clock (clock),
.reset (reset),
.io_d (auto_in_0),
.io_q (auto_out_sync_0)
);
endmodule
hardware/generated/genesys2-soc-verilog/IntSyncCrossingSource_n1x1_Registered.sv
+9
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// Generated by CIRCT firtool-1.151.0
module IntSyncCrossingSource_n1x1_Registered(
input auto_in_0,
output auto_out_sync_0
);
assign auto_out_sync_0 = auto_in_0;
endmodule
hardware/generated/genesys2-soc-verilog/IntSyncCrossingSource_n1x2.sv
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// Generated by CIRCT firtool-1.151.0
module IntSyncCrossingSource_n1x2(
input clock,
reset,
auto_in_0,
auto_in_1,
output auto_out_sync_0,
auto_out_sync_1
);
wire [1:0] _reg_io_q;
AsyncResetRegVec_w2_i0 reg_0 (
.clock (clock),
.reset (reset),
.io_d ({auto_in_1, auto_in_0}),
.io_q (_reg_io_q)
);
assign auto_out_sync_0 = _reg_io_q[0];
assign auto_out_sync_1 = _reg_io_q[1];
endmodule
hardware/generated/genesys2-soc-verilog/IntSyncSyncCrossingSink_n1x1.sv
+9
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// Generated by CIRCT firtool-1.151.0
module IntSyncSyncCrossingSink_n1x1(
input auto_in_sync_0,
output auto_out_0
);
assign auto_out_0 = auto_in_sync_0;
endmodule
hardware/generated/genesys2-soc-verilog/IntSyncSyncCrossingSink_n1x2.sv
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// Generated by CIRCT firtool-1.151.0
module IntSyncSyncCrossingSink_n1x2(
input auto_in_sync_0,
auto_in_sync_1,
output auto_out_0,
auto_out_1
);
assign auto_out_0 = auto_in_sync_0;
assign auto_out_1 = auto_in_sync_1;
endmodule
hardware/generated/genesys2-soc-verilog/IntToFP.sv
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// Generated by CIRCT firtool-1.151.0
module IntToFP(
input clock,
reset,
io_in_valid,
input [1:0] io_in_bits_typeTagIn,
input io_in_bits_wflags,
input [2:0] io_in_bits_rm,
input [1:0] io_in_bits_typ,
input [63:0] io_in_bits_in1,
output [64:0] io_out_bits_data,
output [4:0] io_out_bits_exc
);
wire [64:0] _i2fResults_i2f_1_io_out;
wire [4:0] _i2fResults_i2f_1_io_exceptionFlags;
wire [32:0] _i2fResults_i2f_io_out;
wire [4:0] _i2fResults_i2f_io_exceptionFlags;
reg in_pipe_v;
reg [1:0] in_pipe_b_typeTagIn;
reg in_pipe_b_wflags;
reg [2:0] in_pipe_b_rm;
reg [1:0] in_pipe_b_typ;
reg [63:0] in_pipe_b_in1;
wire [63:0] intValue_res =
in_pipe_b_typ[1]
? in_pipe_b_in1
: {{32{~(in_pipe_b_typ[0]) & in_pipe_b_in1[31]}}, in_pipe_b_in1[31:0]};
reg [64:0] io_out_pipe_b_data;
reg [4:0] io_out_pipe_b_exc;
always @(posedge clock) begin
if (reset)
in_pipe_v <= 1'h0;
else
in_pipe_v <= io_in_valid;
if (io_in_valid) begin
in_pipe_b_typeTagIn <= io_in_bits_typeTagIn;
in_pipe_b_wflags <= io_in_bits_wflags;
in_pipe_b_rm <= io_in_bits_rm;
in_pipe_b_typ <= io_in_bits_typ;
in_pipe_b_in1 <= io_in_bits_in1;
end
if (in_pipe_v) begin
automatic logic [63:0] _mux_data_T_2 =
(in_pipe_b_typeTagIn[0] ? 64'h0 : 64'hFFFFFFFF00000000) | in_pipe_b_in1;
automatic logic mux_data_rawIn_isZeroExpIn = _mux_data_T_2[62:52] == 11'h0;
automatic logic _mux_data_rawIn_out_isNaN_T = |(_mux_data_T_2[51:0]);
automatic logic [5:0] mux_data_rawIn_normDist =
_mux_data_T_2[51]
? 6'h0
: _mux_data_T_2[50]
? 6'h1
: _mux_data_T_2[49]
? 6'h2
: _mux_data_T_2[48]
? 6'h3
: _mux_data_T_2[47]
? 6'h4
: _mux_data_T_2[46]
? 6'h5
: _mux_data_T_2[45]
? 6'h6
: _mux_data_T_2[44]
? 6'h7
: _mux_data_T_2[43]
? 6'h8
: _mux_data_T_2[42]
? 6'h9
: _mux_data_T_2[41]
? 6'hA
: _mux_data_T_2[40]
? 6'hB
: _mux_data_T_2[39]
? 6'hC
: _mux_data_T_2[38]
? 6'hD
: _mux_data_T_2[37]
? 6'hE
: _mux_data_T_2[36]
? 6'hF
: _mux_data_T_2[35]
? 6'h10
: _mux_data_T_2[34]
? 6'h11
: _mux_data_T_2[33]
? 6'h12
: _mux_data_T_2[32]
? 6'h13
: _mux_data_T_2[31]
? 6'h14
: _mux_data_T_2[30]
? 6'h15
: _mux_data_T_2[29]
? 6'h16
: _mux_data_T_2[28]
? 6'h17
: _mux_data_T_2[27]
? 6'h18
: _mux_data_T_2[26]
? 6'h19
: _mux_data_T_2[25]
? 6'h1A
: _mux_data_T_2[24]
? 6'h1B
: _mux_data_T_2[23]
? 6'h1C
: _mux_data_T_2[22]
? 6'h1D
: _mux_data_T_2[21]
? 6'h1E
: _mux_data_T_2[20]
? 6'h1F
: _mux_data_T_2[19]
? 6'h20
: _mux_data_T_2[18]
? 6'h21
: _mux_data_T_2[17]
? 6'h22
: _mux_data_T_2[16]
? 6'h23
: _mux_data_T_2[15]
? 6'h24
: _mux_data_T_2[14]
? 6'h25
: _mux_data_T_2[13]
? 6'h26
: _mux_data_T_2[12]
? 6'h27
: _mux_data_T_2[11]
? 6'h28
: _mux_data_T_2[10]
? 6'h29
: _mux_data_T_2[9]
? 6'h2A
: _mux_data_T_2[8]
? 6'h2B
: _mux_data_T_2[7]
? 6'h2C
: _mux_data_T_2[6]
? 6'h2D
: _mux_data_T_2[5]
? 6'h2E
: _mux_data_T_2[4]
? 6'h2F
: _mux_data_T_2[3]
? 6'h30
: _mux_data_T_2[2]
? 6'h31
: {5'h19,
~(_mux_data_T_2[1])};
automatic logic [11:0] _mux_data_rawIn_adjustedExp_T_4 =
(mux_data_rawIn_isZeroExpIn
? {6'h3F, ~mux_data_rawIn_normDist}
: {1'h0, _mux_data_T_2[62:52]})
+ {10'h100, mux_data_rawIn_isZeroExpIn ? 2'h2 : 2'h1};
automatic logic [114:0] _mux_data_rawIn_subnormFract_T =
{63'h0, _mux_data_T_2[51:0]} << mux_data_rawIn_normDist;
automatic logic [51:0] _mux_data_T_10 =
mux_data_rawIn_isZeroExpIn
? {_mux_data_rawIn_subnormFract_T[50:0], 1'h0}
: _mux_data_T_2[51:0];
automatic logic [2:0] _mux_data_T_4 =
mux_data_rawIn_isZeroExpIn & ~_mux_data_rawIn_out_isNaN_T
? 3'h0
: _mux_data_rawIn_adjustedExp_T_4[11:9];
automatic logic _GEN =
_mux_data_T_4[0] | (&(_mux_data_rawIn_adjustedExp_T_4[11:10]))
& _mux_data_rawIn_out_isNaN_T;
automatic logic mux_data_rawIn_isZeroExpIn_1 = _mux_data_T_2[30:23] == 8'h0;
automatic logic _mux_data_rawIn_out_isNaN_T_2 = |(_mux_data_T_2[22:0]);
automatic logic [4:0] mux_data_rawIn_normDist_1 =
_mux_data_T_2[22]
? 5'h0
: _mux_data_T_2[21]
? 5'h1
: _mux_data_T_2[20]
? 5'h2
: _mux_data_T_2[19]
? 5'h3
: _mux_data_T_2[18]
? 5'h4
: _mux_data_T_2[17]
? 5'h5
: _mux_data_T_2[16]
? 5'h6
: _mux_data_T_2[15]
? 5'h7
: _mux_data_T_2[14]
? 5'h8
: _mux_data_T_2[13]
? 5'h9
: _mux_data_T_2[12]
? 5'hA
: _mux_data_T_2[11]
? 5'hB
: _mux_data_T_2[10]
? 5'hC
: _mux_data_T_2[9]
? 5'hD
: _mux_data_T_2[8]
? 5'hE
: _mux_data_T_2[7]
? 5'hF
: _mux_data_T_2[6]
? 5'h10
: _mux_data_T_2[5]
? 5'h11
: _mux_data_T_2[4]
? 5'h12
: _mux_data_T_2[3]
? 5'h13
: _mux_data_T_2[2]
? 5'h14
: _mux_data_T_2[1]
? 5'h15
: 5'h16;
automatic logic [8:0] _mux_data_rawIn_adjustedExp_T_9 =
(mux_data_rawIn_isZeroExpIn_1
? {4'hF, ~mux_data_rawIn_normDist_1}
: {1'h0, _mux_data_T_2[30:23]})
+ {7'h20, mux_data_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1};
automatic logic [2:0] _mux_data_T_13 =
mux_data_rawIn_isZeroExpIn_1 & ~_mux_data_rawIn_out_isNaN_T_2
? 3'h0
: _mux_data_rawIn_adjustedExp_T_9[8:6];
automatic logic [64:0] i2fResults_1_1 =
({65{_i2fResults_i2f_1_io_out[63:61] != 3'h7}} | 65'h1EFEFFFFFFFFFFFFF)
& _i2fResults_i2f_1_io_out;
automatic logic [53:0] _mux_data_rawIn_subnormFract_T_2 =
{31'h0, _mux_data_T_2[22:0]} << mux_data_rawIn_normDist_1;
io_out_pipe_b_data <=
in_pipe_b_wflags
? (in_pipe_b_typeTagIn[0]
? i2fResults_1_1
: {i2fResults_1_1[64:33], _i2fResults_i2f_io_out})
: {_mux_data_T_2[63],
_mux_data_T_4[2:1],
_GEN,
(&{_mux_data_T_4[2:1], _GEN})
? {&(_mux_data_T_10[51:32]),
_mux_data_rawIn_adjustedExp_T_4[7:1],
_mux_data_T_13[2],
_mux_data_T_10[51:32],
_mux_data_T_2[31],
_mux_data_T_13[1],
_mux_data_T_13[0] | (&(_mux_data_rawIn_adjustedExp_T_9[8:7]))
& _mux_data_rawIn_out_isNaN_T_2,
_mux_data_rawIn_adjustedExp_T_9[5:0],
mux_data_rawIn_isZeroExpIn_1
? {_mux_data_rawIn_subnormFract_T_2[21:0], 1'h0}
: _mux_data_T_2[22:0]}
: {_mux_data_rawIn_adjustedExp_T_4[8:0], _mux_data_T_10}};
io_out_pipe_b_exc <=
in_pipe_b_wflags
? (in_pipe_b_typeTagIn[0]
? _i2fResults_i2f_1_io_exceptionFlags
: _i2fResults_i2f_io_exceptionFlags)
: 5'h0;
end
end // always @(posedge)
INToRecFN i2fResults_i2f (
.io_signedIn (~(in_pipe_b_typ[0])),
.io_in (intValue_res),
.io_roundingMode (in_pipe_b_rm),
.io_out (_i2fResults_i2f_io_out),
.io_exceptionFlags (_i2fResults_i2f_io_exceptionFlags)
);
INToRecFN_1 i2fResults_i2f_1 (
.io_signedIn (~(in_pipe_b_typ[0])),
.io_in (intValue_res),
.io_roundingMode (in_pipe_b_rm),
.io_out (_i2fResults_i2f_1_io_out),
.io_exceptionFlags (_i2fResults_i2f_1_io_exceptionFlags)
);
assign io_out_bits_data = io_out_pipe_b_data;
assign io_out_bits_exc = io_out_pipe_b_exc;
endmodule
hardware/generated/genesys2-soc-verilog/IntXbar_i2_o1.sv
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// Generated by CIRCT firtool-1.151.0
module IntXbar_i2_o1(
input auto_anon_in_1_0,
auto_anon_in_0_0,
auto_anon_in_0_1,
auto_anon_in_0_2,
auto_anon_in_0_3,
auto_anon_in_0_4,
auto_anon_in_0_5,
auto_anon_in_0_6,
auto_anon_in_0_7,
auto_anon_in_0_8,
auto_anon_in_0_9,
output auto_anon_out_0,
auto_anon_out_1,
auto_anon_out_2,
auto_anon_out_3,
auto_anon_out_4,
auto_anon_out_5,
auto_anon_out_6,
auto_anon_out_7,
auto_anon_out_8,
auto_anon_out_9,
auto_anon_out_10
);
assign auto_anon_out_0 = auto_anon_in_0_0;
assign auto_anon_out_1 = auto_anon_in_0_1;
assign auto_anon_out_2 = auto_anon_in_0_2;
assign auto_anon_out_3 = auto_anon_in_0_3;
assign auto_anon_out_4 = auto_anon_in_0_4;
assign auto_anon_out_5 = auto_anon_in_0_5;
assign auto_anon_out_6 = auto_anon_in_0_6;
assign auto_anon_out_7 = auto_anon_in_0_7;
assign auto_anon_out_8 = auto_anon_in_0_8;
assign auto_anon_out_9 = auto_anon_in_0_9;
assign auto_anon_out_10 = auto_anon_in_1_0;
endmodule
hardware/generated/genesys2-soc-verilog/IntXbar_i3_o1.sv
+18
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@@ -0,0 +1,18 @@
// Generated by CIRCT firtool-1.151.0
module IntXbar_i3_o1(
input auto_anon_in_2_0,
auto_anon_in_1_0,
auto_anon_in_1_1,
auto_anon_in_0_0,
output auto_anon_out_0,
auto_anon_out_1,
auto_anon_out_2,
auto_anon_out_3
);
assign auto_anon_out_0 = auto_anon_in_0_0;
assign auto_anon_out_1 = auto_anon_in_1_0;
assign auto_anon_out_2 = auto_anon_in_1_1;
assign auto_anon_out_3 = auto_anon_in_2_0;
endmodule
hardware/generated/genesys2-soc-verilog/LevelGateway.sv
+20
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@@ -0,0 +1,20 @@
// Generated by CIRCT firtool-1.151.0
module LevelGateway(
input clock,
reset,
io_interrupt,
output io_plic_valid,
input io_plic_ready,
io_plic_complete
);
reg inFlight;
always @(posedge clock) begin
if (reset)
inFlight <= 1'h0;
else
inFlight <= ~io_plic_complete & (io_interrupt & io_plic_ready | inFlight);
end // always @(posedge)
assign io_plic_valid = io_interrupt & ~inFlight;
endmodule
hardware/generated/genesys2-soc-verilog/MulAddRecFNPipe_l2_e11_s53.sv
+211
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// Generated by CIRCT firtool-1.151.0
module MulAddRecFNPipe_l2_e11_s53(
input clock,
reset,
io_validin,
input [1:0] io_op,
input [64:0] io_a,
io_b,
io_c,
input [2:0] io_roundingMode,
output [64:0] io_out,
output [4:0] io_exceptionFlags,
output io_validout
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc;
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf;
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero;
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign;
wire [12:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp;
wire [55:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig;
wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddA;
wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddB;
wire [105:0] _mulAddRecFNToRaw_preMul_io_mulAddC;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;
wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;
wire [5:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;
wire [54:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC;
reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant;
reg [5:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist;
reg [54:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC;
reg [106:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b;
reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b;
reg [2:0] roundingMode_stage0_pipe_b;
reg valid_stage0_pipe_v;
reg roundRawFNToRecFN_io_invalidExc_pipe_b;
reg roundRawFNToRecFN_io_in_pipe_b_isNaN;
reg roundRawFNToRecFN_io_in_pipe_b_isInf;
reg roundRawFNToRecFN_io_in_pipe_b_isZero;
reg roundRawFNToRecFN_io_in_pipe_b_sign;
reg [12:0] roundRawFNToRecFN_io_in_pipe_b_sExp;
reg [55:0] roundRawFNToRecFN_io_in_pipe_b_sig;
reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b;
reg io_validout_pipe_v;
always @(posedge clock) begin
if (io_validin) begin
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <=
_mulAddRecFNToRaw_preMul_io_toPostMul_signProd;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <=
_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <=
_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <=
_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <=
_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <=
_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <=
_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <=
{1'h0,
{53'h0, _mulAddRecFNToRaw_preMul_io_mulAddA}
* {53'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}}
+ {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC};
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode;
roundingMode_stage0_pipe_b <= io_roundingMode;
end
if (valid_stage0_pipe_v) begin
roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc;
roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;
roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf;
roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero;
roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign;
roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp;
roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig;
roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0_pipe_b;
end
if (reset) begin
valid_stage0_pipe_v <= 1'h0;
io_validout_pipe_v <= 1'h0;
end
else begin
valid_stage0_pipe_v <= io_validin;
io_validout_pipe_v <= valid_stage0_pipe_v;
end
end // always @(posedge)
MulAddRecFNToRaw_preMul_1 mulAddRecFNToRaw_preMul (
.io_op (io_op),
.io_a (io_a),
.io_b (io_b),
.io_c (io_c),
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
);
MulAddRecFNToRaw_postMul_1 mulAddRecFNToRaw_postMul (
.io_fromPreMul_isSigNaNAny
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny),
.io_fromPreMul_isNaNAOrB
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB),
.io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA),
.io_fromPreMul_isZeroA
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA),
.io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB),
.io_fromPreMul_isZeroB
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB),
.io_fromPreMul_signProd
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd),
.io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC),
.io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC),
.io_fromPreMul_isZeroC
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC),
.io_fromPreMul_sExpSum
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum),
.io_fromPreMul_doSubMags
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags),
.io_fromPreMul_CIsDominant
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant),
.io_fromPreMul_CDom_CAlignDist
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist),
.io_fromPreMul_highAlignedSigC
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC),
.io_fromPreMul_bit0AlignedSigC
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC),
.io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b),
.io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b),
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
);
RoundRawFNToRecFN_1 roundRawFNToRecFN (
.io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_b),
.io_infiniteExc (1'h0),
.io_in_isNaN (roundRawFNToRecFN_io_in_pipe_b_isNaN),
.io_in_isInf (roundRawFNToRecFN_io_in_pipe_b_isInf),
.io_in_isZero (roundRawFNToRecFN_io_in_pipe_b_isZero),
.io_in_sign (roundRawFNToRecFN_io_in_pipe_b_sign),
.io_in_sExp (roundRawFNToRecFN_io_in_pipe_b_sExp),
.io_in_sig (roundRawFNToRecFN_io_in_pipe_b_sig),
.io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_b),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
assign io_validout = io_validout_pipe_v;
endmodule
hardware/generated/genesys2-soc-verilog/MulAddRecFNPipe_l2_e8_s24.sv
+204
View File
@@ -0,0 +1,204 @@
// Generated by CIRCT firtool-1.151.0
module MulAddRecFNPipe_l2_e8_s24(
input clock,
reset,
io_validin,
input [1:0] io_op,
input [32:0] io_a,
io_b,
io_c,
input [2:0] io_roundingMode,
output [32:0] io_out,
output [4:0] io_exceptionFlags
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc;
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf;
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero;
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign;
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp;
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig;
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA;
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB;
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC;
reg [9:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant;
reg [4:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist;
reg [25:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC;
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC;
reg [48:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b;
reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b;
reg [2:0] roundingMode_stage0_pipe_b;
reg valid_stage0_pipe_v;
reg roundRawFNToRecFN_io_invalidExc_pipe_b;
reg roundRawFNToRecFN_io_in_pipe_b_isNaN;
reg roundRawFNToRecFN_io_in_pipe_b_isInf;
reg roundRawFNToRecFN_io_in_pipe_b_isZero;
reg roundRawFNToRecFN_io_in_pipe_b_sign;
reg [9:0] roundRawFNToRecFN_io_in_pipe_b_sExp;
reg [26:0] roundRawFNToRecFN_io_in_pipe_b_sig;
reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b;
always @(posedge clock) begin
if (io_validin) begin
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <=
_mulAddRecFNToRaw_preMul_io_toPostMul_signProd;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <=
_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <=
_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <=
_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <=
_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <=
_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <=
_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <=
_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <=
{1'h0,
{24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA}
* {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}}
+ {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC};
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode;
roundingMode_stage0_pipe_b <= io_roundingMode;
end
if (valid_stage0_pipe_v) begin
roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc;
roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;
roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf;
roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero;
roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign;
roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp;
roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig;
roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0_pipe_b;
end
if (reset)
valid_stage0_pipe_v <= 1'h0;
else
valid_stage0_pipe_v <= io_validin;
end // always @(posedge)
MulAddRecFNToRaw_preMul mulAddRecFNToRaw_preMul (
.io_op (io_op),
.io_a (io_a),
.io_b (io_b),
.io_c (io_c),
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
);
MulAddRecFNToRaw_postMul mulAddRecFNToRaw_postMul (
.io_fromPreMul_isSigNaNAny
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny),
.io_fromPreMul_isNaNAOrB
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB),
.io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA),
.io_fromPreMul_isZeroA
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA),
.io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB),
.io_fromPreMul_isZeroB
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB),
.io_fromPreMul_signProd
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd),
.io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC),
.io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC),
.io_fromPreMul_isZeroC
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC),
.io_fromPreMul_sExpSum
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum),
.io_fromPreMul_doSubMags
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags),
.io_fromPreMul_CIsDominant
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant),
.io_fromPreMul_CDom_CAlignDist
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist),
.io_fromPreMul_highAlignedSigC
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC),
.io_fromPreMul_bit0AlignedSigC
(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC),
.io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b),
.io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b),
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
);
RoundRawFNToRecFN roundRawFNToRecFN (
.io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_b),
.io_infiniteExc (1'h0),
.io_in_isNaN (roundRawFNToRecFN_io_in_pipe_b_isNaN),
.io_in_isInf (roundRawFNToRecFN_io_in_pipe_b_isInf),
.io_in_isZero (roundRawFNToRecFN_io_in_pipe_b_isZero),
.io_in_sign (roundRawFNToRecFN_io_in_pipe_b_sign),
.io_in_sExp (roundRawFNToRecFN_io_in_pipe_b_sExp),
.io_in_sig (roundRawFNToRecFN_io_in_pipe_b_sig),
.io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_b),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
);
endmodule
hardware/generated/genesys2-soc-verilog/MulAddRecFNToRaw_postMul.sv
+183
View File
@@ -0,0 +1,183 @@
// Generated by CIRCT firtool-1.151.0
module MulAddRecFNToRaw_postMul(
input io_fromPreMul_isSigNaNAny,
io_fromPreMul_isNaNAOrB,
io_fromPreMul_isInfA,
io_fromPreMul_isZeroA,
io_fromPreMul_isInfB,
io_fromPreMul_isZeroB,
io_fromPreMul_signProd,
io_fromPreMul_isNaNC,
io_fromPreMul_isInfC,
io_fromPreMul_isZeroC,
input [9:0] io_fromPreMul_sExpSum,
input io_fromPreMul_doSubMags,
io_fromPreMul_CIsDominant,
input [4:0] io_fromPreMul_CDom_CAlignDist,
input [25:0] io_fromPreMul_highAlignedSigC,
input io_fromPreMul_bit0AlignedSigC,
input [48:0] io_mulAddResult,
input [2:0] io_roundingMode,
output io_invalidExc,
io_rawOut_isNaN,
io_rawOut_isInf,
io_rawOut_isZero,
io_rawOut_sign,
output [9:0] io_rawOut_sExp,
output [26:0] io_rawOut_sig
);
wire roundingMode_min = io_roundingMode == 3'h2;
wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags;
wire [25:0] _sigSum_T_3 =
io_mulAddResult[48]
? io_fromPreMul_highAlignedSigC + 26'h1
: io_fromPreMul_highAlignedSigC;
wire [49:0] CDom_absSigSum =
io_fromPreMul_doSubMags
? ~{_sigSum_T_3, io_mulAddResult[47:24]}
: {1'h0,
io_fromPreMul_highAlignedSigC[25:24],
_sigSum_T_3[23:0],
io_mulAddResult[47:25]};
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist;
wire [8:0] CDom_reduced4SigExtra_shift =
$unsigned($signed(9'sh100 >>> ~(io_fromPreMul_CDom_CAlignDist[4:2])));
wire [50:0] notCDom_absSigSum =
_sigSum_T_3[2]
? ~{_sigSum_T_3[1:0], io_mulAddResult[47:0], io_fromPreMul_bit0AlignedSigC}
: {_sigSum_T_3[1:0], io_mulAddResult[47:0], io_fromPreMul_bit0AlignedSigC}
+ {50'h0, io_fromPreMul_doSubMags};
wire notCDom_reduced2AbsSigSum_reducedVec_1 = |(notCDom_absSigSum[3:2]);
wire notCDom_reduced2AbsSigSum_reducedVec_2 = |(notCDom_absSigSum[5:4]);
wire notCDom_reduced2AbsSigSum_reducedVec_3 = |(notCDom_absSigSum[7:6]);
wire notCDom_reduced2AbsSigSum_reducedVec_4 = |(notCDom_absSigSum[9:8]);
wire notCDom_reduced2AbsSigSum_reducedVec_5 = |(notCDom_absSigSum[11:10]);
wire notCDom_reduced2AbsSigSum_reducedVec_6 = |(notCDom_absSigSum[13:12]);
wire notCDom_reduced2AbsSigSum_reducedVec_7 = |(notCDom_absSigSum[15:14]);
wire notCDom_reduced2AbsSigSum_reducedVec_8 = |(notCDom_absSigSum[17:16]);
wire notCDom_reduced2AbsSigSum_reducedVec_9 = |(notCDom_absSigSum[19:18]);
wire notCDom_reduced2AbsSigSum_reducedVec_10 = |(notCDom_absSigSum[21:20]);
wire notCDom_reduced2AbsSigSum_reducedVec_11 = |(notCDom_absSigSum[23:22]);
wire [4:0] notCDom_normDistReduced2 =
notCDom_absSigSum[50]
? 5'h0
: (|(notCDom_absSigSum[49:48]))
? 5'h1
: (|(notCDom_absSigSum[47:46]))
? 5'h2
: (|(notCDom_absSigSum[45:44]))
? 5'h3
: (|(notCDom_absSigSum[43:42]))
? 5'h4
: (|(notCDom_absSigSum[41:40]))
? 5'h5
: (|(notCDom_absSigSum[39:38]))
? 5'h6
: (|(notCDom_absSigSum[37:36]))
? 5'h7
: (|(notCDom_absSigSum[35:34]))
? 5'h8
: (|(notCDom_absSigSum[33:32]))
? 5'h9
: (|(notCDom_absSigSum[31:30]))
? 5'hA
: (|(notCDom_absSigSum[29:28]))
? 5'hB
: (|(notCDom_absSigSum[27:26]))
? 5'hC
: (|(notCDom_absSigSum[25:24]))
? 5'hD
: notCDom_reduced2AbsSigSum_reducedVec_11
? 5'hE
: notCDom_reduced2AbsSigSum_reducedVec_10
? 5'hF
: notCDom_reduced2AbsSigSum_reducedVec_9
? 5'h10
: notCDom_reduced2AbsSigSum_reducedVec_8
? 5'h11
: notCDom_reduced2AbsSigSum_reducedVec_7
? 5'h12
: notCDom_reduced2AbsSigSum_reducedVec_6
? 5'h13
: notCDom_reduced2AbsSigSum_reducedVec_5
? 5'h14
: notCDom_reduced2AbsSigSum_reducedVec_4
? 5'h15
: notCDom_reduced2AbsSigSum_reducedVec_3
? 5'h16
: notCDom_reduced2AbsSigSum_reducedVec_2
? 5'h17
: {4'hC,
~notCDom_reduced2AbsSigSum_reducedVec_1};
wire [113:0] _notCDom_mainSig_T =
{63'h0, notCDom_absSigSum} << {108'h0, notCDom_normDistReduced2, 1'h0};
wire [16:0] notCDom_reduced4SigExtra_shift =
$unsigned($signed(17'sh10000 >>> ~(notCDom_normDistReduced2[4:1])));
wire notCDom_completeCancellation = _notCDom_mainSig_T[51:50] == 2'h0;
wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB;
wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC;
wire notNaN_addZeros =
(io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC;
assign io_invalidExc =
io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB
| io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB
& notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags;
assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC;
assign io_rawOut_isInf = notNaN_isInfOut;
assign io_rawOut_isZero =
notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation;
assign io_rawOut_sign =
notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC
| notNaN_addZeros & io_roundingMode != 3'h2 & io_fromPreMul_signProd & opSignC
| notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC)
| ~notNaN_isInfOut & ~notNaN_addZeros
& (io_fromPreMul_CIsDominant
? opSignC
: notCDom_completeCancellation
? roundingMode_min
: io_fromPreMul_signProd ^ _sigSum_T_3[2]);
assign io_rawOut_sExp =
io_fromPreMul_CIsDominant
? io_fromPreMul_sExpSum - {9'h0, io_fromPreMul_doSubMags}
: io_fromPreMul_sExpSum - {4'h0, notCDom_normDistReduced2, 1'h0};
assign io_rawOut_sig =
io_fromPreMul_CIsDominant
? {_CDom_mainSig_T[49:24],
(|{_CDom_mainSig_T[23:21],
{|(CDom_absSigSum[20:17]),
|(CDom_absSigSum[16:13]),
|(CDom_absSigSum[12:9]),
|(CDom_absSigSum[8:5]),
|(CDom_absSigSum[4:1]),
CDom_absSigSum[0]}
& {CDom_reduced4SigExtra_shift[1],
CDom_reduced4SigExtra_shift[2],
CDom_reduced4SigExtra_shift[3],
CDom_reduced4SigExtra_shift[4],
CDom_reduced4SigExtra_shift[5],
CDom_reduced4SigExtra_shift[6]}})
| (io_fromPreMul_doSubMags
? io_mulAddResult[23:0] != 24'hFFFFFF
: (|(io_mulAddResult[24:0])))}
: {_notCDom_mainSig_T[51:26],
|{_notCDom_mainSig_T[25:23],
{|{notCDom_reduced2AbsSigSum_reducedVec_11,
notCDom_reduced2AbsSigSum_reducedVec_10},
|{notCDom_reduced2AbsSigSum_reducedVec_9,
notCDom_reduced2AbsSigSum_reducedVec_8},
|{notCDom_reduced2AbsSigSum_reducedVec_7,
notCDom_reduced2AbsSigSum_reducedVec_6},
|{notCDom_reduced2AbsSigSum_reducedVec_5,
notCDom_reduced2AbsSigSum_reducedVec_4},
|{notCDom_reduced2AbsSigSum_reducedVec_3,
notCDom_reduced2AbsSigSum_reducedVec_2},
|{notCDom_reduced2AbsSigSum_reducedVec_1, |(notCDom_absSigSum[1:0])}}
& {notCDom_reduced4SigExtra_shift[1],
notCDom_reduced4SigExtra_shift[2],
notCDom_reduced4SigExtra_shift[3],
notCDom_reduced4SigExtra_shift[4],
notCDom_reduced4SigExtra_shift[5],
notCDom_reduced4SigExtra_shift[6]}}};
endmodule
hardware/generated/genesys2-soc-verilog/MulAddRecFNToRaw_postMul_1.sv
+290
View File
@@ -0,0 +1,290 @@
// Generated by CIRCT firtool-1.151.0
module MulAddRecFNToRaw_postMul_1(
input io_fromPreMul_isSigNaNAny,
io_fromPreMul_isNaNAOrB,
io_fromPreMul_isInfA,
io_fromPreMul_isZeroA,
io_fromPreMul_isInfB,
io_fromPreMul_isZeroB,
io_fromPreMul_signProd,
io_fromPreMul_isNaNC,
io_fromPreMul_isInfC,
io_fromPreMul_isZeroC,
input [12:0] io_fromPreMul_sExpSum,
input io_fromPreMul_doSubMags,
io_fromPreMul_CIsDominant,
input [5:0] io_fromPreMul_CDom_CAlignDist,
input [54:0] io_fromPreMul_highAlignedSigC,
input io_fromPreMul_bit0AlignedSigC,
input [106:0] io_mulAddResult,
input [2:0] io_roundingMode,
output io_invalidExc,
io_rawOut_isNaN,
io_rawOut_isInf,
io_rawOut_isZero,
io_rawOut_sign,
output [12:0] io_rawOut_sExp,
output [55:0] io_rawOut_sig
);
wire roundingMode_min = io_roundingMode == 3'h2;
wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags;
wire [54:0] _sigSum_T_3 =
io_mulAddResult[106]
? io_fromPreMul_highAlignedSigC + 55'h1
: io_fromPreMul_highAlignedSigC;
wire [107:0] CDom_absSigSum =
io_fromPreMul_doSubMags
? ~{_sigSum_T_3, io_mulAddResult[105:53]}
: {1'h0,
io_fromPreMul_highAlignedSigC[54:53],
_sigSum_T_3[52:0],
io_mulAddResult[105:54]};
wire [170:0] _CDom_mainSig_T = {63'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist;
wire [16:0] CDom_reduced4SigExtra_shift =
$unsigned($signed(17'sh10000 >>> ~(io_fromPreMul_CDom_CAlignDist[5:2])));
wire [7:0] _CDom_reduced4SigExtra_T_15 =
{4'h0, CDom_reduced4SigExtra_shift[8:5]} | {CDom_reduced4SigExtra_shift[4:1], 4'h0};
wire [7:0] _CDom_reduced4SigExtra_T_25 =
{2'h0, _CDom_reduced4SigExtra_T_15[7:2] & 6'h33}
| {_CDom_reduced4SigExtra_T_15[5:0] & 6'h33, 2'h0};
wire [108:0] notCDom_absSigSum =
_sigSum_T_3[2]
? ~{_sigSum_T_3[1:0], io_mulAddResult[105:0], io_fromPreMul_bit0AlignedSigC}
: {_sigSum_T_3[1:0], io_mulAddResult[105:0], io_fromPreMul_bit0AlignedSigC}
+ {108'h0, io_fromPreMul_doSubMags};
wire notCDom_reduced2AbsSigSum_reducedVec_1 = |(notCDom_absSigSum[3:2]);
wire notCDom_reduced2AbsSigSum_reducedVec_2 = |(notCDom_absSigSum[5:4]);
wire notCDom_reduced2AbsSigSum_reducedVec_3 = |(notCDom_absSigSum[7:6]);
wire notCDom_reduced2AbsSigSum_reducedVec_4 = |(notCDom_absSigSum[9:8]);
wire notCDom_reduced2AbsSigSum_reducedVec_5 = |(notCDom_absSigSum[11:10]);
wire notCDom_reduced2AbsSigSum_reducedVec_6 = |(notCDom_absSigSum[13:12]);
wire notCDom_reduced2AbsSigSum_reducedVec_7 = |(notCDom_absSigSum[15:14]);
wire notCDom_reduced2AbsSigSum_reducedVec_8 = |(notCDom_absSigSum[17:16]);
wire notCDom_reduced2AbsSigSum_reducedVec_9 = |(notCDom_absSigSum[19:18]);
wire notCDom_reduced2AbsSigSum_reducedVec_10 = |(notCDom_absSigSum[21:20]);
wire notCDom_reduced2AbsSigSum_reducedVec_11 = |(notCDom_absSigSum[23:22]);
wire notCDom_reduced2AbsSigSum_reducedVec_12 = |(notCDom_absSigSum[25:24]);
wire notCDom_reduced2AbsSigSum_reducedVec_13 = |(notCDom_absSigSum[27:26]);
wire notCDom_reduced2AbsSigSum_reducedVec_14 = |(notCDom_absSigSum[29:28]);
wire notCDom_reduced2AbsSigSum_reducedVec_15 = |(notCDom_absSigSum[31:30]);
wire notCDom_reduced2AbsSigSum_reducedVec_16 = |(notCDom_absSigSum[33:32]);
wire notCDom_reduced2AbsSigSum_reducedVec_17 = |(notCDom_absSigSum[35:34]);
wire notCDom_reduced2AbsSigSum_reducedVec_18 = |(notCDom_absSigSum[37:36]);
wire notCDom_reduced2AbsSigSum_reducedVec_19 = |(notCDom_absSigSum[39:38]);
wire notCDom_reduced2AbsSigSum_reducedVec_20 = |(notCDom_absSigSum[41:40]);
wire notCDom_reduced2AbsSigSum_reducedVec_21 = |(notCDom_absSigSum[43:42]);
wire notCDom_reduced2AbsSigSum_reducedVec_22 = |(notCDom_absSigSum[45:44]);
wire notCDom_reduced2AbsSigSum_reducedVec_23 = |(notCDom_absSigSum[47:46]);
wire notCDom_reduced2AbsSigSum_reducedVec_24 = |(notCDom_absSigSum[49:48]);
wire notCDom_reduced2AbsSigSum_reducedVec_25 = |(notCDom_absSigSum[51:50]);
wire [5:0] notCDom_normDistReduced2 =
notCDom_absSigSum[108]
? 6'h0
: (|(notCDom_absSigSum[107:106]))
? 6'h1
: (|(notCDom_absSigSum[105:104]))
? 6'h2
: (|(notCDom_absSigSum[103:102]))
? 6'h3
: (|(notCDom_absSigSum[101:100]))
? 6'h4
: (|(notCDom_absSigSum[99:98]))
? 6'h5
: (|(notCDom_absSigSum[97:96]))
? 6'h6
: (|(notCDom_absSigSum[95:94]))
? 6'h7
: (|(notCDom_absSigSum[93:92]))
? 6'h8
: (|(notCDom_absSigSum[91:90]))
? 6'h9
: (|(notCDom_absSigSum[89:88]))
? 6'hA
: (|(notCDom_absSigSum[87:86]))
? 6'hB
: (|(notCDom_absSigSum[85:84]))
? 6'hC
: (|(notCDom_absSigSum[83:82]))
? 6'hD
: (|(notCDom_absSigSum[81:80]))
? 6'hE
: (|(notCDom_absSigSum[79:78]))
? 6'hF
: (|(notCDom_absSigSum[77:76]))
? 6'h10
: (|(notCDom_absSigSum[75:74]))
? 6'h11
: (|(notCDom_absSigSum[73:72]))
? 6'h12
: (|(notCDom_absSigSum[71:70]))
? 6'h13
: (|(notCDom_absSigSum[69:68]))
? 6'h14
: (|(notCDom_absSigSum[67:66]))
? 6'h15
: (|(notCDom_absSigSum[65:64]))
? 6'h16
: (|(notCDom_absSigSum[63:62]))
? 6'h17
: (|(notCDom_absSigSum[61:60]))
? 6'h18
: (|(notCDom_absSigSum[59:58]))
? 6'h19
: (|(notCDom_absSigSum[57:56]))
? 6'h1A
: (|(notCDom_absSigSum[55:54]))
? 6'h1B
: (|(notCDom_absSigSum[53:52]))
? 6'h1C
: notCDom_reduced2AbsSigSum_reducedVec_25
? 6'h1D
: notCDom_reduced2AbsSigSum_reducedVec_24
? 6'h1E
: notCDom_reduced2AbsSigSum_reducedVec_23
? 6'h1F
: notCDom_reduced2AbsSigSum_reducedVec_22
? 6'h20
: notCDom_reduced2AbsSigSum_reducedVec_21
? 6'h21
: notCDom_reduced2AbsSigSum_reducedVec_20
? 6'h22
: notCDom_reduced2AbsSigSum_reducedVec_19
? 6'h23
: notCDom_reduced2AbsSigSum_reducedVec_18
? 6'h24
: notCDom_reduced2AbsSigSum_reducedVec_17
? 6'h25
: notCDom_reduced2AbsSigSum_reducedVec_16
? 6'h26
: notCDom_reduced2AbsSigSum_reducedVec_15
? 6'h27
: notCDom_reduced2AbsSigSum_reducedVec_14
? 6'h28
: notCDom_reduced2AbsSigSum_reducedVec_13
? 6'h29
: notCDom_reduced2AbsSigSum_reducedVec_12
? 6'h2A
: notCDom_reduced2AbsSigSum_reducedVec_11
? 6'h2B
: notCDom_reduced2AbsSigSum_reducedVec_10
? 6'h2C
: notCDom_reduced2AbsSigSum_reducedVec_9
? 6'h2D
: notCDom_reduced2AbsSigSum_reducedVec_8
? 6'h2E
: notCDom_reduced2AbsSigSum_reducedVec_7
? 6'h2F
: notCDom_reduced2AbsSigSum_reducedVec_6
? 6'h30
: notCDom_reduced2AbsSigSum_reducedVec_5
? 6'h31
: notCDom_reduced2AbsSigSum_reducedVec_4
? 6'h32
: notCDom_reduced2AbsSigSum_reducedVec_3
? 6'h33
: notCDom_reduced2AbsSigSum_reducedVec_2
? 6'h34
: notCDom_reduced2AbsSigSum_reducedVec_1
? 6'h35
: 6'h36;
wire [235:0] _notCDom_mainSig_T =
{127'h0, notCDom_absSigSum} << {229'h0, notCDom_normDistReduced2, 1'h0};
wire [32:0] notCDom_reduced4SigExtra_shift =
$unsigned($signed(33'sh100000000 >>> ~(notCDom_normDistReduced2[5:1])));
wire [7:0] _notCDom_reduced4SigExtra_T_15 =
{4'h0, notCDom_reduced4SigExtra_shift[8:5]}
| {notCDom_reduced4SigExtra_shift[4:1], 4'h0};
wire [7:0] _notCDom_reduced4SigExtra_T_25 =
{2'h0, _notCDom_reduced4SigExtra_T_15[7:2] & 6'h33}
| {_notCDom_reduced4SigExtra_T_15[5:0] & 6'h33, 2'h0};
wire notCDom_completeCancellation = _notCDom_mainSig_T[109:108] == 2'h0;
wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB;
wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC;
wire notNaN_addZeros =
(io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC;
assign io_invalidExc =
io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB
| io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB
& notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags;
assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC;
assign io_rawOut_isInf = notNaN_isInfOut;
assign io_rawOut_isZero =
notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation;
assign io_rawOut_sign =
notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC
| notNaN_addZeros & io_roundingMode != 3'h2 & io_fromPreMul_signProd & opSignC
| notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC)
| ~notNaN_isInfOut & ~notNaN_addZeros
& (io_fromPreMul_CIsDominant
? opSignC
: notCDom_completeCancellation
? roundingMode_min
: io_fromPreMul_signProd ^ _sigSum_T_3[2]);
assign io_rawOut_sExp =
io_fromPreMul_CIsDominant
? io_fromPreMul_sExpSum - {12'h0, io_fromPreMul_doSubMags}
: io_fromPreMul_sExpSum - {6'h0, notCDom_normDistReduced2, 1'h0};
assign io_rawOut_sig =
io_fromPreMul_CIsDominant
? {_CDom_mainSig_T[107:53],
(|{_CDom_mainSig_T[52:50],
{|(CDom_absSigSum[49:46]),
|(CDom_absSigSum[45:42]),
|(CDom_absSigSum[41:38]),
|(CDom_absSigSum[37:34]),
|(CDom_absSigSum[33:30]),
|(CDom_absSigSum[29:26]),
|(CDom_absSigSum[25:22]),
|(CDom_absSigSum[21:18]),
|(CDom_absSigSum[17:14]),
|(CDom_absSigSum[13:10]),
|(CDom_absSigSum[9:6]),
|(CDom_absSigSum[5:2]),
|(CDom_absSigSum[1:0])}
& {{1'h0, _CDom_reduced4SigExtra_T_25[7:1] & 7'h55}
| {_CDom_reduced4SigExtra_T_25[6:0] & 7'h55, 1'h0},
CDom_reduced4SigExtra_shift[9],
CDom_reduced4SigExtra_shift[10],
CDom_reduced4SigExtra_shift[11],
CDom_reduced4SigExtra_shift[12],
CDom_reduced4SigExtra_shift[13]}})
| (io_fromPreMul_doSubMags
? io_mulAddResult[52:0] != 53'h1FFFFFFFFFFFFF
: (|(io_mulAddResult[53:0])))}
: {_notCDom_mainSig_T[109:55],
|{_notCDom_mainSig_T[54:52],
{|{notCDom_reduced2AbsSigSum_reducedVec_25,
notCDom_reduced2AbsSigSum_reducedVec_24},
|{notCDom_reduced2AbsSigSum_reducedVec_23,
notCDom_reduced2AbsSigSum_reducedVec_22},
|{notCDom_reduced2AbsSigSum_reducedVec_21,
notCDom_reduced2AbsSigSum_reducedVec_20},
|{notCDom_reduced2AbsSigSum_reducedVec_19,
notCDom_reduced2AbsSigSum_reducedVec_18},
|{notCDom_reduced2AbsSigSum_reducedVec_17,
notCDom_reduced2AbsSigSum_reducedVec_16},
|{notCDom_reduced2AbsSigSum_reducedVec_15,
notCDom_reduced2AbsSigSum_reducedVec_14},
|{notCDom_reduced2AbsSigSum_reducedVec_13,
notCDom_reduced2AbsSigSum_reducedVec_12},
|{notCDom_reduced2AbsSigSum_reducedVec_11,
notCDom_reduced2AbsSigSum_reducedVec_10},
|{notCDom_reduced2AbsSigSum_reducedVec_9,
notCDom_reduced2AbsSigSum_reducedVec_8},
|{notCDom_reduced2AbsSigSum_reducedVec_7,
notCDom_reduced2AbsSigSum_reducedVec_6},
|{notCDom_reduced2AbsSigSum_reducedVec_5,
notCDom_reduced2AbsSigSum_reducedVec_4},
|{notCDom_reduced2AbsSigSum_reducedVec_3,
notCDom_reduced2AbsSigSum_reducedVec_2},
|{notCDom_reduced2AbsSigSum_reducedVec_1, |(notCDom_absSigSum[1:0])}}
& {{1'h0, _notCDom_reduced4SigExtra_T_25[7:1] & 7'h55}
| {_notCDom_reduced4SigExtra_T_25[6:0] & 7'h55, 1'h0},
notCDom_reduced4SigExtra_shift[9],
notCDom_reduced4SigExtra_shift[10],
notCDom_reduced4SigExtra_shift[11],
notCDom_reduced4SigExtra_shift[12],
notCDom_reduced4SigExtra_shift[13]}}};
endmodule
hardware/generated/genesys2-soc-verilog/MulAddRecFNToRaw_preMul.sv
+92
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@@ -0,0 +1,92 @@
// Generated by CIRCT firtool-1.151.0
module MulAddRecFNToRaw_preMul(
input [1:0] io_op,
input [32:0] io_a,
io_b,
io_c,
output [23:0] io_mulAddA,
io_mulAddB,
output [47:0] io_mulAddC,
output io_toPostMul_isSigNaNAny,
io_toPostMul_isNaNAOrB,
io_toPostMul_isInfA,
io_toPostMul_isZeroA,
io_toPostMul_isInfB,
io_toPostMul_isZeroB,
io_toPostMul_signProd,
io_toPostMul_isNaNC,
io_toPostMul_isInfC,
io_toPostMul_isZeroC,
output [9:0] io_toPostMul_sExpSum,
output io_toPostMul_doSubMags,
io_toPostMul_CIsDominant,
output [4:0] io_toPostMul_CDom_CAlignDist,
output [25:0] io_toPostMul_highAlignedSigC,
output io_toPostMul_bit0AlignedSigC
);
wire _rawA_out_sig_T = |(io_a[31:29]);
wire rawA_isSpecial = &(io_a[31:30]);
wire rawA_isNaN = rawA_isSpecial & io_a[29];
wire _rawB_out_sig_T = |(io_b[31:29]);
wire rawB_isSpecial = &(io_b[31:30]);
wire rawB_isNaN = rawB_isSpecial & io_b[29];
wire _rawC_out_sig_T = |(io_c[31:29]);
wire rawC_isSpecial = &(io_c[31:30]);
wire rawC_isNaN = rawC_isSpecial & io_c[29];
wire signProd = io_a[32] ^ io_b[32] ^ io_op[1];
wire [10:0] _sExpAlignedProd_T_1 = {2'h0, io_a[31:23]} + {2'h0, io_b[31:23]} - 11'hE5;
wire doSubMags = signProd ^ io_c[32] ^ io_op[0];
wire [10:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[31:23]};
wire isMinCAlign =
~_rawA_out_sig_T | ~_rawB_out_sig_T | $signed(_sNatCAlignDist_T) < 11'sh0;
wire CIsDominant =
_rawC_out_sig_T & (isMinCAlign | _sNatCAlignDist_T[9:0] < 10'h19);
wire [6:0] CAlignDist =
isMinCAlign ? 7'h0 : _sNatCAlignDist_T[9:0] < 10'h4A ? _sNatCAlignDist_T[6:0] : 7'h4A;
wire [77:0] mainAlignedSigC =
$unsigned($signed($signed({doSubMags
? {1'h1, ~_rawC_out_sig_T, ~(io_c[22:0])}
: {1'h0, _rawC_out_sig_T, io_c[22:0]},
{53{doSubMags}}}) >>> CAlignDist));
wire [32:0] reduced4CExtra_shift =
$unsigned($signed(33'sh100000000 >>> CAlignDist[6:2]));
wire [5:0] _GEN =
{|(io_c[21:18]),
|(io_c[17:14]),
|(io_c[13:10]),
|(io_c[9:6]),
|(io_c[5:2]),
|(io_c[1:0])}
& {reduced4CExtra_shift[14],
reduced4CExtra_shift[15],
reduced4CExtra_shift[16],
reduced4CExtra_shift[17],
reduced4CExtra_shift[18],
reduced4CExtra_shift[19]};
assign io_mulAddA = {_rawA_out_sig_T, io_a[22:0]};
assign io_mulAddB = {_rawB_out_sig_T, io_b[22:0]};
assign io_mulAddC = mainAlignedSigC[50:3];
assign io_toPostMul_isSigNaNAny =
rawA_isNaN & ~(io_a[22]) | rawB_isNaN & ~(io_b[22]) | rawC_isNaN & ~(io_c[22]);
assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN;
assign io_toPostMul_isInfA = rawA_isSpecial & ~(io_a[29]);
assign io_toPostMul_isZeroA = ~_rawA_out_sig_T;
assign io_toPostMul_isInfB = rawB_isSpecial & ~(io_b[29]);
assign io_toPostMul_isZeroB = ~_rawB_out_sig_T;
assign io_toPostMul_signProd = signProd;
assign io_toPostMul_isNaNC = rawC_isNaN;
assign io_toPostMul_isInfC = rawC_isSpecial & ~(io_c[29]);
assign io_toPostMul_isZeroC = ~_rawC_out_sig_T;
assign io_toPostMul_sExpSum =
CIsDominant ? {1'h0, io_c[31:23]} : _sExpAlignedProd_T_1[9:0] - 10'h18;
assign io_toPostMul_doSubMags = doSubMags;
assign io_toPostMul_CIsDominant = CIsDominant;
assign io_toPostMul_CDom_CAlignDist = CAlignDist[4:0];
assign io_toPostMul_highAlignedSigC = mainAlignedSigC[76:51];
assign io_toPostMul_bit0AlignedSigC =
doSubMags
? (&(mainAlignedSigC[2:0])) & _GEN == 6'h0
: (|{mainAlignedSigC[2:0], _GEN});
endmodule
hardware/generated/genesys2-soc-verilog/MulAddRecFNToRaw_preMul_1.sv
+106
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@@ -0,0 +1,106 @@
// Generated by CIRCT firtool-1.151.0
module MulAddRecFNToRaw_preMul_1(
input [1:0] io_op,
input [64:0] io_a,
io_b,
io_c,
output [52:0] io_mulAddA,
io_mulAddB,
output [105:0] io_mulAddC,
output io_toPostMul_isSigNaNAny,
io_toPostMul_isNaNAOrB,
io_toPostMul_isInfA,
io_toPostMul_isZeroA,
io_toPostMul_isInfB,
io_toPostMul_isZeroB,
io_toPostMul_signProd,
io_toPostMul_isNaNC,
io_toPostMul_isInfC,
io_toPostMul_isZeroC,
output [12:0] io_toPostMul_sExpSum,
output io_toPostMul_doSubMags,
io_toPostMul_CIsDominant,
output [5:0] io_toPostMul_CDom_CAlignDist,
output [54:0] io_toPostMul_highAlignedSigC,
output io_toPostMul_bit0AlignedSigC
);
wire _rawA_out_sig_T = |(io_a[63:61]);
wire rawA_isSpecial = &(io_a[63:62]);
wire rawA_isNaN = rawA_isSpecial & io_a[61];
wire _rawB_out_sig_T = |(io_b[63:61]);
wire rawB_isSpecial = &(io_b[63:62]);
wire rawB_isNaN = rawB_isSpecial & io_b[61];
wire _rawC_out_sig_T = |(io_c[63:61]);
wire rawC_isSpecial = &(io_c[63:62]);
wire rawC_isNaN = rawC_isSpecial & io_c[61];
wire signProd = io_a[64] ^ io_b[64] ^ io_op[1];
wire [13:0] _sExpAlignedProd_T_1 = {2'h0, io_a[63:52]} + {2'h0, io_b[63:52]} - 14'h7C8;
wire doSubMags = signProd ^ io_c[64] ^ io_op[0];
wire [13:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[63:52]};
wire isMinCAlign =
~_rawA_out_sig_T | ~_rawB_out_sig_T | $signed(_sNatCAlignDist_T) < 14'sh0;
wire CIsDominant =
_rawC_out_sig_T & (isMinCAlign | _sNatCAlignDist_T[12:0] < 13'h36);
wire [7:0] CAlignDist =
isMinCAlign
? 8'h0
: _sNatCAlignDist_T[12:0] < 13'hA1 ? _sNatCAlignDist_T[7:0] : 8'hA1;
wire [164:0] mainAlignedSigC =
$unsigned($signed($signed({doSubMags
? {1'h1, ~_rawC_out_sig_T, ~(io_c[51:0])}
: {1'h0, _rawC_out_sig_T, io_c[51:0]},
{111{doSubMags}}}) >>> CAlignDist));
wire [64:0] reduced4CExtra_shift =
$unsigned($signed(65'sh10000000000000000 >>> CAlignDist[7:2]));
wire [7:0] _reduced4CExtra_T_13 =
{4'h0, reduced4CExtra_shift[31:28]} | {reduced4CExtra_shift[27:24], 4'h0};
wire [7:0] _reduced4CExtra_T_23 =
{2'h0, _reduced4CExtra_T_13[7:2] & 6'h33} | {_reduced4CExtra_T_13[5:0] & 6'h33, 2'h0};
wire [12:0] _GEN =
{|(io_c[51:48]),
|(io_c[47:44]),
|(io_c[43:40]),
|(io_c[39:36]),
|(io_c[35:32]),
|(io_c[31:28]),
|(io_c[27:24]),
|(io_c[23:20]),
|(io_c[19:16]),
|(io_c[15:12]),
|(io_c[11:8]),
|(io_c[7:4]),
|(io_c[3:0])}
& {{1'h0, _reduced4CExtra_T_23[7:1] & 7'h55}
| {_reduced4CExtra_T_23[6:0] & 7'h55, 1'h0},
reduced4CExtra_shift[32],
reduced4CExtra_shift[33],
reduced4CExtra_shift[34],
reduced4CExtra_shift[35],
reduced4CExtra_shift[36]};
assign io_mulAddA = {_rawA_out_sig_T, io_a[51:0]};
assign io_mulAddB = {_rawB_out_sig_T, io_b[51:0]};
assign io_mulAddC = mainAlignedSigC[108:3];
assign io_toPostMul_isSigNaNAny =
rawA_isNaN & ~(io_a[51]) | rawB_isNaN & ~(io_b[51]) | rawC_isNaN & ~(io_c[51]);
assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN;
assign io_toPostMul_isInfA = rawA_isSpecial & ~(io_a[61]);
assign io_toPostMul_isZeroA = ~_rawA_out_sig_T;
assign io_toPostMul_isInfB = rawB_isSpecial & ~(io_b[61]);
assign io_toPostMul_isZeroB = ~_rawB_out_sig_T;
assign io_toPostMul_signProd = signProd;
assign io_toPostMul_isNaNC = rawC_isNaN;
assign io_toPostMul_isInfC = rawC_isSpecial & ~(io_c[61]);
assign io_toPostMul_isZeroC = ~_rawC_out_sig_T;
assign io_toPostMul_sExpSum =
CIsDominant ? {1'h0, io_c[63:52]} : _sExpAlignedProd_T_1[12:0] - 13'h35;
assign io_toPostMul_doSubMags = doSubMags;
assign io_toPostMul_CIsDominant = CIsDominant;
assign io_toPostMul_CDom_CAlignDist = CAlignDist[5:0];
assign io_toPostMul_highAlignedSigC = mainAlignedSigC[163:109];
assign io_toPostMul_bit0AlignedSigC =
doSubMags
? (&(mainAlignedSigC[2:0])) & _GEN == 13'h0
: (|{mainAlignedSigC[2:0], _GEN});
endmodule
hardware/generated/genesys2-soc-verilog/MulDiv.sv
+123
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@@ -0,0 +1,123 @@
// Generated by CIRCT firtool-1.151.0
module MulDiv(
input clock,
reset,
output io_req_ready,
input io_req_valid,
input [4:0] io_req_bits_fn,
input io_req_bits_dw,
input [63:0] io_req_bits_in1,
io_req_bits_in2,
input [4:0] io_req_bits_tag,
input io_kill,
io_resp_ready,
output io_resp_valid,
output [63:0] io_resp_bits_data,
output [4:0] io_resp_bits_tag
);
reg [2:0] state;
reg req_dw;
reg [4:0] req_tag;
reg [6:0] count;
reg neg_out;
reg isHi;
reg resHi;
reg [64:0] divisor;
reg [129:0] remainder;
wire [63:0] result = resHi ? remainder[128:65] : remainder[63:0];
wire [31:0] loOut = req_dw | state[0] ? result[31:0] : result[63:32];
wire io_resp_valid_0 = state == 3'h6 | (&state);
wire io_req_ready_0 = state == 3'h0;
always @(posedge clock) begin
automatic logic [2:0] decoded_invInputs = ~(io_req_bits_fn[2:0]);
automatic logic decoded_andMatrixOutputs_2_2 =
&{decoded_invInputs[1], decoded_invInputs[2]};
automatic logic cmdHi;
automatic logic lhs_sign;
automatic logic rhs_sign;
automatic logic [64:0] _subtractor_T_1;
automatic logic _GEN;
automatic logic _GEN_0;
automatic logic _GEN_1;
automatic logic _GEN_2;
automatic logic _GEN_3;
automatic logic _GEN_4;
automatic logic _GEN_5;
cmdHi = |{&{io_req_bits_fn[0], decoded_invInputs[2]}, io_req_bits_fn[1]};
lhs_sign =
(|{decoded_invInputs[0], decoded_andMatrixOutputs_2_2})
& (io_req_bits_dw ? io_req_bits_in1[63] : io_req_bits_in1[31]);
rhs_sign =
(|{decoded_andMatrixOutputs_2_2, &{decoded_invInputs[0], io_req_bits_fn[2]}})
& (io_req_bits_dw ? io_req_bits_in2[63] : io_req_bits_in2[31]);
_subtractor_T_1 = remainder[128:64] - divisor;
_GEN = state == 3'h1;
_GEN_0 = state == 3'h5;
_GEN_1 = state == 3'h2;
_GEN_2 = _GEN_1 & count == 7'h3F;
_GEN_3 = state == 3'h3;
_GEN_4 = count == 7'h40;
_GEN_5 = io_req_ready_0 & io_req_valid;
if (reset)
state <= 3'h0;
else if (_GEN_5)
state <= decoded_invInputs[2] ? 3'h2 : {1'h0, ~(lhs_sign | rhs_sign), 1'h1};
else if (io_resp_ready & io_resp_valid_0 | io_kill)
state <= 3'h0;
else if (_GEN_3 & _GEN_4)
state <= {1'h1, ~neg_out, 1'h1};
else if (_GEN_2)
state <= 3'h6;
else if (_GEN_0)
state <= 3'h7;
else if (_GEN)
state <= 3'h3;
if (_GEN_5) begin
req_dw <= io_req_bits_dw;
req_tag <= io_req_bits_tag;
count <= {1'h0, decoded_invInputs[2] & ~io_req_bits_dw, 5'h0};
isHi <= cmdHi;
divisor <=
{rhs_sign,
io_req_bits_dw ? io_req_bits_in2[63:32] : {32{rhs_sign}},
io_req_bits_in2[31:0]};
remainder <=
{66'h0,
io_req_bits_dw ? io_req_bits_in1[63:32] : {32{lhs_sign}},
io_req_bits_in1[31:0]};
end
else begin
if (_GEN_3) begin
count <= count + 7'h1;
remainder <=
{1'h0,
_subtractor_T_1[64] ? remainder[127:64] : _subtractor_T_1[63:0],
remainder[63:0],
~(_subtractor_T_1[64])};
end
else if (_GEN_1) begin
automatic logic [65:0] _prod_T_4 =
{{65{remainder[64]}}, remainder[0]} * {divisor[64], divisor}
+ {remainder[129], remainder[129:65]};
count <= count + 7'h1;
remainder <=
{_prod_T_4[65:1], count == 7'h3E & neg_out, _prod_T_4[0], remainder[63:1]};
end
else if (_GEN_0 | _GEN & remainder[63])
remainder <= {66'h0, 64'h0 - result};
if (_GEN & divisor[63])
divisor <= _subtractor_T_1;
end
neg_out <=
_GEN_5
? (cmdHi ? lhs_sign : lhs_sign != rhs_sign)
: ~(_GEN_3 & count == 7'h0 & ~(_subtractor_T_1[64]) & ~isHi) & neg_out;
resHi <= ~_GEN_5 & (_GEN_3 & _GEN_4 | _GEN_2 ? isHi : ~_GEN_0 & resHi);
end // always @(posedge)
assign io_req_ready = io_req_ready_0;
assign io_resp_valid = io_resp_valid_0;
assign io_resp_bits_data = {req_dw ? result[63:32] : {32{loOut[31]}}, loOut};
assign io_resp_bits_tag = req_tag;
endmodule
hardware/generated/genesys2-soc-verilog/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv
+18
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@@ -0,0 +1,18 @@
// Generated by CIRCT firtool-1.151.0
module NonSyncResetSynchronizerPrimitiveShiftReg_d3(
input clock,
io_d,
output io_q
);
reg sync_0;
reg sync_1;
reg sync_2;
always @(posedge clock) begin
sync_0 <= sync_1;
sync_1 <= sync_2;
sync_2 <= io_d;
end // always @(posedge)
assign io_q = sync_0;
endmodule
hardware/generated/genesys2-soc-verilog/OptimizationBarrier_TLBEntryData.sv
+54
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@@ -0,0 +1,54 @@
// Generated by CIRCT firtool-1.151.0
module OptimizationBarrier_TLBEntryData(
input io_x_u,
io_x_ae_ptw,
io_x_ae_final,
io_x_pf,
io_x_gf,
io_x_sw,
io_x_sx,
io_x_sr,
io_x_pw,
io_x_px,
io_x_pr,
io_x_ppp,
io_x_pal,
io_x_paa,
io_x_eff,
io_x_c,
output io_y_u,
io_y_ae_ptw,
io_y_ae_final,
io_y_pf,
io_y_gf,
io_y_sw,
io_y_sx,
io_y_sr,
io_y_pw,
io_y_px,
io_y_pr,
io_y_ppp,
io_y_pal,
io_y_paa,
io_y_eff,
io_y_c
);
assign io_y_u = io_x_u;
assign io_y_ae_ptw = io_x_ae_ptw;
assign io_y_ae_final = io_x_ae_final;
assign io_y_pf = io_x_pf;
assign io_y_gf = io_x_gf;
assign io_y_sw = io_x_sw;
assign io_y_sx = io_x_sx;
assign io_y_sr = io_x_sr;
assign io_y_pw = io_x_pw;
assign io_y_px = io_x_px;
assign io_y_pr = io_x_pr;
assign io_y_ppp = io_x_ppp;
assign io_y_pal = io_x_pal;
assign io_y_paa = io_x_paa;
assign io_y_eff = io_x_eff;
assign io_y_c = io_x_c;
endmodule
hardware/generated/genesys2-soc-verilog/PLICClockSinkDomain.sv
+71
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@@ -0,0 +1,71 @@
// Generated by CIRCT firtool-1.151.0
module PLICClockSinkDomain(
input auto_plic_int_in_0,
auto_plic_int_in_1,
auto_plic_int_in_2,
auto_plic_int_in_3,
auto_plic_int_in_4,
auto_plic_int_in_5,
auto_plic_int_in_6,
auto_plic_int_in_7,
auto_plic_int_in_8,
auto_plic_int_in_9,
auto_plic_int_in_10,
output auto_plic_in_a_ready,
input auto_plic_in_a_valid,
input [2:0] auto_plic_in_a_bits_opcode,
input [1:0] auto_plic_in_a_bits_size,
input [5:0] auto_plic_in_a_bits_source,
input [27:0] auto_plic_in_a_bits_address,
input [7:0] auto_plic_in_a_bits_mask,
input [63:0] auto_plic_in_a_bits_data,
input auto_plic_in_d_ready,
output auto_plic_in_d_valid,
output [2:0] auto_plic_in_d_bits_opcode,
output [1:0] auto_plic_in_d_bits_size,
output [5:0] auto_plic_in_d_bits_source,
output [63:0] auto_plic_in_d_bits_data,
output auto_int_in_clock_xing_out_sync_0,
input auto_clock_in_clock,
auto_clock_in_reset
);
wire _plic_auto_int_out_0;
TLPLIC plic (
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_int_in_0 (auto_plic_int_in_0),
.auto_int_in_1 (auto_plic_int_in_1),
.auto_int_in_2 (auto_plic_int_in_2),
.auto_int_in_3 (auto_plic_int_in_3),
.auto_int_in_4 (auto_plic_int_in_4),
.auto_int_in_5 (auto_plic_int_in_5),
.auto_int_in_6 (auto_plic_int_in_6),
.auto_int_in_7 (auto_plic_int_in_7),
.auto_int_in_8 (auto_plic_int_in_8),
.auto_int_in_9 (auto_plic_int_in_9),
.auto_int_in_10 (auto_plic_int_in_10),
.auto_int_out_0 (_plic_auto_int_out_0),
.auto_in_a_ready (auto_plic_in_a_ready),
.auto_in_a_valid (auto_plic_in_a_valid),
.auto_in_a_bits_opcode (auto_plic_in_a_bits_opcode),
.auto_in_a_bits_size (auto_plic_in_a_bits_size),
.auto_in_a_bits_source (auto_plic_in_a_bits_source),
.auto_in_a_bits_address (auto_plic_in_a_bits_address),
.auto_in_a_bits_mask (auto_plic_in_a_bits_mask),
.auto_in_a_bits_data (auto_plic_in_a_bits_data),
.auto_in_d_ready (auto_plic_in_d_ready),
.auto_in_d_valid (auto_plic_in_d_valid),
.auto_in_d_bits_opcode (auto_plic_in_d_bits_opcode),
.auto_in_d_bits_size (auto_plic_in_d_bits_size),
.auto_in_d_bits_source (auto_plic_in_d_bits_source),
.auto_in_d_bits_data (auto_plic_in_d_bits_data)
);
IntSyncCrossingSource_n1x1 intsource (
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_0),
.auto_out_sync_0 (auto_int_in_clock_xing_out_sync_0)
);
endmodule
hardware/generated/genesys2-soc-verilog/PLICFanIn.sv
+78
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@@ -0,0 +1,78 @@
// Generated by CIRCT firtool-1.151.0
module PLICFanIn(
input [2:0] io_prio_0,
io_prio_1,
io_prio_2,
io_prio_3,
io_prio_4,
io_prio_5,
io_prio_6,
io_prio_7,
io_prio_8,
io_prio_9,
io_prio_10,
input [10:0] io_ip,
output [3:0] io_dev,
output [2:0] io_max
);
wire [3:0] effectivePriority_1 = {io_ip[0], io_prio_0};
wire [3:0] effectivePriority_2 = {io_ip[1], io_prio_1};
wire [3:0] effectivePriority_3 = {io_ip[2], io_prio_2};
wire [3:0] effectivePriority_4 = {io_ip[3], io_prio_3};
wire [3:0] effectivePriority_5 = {io_ip[4], io_prio_4};
wire [3:0] effectivePriority_6 = {io_ip[5], io_prio_5};
wire [3:0] effectivePriority_7 = {io_ip[6], io_prio_6};
wire [3:0] effectivePriority_8 = {io_ip[7], io_prio_7};
wire [3:0] effectivePriority_9 = {io_ip[8], io_prio_8};
wire [3:0] effectivePriority_10 = {io_ip[9], io_prio_9};
wire [3:0] effectivePriority_11 = {io_ip[10], io_prio_10};
wire [3:0] left_left_left_1 = effectivePriority_1 < 4'h9 ? 4'h8 : effectivePriority_1;
wire [3:0] left_left_right_1 =
effectivePriority_2 >= effectivePriority_3
? effectivePriority_2
: effectivePriority_3;
wire _left_left_T = left_left_left_1 >= left_left_right_1;
wire [3:0] left_left_1 = _left_left_T ? left_left_left_1 : left_left_right_1;
wire [3:0] left_right_left_1 =
effectivePriority_4 >= effectivePriority_5
? effectivePriority_4
: effectivePriority_5;
wire [3:0] left_right_right_1 =
effectivePriority_6 >= effectivePriority_7
? effectivePriority_6
: effectivePriority_7;
wire _left_right_T = left_right_left_1 >= left_right_right_1;
wire [3:0] left_right_1 = _left_right_T ? left_right_left_1 : left_right_right_1;
wire _left_T = left_left_1 >= left_right_1;
wire [3:0] left_1 = _left_T ? left_left_1 : left_right_1;
wire [3:0] right_left_1 =
effectivePriority_8 >= effectivePriority_9
? effectivePriority_8
: effectivePriority_9;
wire [3:0] right_right_1 =
effectivePriority_10 >= effectivePriority_11
? effectivePriority_10
: effectivePriority_11;
wire _right_T = right_left_1 >= right_right_1;
wire [3:0] right_1 = _right_T ? right_left_1 : right_right_1;
wire _GEN = left_1 >= right_1;
assign io_dev =
_GEN
? {1'h0,
_left_T
? {1'h0,
_left_left_T
? {1'h0, effectivePriority_1 > 4'h8}
: {1'h1, effectivePriority_2 < effectivePriority_3}}
: {1'h1,
_left_right_T
? {1'h0, effectivePriority_4 < effectivePriority_5}
: {1'h1, effectivePriority_6 < effectivePriority_7}}}
: {2'h2,
_right_T
? {1'h0, effectivePriority_8 < effectivePriority_9}
: {1'h1, effectivePriority_10 < effectivePriority_11}};
assign io_max = _GEN ? left_1[2:0] : right_1[2:0];
endmodule
hardware/generated/genesys2-soc-verilog/PMAChecker.sv
+66
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@@ -0,0 +1,66 @@
// Generated by CIRCT firtool-1.151.0
module PMAChecker(
input [33:0] io_paddr,
output io_resp_r,
io_resp_w,
io_resp_pp,
io_resp_al,
io_resp_aa,
io_resp_x,
io_resp_eff
);
wire [9:0] _GEN = io_paddr[25:16] ^ 10'h200;
wire [16:0] _GEN_0 = io_paddr[28:12] ^ 17'h10014;
wire [11:0] _GEN_1 = io_paddr[31:20] ^ 12'h800;
wire legal_address =
io_paddr[33:12] == 22'h0 | {io_paddr[33:14], ~(io_paddr[13:12])} == 22'h0
| {io_paddr[33:17], ~(io_paddr[16])} == 18'h0 | {io_paddr[33:26], _GEN} == 18'h0
| {io_paddr[33:28], ~(io_paddr[27:26])} == 8'h0
| {io_paddr[33:29], io_paddr[28:12] ^ 17'h10013} == 22'h0
| {io_paddr[33:29], _GEN_0} == 22'h0
| {io_paddr[33:29], io_paddr[28:12] ^ 17'h10015} == 22'h0
| {io_paddr[33:29], io_paddr[28:12] ^ 17'h10020} == 22'h0
| {io_paddr[33:29], io_paddr[28:12] ^ 17'h10021} == 22'h0
| {io_paddr[33:29], io_paddr[28:12] ^ 17'h10022} == 22'h0
| {io_paddr[33:29], io_paddr[28:12] ^ 17'h10023} == 22'h0
| {io_paddr[33:29], io_paddr[28:12] ^ 17'h10024} == 22'h0
| {io_paddr[33:29], io_paddr[28:12] ^ 17'h10025} == 22'h0
| {io_paddr[33:29], io_paddr[28:12] ^ 17'h10026} == 22'h0
| {io_paddr[33:29], io_paddr[28:12] ^ 17'h10027} == 22'h0
| {io_paddr[33:29], io_paddr[28:12] ^ 17'h10028} == 22'h0
| {io_paddr[33:29], io_paddr[28:12] ^ 17'h10029} == 22'h0
| {io_paddr[33:29], io_paddr[28:12] ^ 17'h1002A} == 22'h0
| {io_paddr[33:32], _GEN_1} == 14'h0;
wire _GEN_2 = |{io_paddr[31:29], io_paddr[27], io_paddr[16]};
wire _GEN_3 = |{io_paddr[31:27], io_paddr[16], io_paddr[14]};
wire _GEN_4 = |{io_paddr[31:28], ~(io_paddr[27])};
wire [16:0] _GEN_5 = io_paddr[28:12] ^ 17'h10011;
wire _GEN_6 =
|{io_paddr[31:29], _GEN_5[16:15], _GEN_5[4], io_paddr[14], _GEN_5[0]};
wire _GEN_7 = |{io_paddr[31:29], _GEN_0[16:15], _GEN_0[4], _GEN_0[2]};
wire _GEN_8 = |(_GEN_1[11:7]);
wire [14:0] _GEN_9 = io_paddr[28:14] ^ 15'h4002;
assign io_resp_r = legal_address;
assign io_resp_w =
legal_address & (~_GEN_2 | ~_GEN_3 | ~_GEN_4 | ~_GEN_6 | ~_GEN_7 | ~_GEN_8);
assign io_resp_pp =
legal_address & (~_GEN_2 | ~_GEN_3 | ~_GEN_4 | ~_GEN_6 | ~_GEN_7 | ~_GEN_8);
assign io_resp_al =
legal_address & (~_GEN_2 | ~_GEN_3 | ~_GEN_4 | ~_GEN_6 | ~_GEN_7 | ~_GEN_8);
assign io_resp_aa =
legal_address & (~_GEN_2 | ~_GEN_3 | ~_GEN_4 | ~_GEN_6 | ~_GEN_7 | ~_GEN_8);
assign io_resp_x =
legal_address
& ({io_paddr[30:27], io_paddr[25]} == 5'h0
| {io_paddr[31:27], io_paddr[25], io_paddr[14]} == 7'h0);
assign io_resp_eff =
legal_address
& ({io_paddr[31:27], io_paddr[25], io_paddr[16:14], io_paddr[12]} == 10'h0
| {io_paddr[31:27], _GEN[9], io_paddr[16]} == 7'h0 | ~_GEN_4
| {io_paddr[31:29], io_paddr[28:27] ^ 2'h2, io_paddr[25], io_paddr[16:15]} == 8'h0
| {io_paddr[31:29], _GEN_9[14:13], io_paddr[25], _GEN_9[2:0]} == 9'h0
| {io_paddr[31:29], _GEN_5[16:15], io_paddr[25], _GEN_5[4:2], _GEN_5[0]} == 10'h0
| {io_paddr[31:29], _GEN_0[16:15], io_paddr[25], _GEN_0[4:2]} == 9'h0);
endmodule
hardware/generated/genesys2-soc-verilog/PMPChecker_s2.sv
+90
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@@ -0,0 +1,90 @@
// Generated by CIRCT firtool-1.151.0
module PMPChecker_s2(
input io_pmp_0_cfg_l,
input [1:0] io_pmp_0_cfg_a,
input io_pmp_0_cfg_x,
input [29:0] io_pmp_0_addr,
input [31:0] io_pmp_0_mask,
input io_pmp_1_cfg_l,
input [1:0] io_pmp_1_cfg_a,
input io_pmp_1_cfg_x,
input [29:0] io_pmp_1_addr,
input [31:0] io_pmp_1_mask,
input io_pmp_2_cfg_l,
input [1:0] io_pmp_2_cfg_a,
input io_pmp_2_cfg_x,
input [29:0] io_pmp_2_addr,
input [31:0] io_pmp_2_mask,
input io_pmp_3_cfg_l,
input [1:0] io_pmp_3_cfg_a,
input io_pmp_3_cfg_x,
input [29:0] io_pmp_3_addr,
input [31:0] io_pmp_3_mask,
input io_pmp_4_cfg_l,
input [1:0] io_pmp_4_cfg_a,
input io_pmp_4_cfg_x,
input [29:0] io_pmp_4_addr,
input [31:0] io_pmp_4_mask,
input io_pmp_5_cfg_l,
input [1:0] io_pmp_5_cfg_a,
input io_pmp_5_cfg_x,
input [29:0] io_pmp_5_addr,
input [31:0] io_pmp_5_mask,
input io_pmp_6_cfg_l,
input [1:0] io_pmp_6_cfg_a,
input io_pmp_6_cfg_x,
input [29:0] io_pmp_6_addr,
input [31:0] io_pmp_6_mask,
input io_pmp_7_cfg_l,
input [1:0] io_pmp_7_cfg_a,
input io_pmp_7_cfg_x,
input [29:0] io_pmp_7_addr,
input [31:0] io_pmp_7_mask,
io_addr,
output io_x
);
assign io_x =
(io_pmp_0_cfg_a[1]
? ((io_addr ^ {io_pmp_0_addr, 2'h0}) & ~io_pmp_0_mask) == 32'h0
: io_pmp_0_cfg_a[0] & io_addr < {io_pmp_0_addr, 2'h0})
? io_pmp_0_cfg_x | ~io_pmp_0_cfg_l
: (io_pmp_1_cfg_a[1]
? ((io_addr ^ {io_pmp_1_addr, 2'h0}) & ~io_pmp_1_mask) == 32'h0
: io_pmp_1_cfg_a[0] & io_addr >= {io_pmp_0_addr, 2'h0}
& io_addr < {io_pmp_1_addr, 2'h0})
? io_pmp_1_cfg_x | ~io_pmp_1_cfg_l
: (io_pmp_2_cfg_a[1]
? ((io_addr ^ {io_pmp_2_addr, 2'h0}) & ~io_pmp_2_mask) == 32'h0
: io_pmp_2_cfg_a[0] & io_addr >= {io_pmp_1_addr, 2'h0}
& io_addr < {io_pmp_2_addr, 2'h0})
? io_pmp_2_cfg_x | ~io_pmp_2_cfg_l
: (io_pmp_3_cfg_a[1]
? ((io_addr ^ {io_pmp_3_addr, 2'h0}) & ~io_pmp_3_mask) == 32'h0
: io_pmp_3_cfg_a[0] & io_addr >= {io_pmp_2_addr, 2'h0}
& io_addr < {io_pmp_3_addr, 2'h0})
? io_pmp_3_cfg_x | ~io_pmp_3_cfg_l
: (io_pmp_4_cfg_a[1]
? ((io_addr ^ {io_pmp_4_addr, 2'h0}) & ~io_pmp_4_mask) == 32'h0
: io_pmp_4_cfg_a[0] & io_addr >= {io_pmp_3_addr, 2'h0}
& io_addr < {io_pmp_4_addr, 2'h0})
? io_pmp_4_cfg_x | ~io_pmp_4_cfg_l
: (io_pmp_5_cfg_a[1]
? ((io_addr ^ {io_pmp_5_addr, 2'h0}) & ~io_pmp_5_mask) == 32'h0
: io_pmp_5_cfg_a[0] & io_addr >= {io_pmp_4_addr, 2'h0}
& io_addr < {io_pmp_5_addr, 2'h0})
? io_pmp_5_cfg_x | ~io_pmp_5_cfg_l
: (io_pmp_6_cfg_a[1]
? ((io_addr ^ {io_pmp_6_addr, 2'h0})
& ~io_pmp_6_mask) == 32'h0
: io_pmp_6_cfg_a[0] & io_addr >= {io_pmp_5_addr, 2'h0}
& io_addr < {io_pmp_6_addr, 2'h0})
? io_pmp_6_cfg_x | ~io_pmp_6_cfg_l
: ~(io_pmp_7_cfg_a[1]
? ((io_addr ^ {io_pmp_7_addr, 2'h0})
& ~io_pmp_7_mask) == 32'h0
: io_pmp_7_cfg_a[0] & io_addr >= {io_pmp_6_addr, 2'h0}
& io_addr < {io_pmp_7_addr, 2'h0}) | io_pmp_7_cfg_x
| ~io_pmp_7_cfg_l;
endmodule
hardware/generated/genesys2-soc-verilog/PMPChecker_s3.sv
+259
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@@ -0,0 +1,259 @@
// Generated by CIRCT firtool-1.151.0
module PMPChecker_s3(
input [1:0] io_prv,
input io_pmp_0_cfg_l,
input [1:0] io_pmp_0_cfg_a,
input io_pmp_0_cfg_w,
io_pmp_0_cfg_r,
input [29:0] io_pmp_0_addr,
input [31:0] io_pmp_0_mask,
input io_pmp_1_cfg_l,
input [1:0] io_pmp_1_cfg_a,
input io_pmp_1_cfg_w,
io_pmp_1_cfg_r,
input [29:0] io_pmp_1_addr,
input [31:0] io_pmp_1_mask,
input io_pmp_2_cfg_l,
input [1:0] io_pmp_2_cfg_a,
input io_pmp_2_cfg_w,
io_pmp_2_cfg_r,
input [29:0] io_pmp_2_addr,
input [31:0] io_pmp_2_mask,
input io_pmp_3_cfg_l,
input [1:0] io_pmp_3_cfg_a,
input io_pmp_3_cfg_w,
io_pmp_3_cfg_r,
input [29:0] io_pmp_3_addr,
input [31:0] io_pmp_3_mask,
input io_pmp_4_cfg_l,
input [1:0] io_pmp_4_cfg_a,
input io_pmp_4_cfg_w,
io_pmp_4_cfg_r,
input [29:0] io_pmp_4_addr,
input [31:0] io_pmp_4_mask,
input io_pmp_5_cfg_l,
input [1:0] io_pmp_5_cfg_a,
input io_pmp_5_cfg_w,
io_pmp_5_cfg_r,
input [29:0] io_pmp_5_addr,
input [31:0] io_pmp_5_mask,
input io_pmp_6_cfg_l,
input [1:0] io_pmp_6_cfg_a,
input io_pmp_6_cfg_w,
io_pmp_6_cfg_r,
input [29:0] io_pmp_6_addr,
input [31:0] io_pmp_6_mask,
input io_pmp_7_cfg_l,
input [1:0] io_pmp_7_cfg_a,
input io_pmp_7_cfg_w,
io_pmp_7_cfg_r,
input [29:0] io_pmp_7_addr,
input [31:0] io_pmp_7_mask,
io_addr,
input [1:0] io_size,
output io_r,
io_w
);
wire [5:0] _res_aligned_lsbMask_T_14 = 6'h7 << io_size;
wire res_hit =
io_pmp_7_cfg_a[1]
? ((io_addr[31:3] ^ io_pmp_7_addr[29:1]) & ~(io_pmp_7_mask[31:3])) == 29'h0
& ((io_addr[2:0] ^ {io_pmp_7_addr[0], 2'h0})
& ~(io_pmp_7_mask[2:0] | ~(_res_aligned_lsbMask_T_14[2:0]))) == 3'h0
: io_pmp_7_cfg_a[0]
& ~(io_addr[31:3] < io_pmp_6_addr[29:1]
| (io_addr[31:3] ^ io_pmp_6_addr[29:1]) == 29'h0
& (io_addr[2:0]
| ~(_res_aligned_lsbMask_T_14[2:0])) < {io_pmp_6_addr[0], 2'h0})
& (io_addr[31:3] < io_pmp_7_addr[29:1]
| (io_addr[31:3] ^ io_pmp_7_addr[29:1]) == 29'h0
& io_addr[2:0] < {io_pmp_7_addr[0], 2'h0});
wire res_ignore = io_prv[1] & ~io_pmp_7_cfg_l;
wire [2:0] res_aligned_lsbMask = ~(_res_aligned_lsbMask_T_14[2:0]);
wire res_aligned =
io_pmp_7_cfg_a[1]
? (res_aligned_lsbMask & ~(io_pmp_7_mask[2:0])) == 3'h0
: ~((io_addr[31:3] ^ io_pmp_6_addr[29:1]) == 29'h0 & io_pmp_6_addr[0]
& ~(io_addr[2]) | (io_addr[31:3] ^ io_pmp_7_addr[29:1]) == 29'h0
& io_pmp_7_addr[0] & (io_addr[2] | res_aligned_lsbMask[2]));
wire res_hit_1 =
io_pmp_6_cfg_a[1]
? ((io_addr[31:3] ^ io_pmp_6_addr[29:1]) & ~(io_pmp_6_mask[31:3])) == 29'h0
& ((io_addr[2:0] ^ {io_pmp_6_addr[0], 2'h0})
& ~(io_pmp_6_mask[2:0] | ~(_res_aligned_lsbMask_T_14[2:0]))) == 3'h0
: io_pmp_6_cfg_a[0]
& ~(io_addr[31:3] < io_pmp_5_addr[29:1]
| (io_addr[31:3] ^ io_pmp_5_addr[29:1]) == 29'h0
& (io_addr[2:0]
| ~(_res_aligned_lsbMask_T_14[2:0])) < {io_pmp_5_addr[0], 2'h0})
& (io_addr[31:3] < io_pmp_6_addr[29:1]
| (io_addr[31:3] ^ io_pmp_6_addr[29:1]) == 29'h0
& io_addr[2:0] < {io_pmp_6_addr[0], 2'h0});
wire res_ignore_1 = io_prv[1] & ~io_pmp_6_cfg_l;
wire [2:0] res_aligned_lsbMask_1 = ~(_res_aligned_lsbMask_T_14[2:0]);
wire res_aligned_1 =
io_pmp_6_cfg_a[1]
? (res_aligned_lsbMask_1 & ~(io_pmp_6_mask[2:0])) == 3'h0
: ~((io_addr[31:3] ^ io_pmp_5_addr[29:1]) == 29'h0 & io_pmp_5_addr[0]
& ~(io_addr[2]) | (io_addr[31:3] ^ io_pmp_6_addr[29:1]) == 29'h0
& io_pmp_6_addr[0] & (io_addr[2] | res_aligned_lsbMask_1[2]));
wire res_hit_2 =
io_pmp_5_cfg_a[1]
? ((io_addr[31:3] ^ io_pmp_5_addr[29:1]) & ~(io_pmp_5_mask[31:3])) == 29'h0
& ((io_addr[2:0] ^ {io_pmp_5_addr[0], 2'h0})
& ~(io_pmp_5_mask[2:0] | ~(_res_aligned_lsbMask_T_14[2:0]))) == 3'h0
: io_pmp_5_cfg_a[0]
& ~(io_addr[31:3] < io_pmp_4_addr[29:1]
| (io_addr[31:3] ^ io_pmp_4_addr[29:1]) == 29'h0
& (io_addr[2:0]
| ~(_res_aligned_lsbMask_T_14[2:0])) < {io_pmp_4_addr[0], 2'h0})
& (io_addr[31:3] < io_pmp_5_addr[29:1]
| (io_addr[31:3] ^ io_pmp_5_addr[29:1]) == 29'h0
& io_addr[2:0] < {io_pmp_5_addr[0], 2'h0});
wire res_ignore_2 = io_prv[1] & ~io_pmp_5_cfg_l;
wire [2:0] res_aligned_lsbMask_2 = ~(_res_aligned_lsbMask_T_14[2:0]);
wire res_aligned_2 =
io_pmp_5_cfg_a[1]
? (res_aligned_lsbMask_2 & ~(io_pmp_5_mask[2:0])) == 3'h0
: ~((io_addr[31:3] ^ io_pmp_4_addr[29:1]) == 29'h0 & io_pmp_4_addr[0]
& ~(io_addr[2]) | (io_addr[31:3] ^ io_pmp_5_addr[29:1]) == 29'h0
& io_pmp_5_addr[0] & (io_addr[2] | res_aligned_lsbMask_2[2]));
wire res_hit_3 =
io_pmp_4_cfg_a[1]
? ((io_addr[31:3] ^ io_pmp_4_addr[29:1]) & ~(io_pmp_4_mask[31:3])) == 29'h0
& ((io_addr[2:0] ^ {io_pmp_4_addr[0], 2'h0})
& ~(io_pmp_4_mask[2:0] | ~(_res_aligned_lsbMask_T_14[2:0]))) == 3'h0
: io_pmp_4_cfg_a[0]
& ~(io_addr[31:3] < io_pmp_3_addr[29:1]
| (io_addr[31:3] ^ io_pmp_3_addr[29:1]) == 29'h0
& (io_addr[2:0]
| ~(_res_aligned_lsbMask_T_14[2:0])) < {io_pmp_3_addr[0], 2'h0})
& (io_addr[31:3] < io_pmp_4_addr[29:1]
| (io_addr[31:3] ^ io_pmp_4_addr[29:1]) == 29'h0
& io_addr[2:0] < {io_pmp_4_addr[0], 2'h0});
wire res_ignore_3 = io_prv[1] & ~io_pmp_4_cfg_l;
wire [2:0] res_aligned_lsbMask_3 = ~(_res_aligned_lsbMask_T_14[2:0]);
wire res_aligned_3 =
io_pmp_4_cfg_a[1]
? (res_aligned_lsbMask_3 & ~(io_pmp_4_mask[2:0])) == 3'h0
: ~((io_addr[31:3] ^ io_pmp_3_addr[29:1]) == 29'h0 & io_pmp_3_addr[0]
& ~(io_addr[2]) | (io_addr[31:3] ^ io_pmp_4_addr[29:1]) == 29'h0
& io_pmp_4_addr[0] & (io_addr[2] | res_aligned_lsbMask_3[2]));
wire res_hit_4 =
io_pmp_3_cfg_a[1]
? ((io_addr[31:3] ^ io_pmp_3_addr[29:1]) & ~(io_pmp_3_mask[31:3])) == 29'h0
& ((io_addr[2:0] ^ {io_pmp_3_addr[0], 2'h0})
& ~(io_pmp_3_mask[2:0] | ~(_res_aligned_lsbMask_T_14[2:0]))) == 3'h0
: io_pmp_3_cfg_a[0]
& ~(io_addr[31:3] < io_pmp_2_addr[29:1]
| (io_addr[31:3] ^ io_pmp_2_addr[29:1]) == 29'h0
& (io_addr[2:0]
| ~(_res_aligned_lsbMask_T_14[2:0])) < {io_pmp_2_addr[0], 2'h0})
& (io_addr[31:3] < io_pmp_3_addr[29:1]
| (io_addr[31:3] ^ io_pmp_3_addr[29:1]) == 29'h0
& io_addr[2:0] < {io_pmp_3_addr[0], 2'h0});
wire res_ignore_4 = io_prv[1] & ~io_pmp_3_cfg_l;
wire [2:0] res_aligned_lsbMask_4 = ~(_res_aligned_lsbMask_T_14[2:0]);
wire res_aligned_4 =
io_pmp_3_cfg_a[1]
? (res_aligned_lsbMask_4 & ~(io_pmp_3_mask[2:0])) == 3'h0
: ~((io_addr[31:3] ^ io_pmp_2_addr[29:1]) == 29'h0 & io_pmp_2_addr[0]
& ~(io_addr[2]) | (io_addr[31:3] ^ io_pmp_3_addr[29:1]) == 29'h0
& io_pmp_3_addr[0] & (io_addr[2] | res_aligned_lsbMask_4[2]));
wire res_hit_5 =
io_pmp_2_cfg_a[1]
? ((io_addr[31:3] ^ io_pmp_2_addr[29:1]) & ~(io_pmp_2_mask[31:3])) == 29'h0
& ((io_addr[2:0] ^ {io_pmp_2_addr[0], 2'h0})
& ~(io_pmp_2_mask[2:0] | ~(_res_aligned_lsbMask_T_14[2:0]))) == 3'h0
: io_pmp_2_cfg_a[0]
& ~(io_addr[31:3] < io_pmp_1_addr[29:1]
| (io_addr[31:3] ^ io_pmp_1_addr[29:1]) == 29'h0
& (io_addr[2:0]
| ~(_res_aligned_lsbMask_T_14[2:0])) < {io_pmp_1_addr[0], 2'h0})
& (io_addr[31:3] < io_pmp_2_addr[29:1]
| (io_addr[31:3] ^ io_pmp_2_addr[29:1]) == 29'h0
& io_addr[2:0] < {io_pmp_2_addr[0], 2'h0});
wire res_ignore_5 = io_prv[1] & ~io_pmp_2_cfg_l;
wire [2:0] res_aligned_lsbMask_5 = ~(_res_aligned_lsbMask_T_14[2:0]);
wire res_aligned_5 =
io_pmp_2_cfg_a[1]
? (res_aligned_lsbMask_5 & ~(io_pmp_2_mask[2:0])) == 3'h0
: ~((io_addr[31:3] ^ io_pmp_1_addr[29:1]) == 29'h0 & io_pmp_1_addr[0]
& ~(io_addr[2]) | (io_addr[31:3] ^ io_pmp_2_addr[29:1]) == 29'h0
& io_pmp_2_addr[0] & (io_addr[2] | res_aligned_lsbMask_5[2]));
wire res_hit_6 =
io_pmp_1_cfg_a[1]
? ((io_addr[31:3] ^ io_pmp_1_addr[29:1]) & ~(io_pmp_1_mask[31:3])) == 29'h0
& ((io_addr[2:0] ^ {io_pmp_1_addr[0], 2'h0})
& ~(io_pmp_1_mask[2:0] | ~(_res_aligned_lsbMask_T_14[2:0]))) == 3'h0
: io_pmp_1_cfg_a[0]
& ~(io_addr[31:3] < io_pmp_0_addr[29:1]
| (io_addr[31:3] ^ io_pmp_0_addr[29:1]) == 29'h0
& (io_addr[2:0]
| ~(_res_aligned_lsbMask_T_14[2:0])) < {io_pmp_0_addr[0], 2'h0})
& (io_addr[31:3] < io_pmp_1_addr[29:1]
| (io_addr[31:3] ^ io_pmp_1_addr[29:1]) == 29'h0
& io_addr[2:0] < {io_pmp_1_addr[0], 2'h0});
wire res_ignore_6 = io_prv[1] & ~io_pmp_1_cfg_l;
wire [2:0] res_aligned_lsbMask_6 = ~(_res_aligned_lsbMask_T_14[2:0]);
wire res_aligned_6 =
io_pmp_1_cfg_a[1]
? (res_aligned_lsbMask_6 & ~(io_pmp_1_mask[2:0])) == 3'h0
: ~((io_addr[31:3] ^ io_pmp_0_addr[29:1]) == 29'h0 & io_pmp_0_addr[0]
& ~(io_addr[2]) | (io_addr[31:3] ^ io_pmp_1_addr[29:1]) == 29'h0
& io_pmp_1_addr[0] & (io_addr[2] | res_aligned_lsbMask_6[2]));
wire res_hit_7 =
io_pmp_0_cfg_a[1]
? ((io_addr[31:3] ^ io_pmp_0_addr[29:1]) & ~(io_pmp_0_mask[31:3])) == 29'h0
& ((io_addr[2:0] ^ {io_pmp_0_addr[0], 2'h0})
& ~(io_pmp_0_mask[2:0] | ~(_res_aligned_lsbMask_T_14[2:0]))) == 3'h0
: io_pmp_0_cfg_a[0]
& (io_addr[31:3] < io_pmp_0_addr[29:1]
| (io_addr[31:3] ^ io_pmp_0_addr[29:1]) == 29'h0
& io_addr[2:0] < {io_pmp_0_addr[0], 2'h0});
wire res_ignore_7 = io_prv[1] & ~io_pmp_0_cfg_l;
wire [2:0] res_aligned_lsbMask_7 = ~(_res_aligned_lsbMask_T_14[2:0]);
wire res_aligned_7 =
io_pmp_0_cfg_a[1]
? (res_aligned_lsbMask_7 & ~(io_pmp_0_mask[2:0])) == 3'h0
: ~((io_addr[31:3] ^ io_pmp_0_addr[29:1]) == 29'h0 & io_pmp_0_addr[0]
& (io_addr[2] | res_aligned_lsbMask_7[2]));
assign io_r =
res_hit_7
? res_aligned_7 & (io_pmp_0_cfg_r | res_ignore_7)
: res_hit_6
? res_aligned_6 & (io_pmp_1_cfg_r | res_ignore_6)
: res_hit_5
? res_aligned_5 & (io_pmp_2_cfg_r | res_ignore_5)
: res_hit_4
? res_aligned_4 & (io_pmp_3_cfg_r | res_ignore_4)
: res_hit_3
? res_aligned_3 & (io_pmp_4_cfg_r | res_ignore_3)
: res_hit_2
? res_aligned_2 & (io_pmp_5_cfg_r | res_ignore_2)
: res_hit_1
? res_aligned_1 & (io_pmp_6_cfg_r | res_ignore_1)
: res_hit
? res_aligned & (io_pmp_7_cfg_r | res_ignore)
: io_prv[1];
assign io_w =
res_hit_7
? res_aligned_7 & (io_pmp_0_cfg_w | res_ignore_7)
: res_hit_6
? res_aligned_6 & (io_pmp_1_cfg_w | res_ignore_6)
: res_hit_5
? res_aligned_5 & (io_pmp_2_cfg_w | res_ignore_5)
: res_hit_4
? res_aligned_4 & (io_pmp_3_cfg_w | res_ignore_4)
: res_hit_3
? res_aligned_3 & (io_pmp_4_cfg_w | res_ignore_3)
: res_hit_2
? res_aligned_2 & (io_pmp_5_cfg_w | res_ignore_2)
: res_hit_1
? res_aligned_1 & (io_pmp_6_cfg_w | res_ignore_1)
: res_hit
? res_aligned & (io_pmp_7_cfg_w | res_ignore)
: io_prv[1];
endmodule
hardware/generated/genesys2-soc-verilog/PTW.sv
+256
View File
@@ -0,0 +1,256 @@
// Generated by CIRCT firtool-1.151.0
// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifndef PRINTF_COND_
`ifdef PRINTF_COND
`define PRINTF_COND_ (`PRINTF_COND)
`else // PRINTF_COND
`define PRINTF_COND_ 1
`endif // PRINTF_COND
`endif // not def PRINTF_COND_
module PTW(
input clock,
output io_requestor_0_status_debug,
io_requestor_0_pmp_0_cfg_l,
output [1:0] io_requestor_0_pmp_0_cfg_a,
output io_requestor_0_pmp_0_cfg_w,
io_requestor_0_pmp_0_cfg_r,
output [29:0] io_requestor_0_pmp_0_addr,
output [31:0] io_requestor_0_pmp_0_mask,
output io_requestor_0_pmp_1_cfg_l,
output [1:0] io_requestor_0_pmp_1_cfg_a,
output io_requestor_0_pmp_1_cfg_w,
io_requestor_0_pmp_1_cfg_r,
output [29:0] io_requestor_0_pmp_1_addr,
output [31:0] io_requestor_0_pmp_1_mask,
output io_requestor_0_pmp_2_cfg_l,
output [1:0] io_requestor_0_pmp_2_cfg_a,
output io_requestor_0_pmp_2_cfg_w,
io_requestor_0_pmp_2_cfg_r,
output [29:0] io_requestor_0_pmp_2_addr,
output [31:0] io_requestor_0_pmp_2_mask,
output io_requestor_0_pmp_3_cfg_l,
output [1:0] io_requestor_0_pmp_3_cfg_a,
output io_requestor_0_pmp_3_cfg_w,
io_requestor_0_pmp_3_cfg_r,
output [29:0] io_requestor_0_pmp_3_addr,
output [31:0] io_requestor_0_pmp_3_mask,
output io_requestor_0_pmp_4_cfg_l,
output [1:0] io_requestor_0_pmp_4_cfg_a,
output io_requestor_0_pmp_4_cfg_w,
io_requestor_0_pmp_4_cfg_r,
output [29:0] io_requestor_0_pmp_4_addr,
output [31:0] io_requestor_0_pmp_4_mask,
output io_requestor_0_pmp_5_cfg_l,
output [1:0] io_requestor_0_pmp_5_cfg_a,
output io_requestor_0_pmp_5_cfg_w,
io_requestor_0_pmp_5_cfg_r,
output [29:0] io_requestor_0_pmp_5_addr,
output [31:0] io_requestor_0_pmp_5_mask,
output io_requestor_0_pmp_6_cfg_l,
output [1:0] io_requestor_0_pmp_6_cfg_a,
output io_requestor_0_pmp_6_cfg_w,
io_requestor_0_pmp_6_cfg_r,
output [29:0] io_requestor_0_pmp_6_addr,
output [31:0] io_requestor_0_pmp_6_mask,
output io_requestor_0_pmp_7_cfg_l,
output [1:0] io_requestor_0_pmp_7_cfg_a,
output io_requestor_0_pmp_7_cfg_w,
io_requestor_0_pmp_7_cfg_r,
output [29:0] io_requestor_0_pmp_7_addr,
output [31:0] io_requestor_0_pmp_7_mask,
output io_requestor_1_status_debug,
io_requestor_1_pmp_0_cfg_l,
output [1:0] io_requestor_1_pmp_0_cfg_a,
output io_requestor_1_pmp_0_cfg_x,
output [29:0] io_requestor_1_pmp_0_addr,
output [31:0] io_requestor_1_pmp_0_mask,
output io_requestor_1_pmp_1_cfg_l,
output [1:0] io_requestor_1_pmp_1_cfg_a,
output io_requestor_1_pmp_1_cfg_x,
output [29:0] io_requestor_1_pmp_1_addr,
output [31:0] io_requestor_1_pmp_1_mask,
output io_requestor_1_pmp_2_cfg_l,
output [1:0] io_requestor_1_pmp_2_cfg_a,
output io_requestor_1_pmp_2_cfg_x,
output [29:0] io_requestor_1_pmp_2_addr,
output [31:0] io_requestor_1_pmp_2_mask,
output io_requestor_1_pmp_3_cfg_l,
output [1:0] io_requestor_1_pmp_3_cfg_a,
output io_requestor_1_pmp_3_cfg_x,
output [29:0] io_requestor_1_pmp_3_addr,
output [31:0] io_requestor_1_pmp_3_mask,
output io_requestor_1_pmp_4_cfg_l,
output [1:0] io_requestor_1_pmp_4_cfg_a,
output io_requestor_1_pmp_4_cfg_x,
output [29:0] io_requestor_1_pmp_4_addr,
output [31:0] io_requestor_1_pmp_4_mask,
output io_requestor_1_pmp_5_cfg_l,
output [1:0] io_requestor_1_pmp_5_cfg_a,
output io_requestor_1_pmp_5_cfg_x,
output [29:0] io_requestor_1_pmp_5_addr,
output [31:0] io_requestor_1_pmp_5_mask,
output io_requestor_1_pmp_6_cfg_l,
output [1:0] io_requestor_1_pmp_6_cfg_a,
output io_requestor_1_pmp_6_cfg_x,
output [29:0] io_requestor_1_pmp_6_addr,
output [31:0] io_requestor_1_pmp_6_mask,
output io_requestor_1_pmp_7_cfg_l,
output [1:0] io_requestor_1_pmp_7_cfg_a,
output io_requestor_1_pmp_7_cfg_x,
output [29:0] io_requestor_1_pmp_7_addr,
output [31:0] io_requestor_1_pmp_7_mask,
output [63:0] io_requestor_1_customCSRs_csrs_0_value,
input io_dpath_status_debug,
io_dpath_pmp_0_cfg_l,
input [1:0] io_dpath_pmp_0_cfg_a,
input io_dpath_pmp_0_cfg_x,
io_dpath_pmp_0_cfg_w,
io_dpath_pmp_0_cfg_r,
input [29:0] io_dpath_pmp_0_addr,
input [31:0] io_dpath_pmp_0_mask,
input io_dpath_pmp_1_cfg_l,
input [1:0] io_dpath_pmp_1_cfg_a,
input io_dpath_pmp_1_cfg_x,
io_dpath_pmp_1_cfg_w,
io_dpath_pmp_1_cfg_r,
input [29:0] io_dpath_pmp_1_addr,
input [31:0] io_dpath_pmp_1_mask,
input io_dpath_pmp_2_cfg_l,
input [1:0] io_dpath_pmp_2_cfg_a,
input io_dpath_pmp_2_cfg_x,
io_dpath_pmp_2_cfg_w,
io_dpath_pmp_2_cfg_r,
input [29:0] io_dpath_pmp_2_addr,
input [31:0] io_dpath_pmp_2_mask,
input io_dpath_pmp_3_cfg_l,
input [1:0] io_dpath_pmp_3_cfg_a,
input io_dpath_pmp_3_cfg_x,
io_dpath_pmp_3_cfg_w,
io_dpath_pmp_3_cfg_r,
input [29:0] io_dpath_pmp_3_addr,
input [31:0] io_dpath_pmp_3_mask,
input io_dpath_pmp_4_cfg_l,
input [1:0] io_dpath_pmp_4_cfg_a,
input io_dpath_pmp_4_cfg_x,
io_dpath_pmp_4_cfg_w,
io_dpath_pmp_4_cfg_r,
input [29:0] io_dpath_pmp_4_addr,
input [31:0] io_dpath_pmp_4_mask,
input io_dpath_pmp_5_cfg_l,
input [1:0] io_dpath_pmp_5_cfg_a,
input io_dpath_pmp_5_cfg_x,
io_dpath_pmp_5_cfg_w,
io_dpath_pmp_5_cfg_r,
input [29:0] io_dpath_pmp_5_addr,
input [31:0] io_dpath_pmp_5_mask,
input io_dpath_pmp_6_cfg_l,
input [1:0] io_dpath_pmp_6_cfg_a,
input io_dpath_pmp_6_cfg_x,
io_dpath_pmp_6_cfg_w,
io_dpath_pmp_6_cfg_r,
input [29:0] io_dpath_pmp_6_addr,
input [31:0] io_dpath_pmp_6_mask,
input io_dpath_pmp_7_cfg_l,
input [1:0] io_dpath_pmp_7_cfg_a,
input io_dpath_pmp_7_cfg_x,
io_dpath_pmp_7_cfg_w,
io_dpath_pmp_7_cfg_r,
input [29:0] io_dpath_pmp_7_addr,
input [31:0] io_dpath_pmp_7_mask,
input [63:0] io_dpath_customCSRs_csrs_0_value
);
assign io_requestor_0_status_debug = io_dpath_status_debug;
assign io_requestor_0_pmp_0_cfg_l = io_dpath_pmp_0_cfg_l;
assign io_requestor_0_pmp_0_cfg_a = io_dpath_pmp_0_cfg_a;
assign io_requestor_0_pmp_0_cfg_w = io_dpath_pmp_0_cfg_w;
assign io_requestor_0_pmp_0_cfg_r = io_dpath_pmp_0_cfg_r;
assign io_requestor_0_pmp_0_addr = io_dpath_pmp_0_addr;
assign io_requestor_0_pmp_0_mask = io_dpath_pmp_0_mask;
assign io_requestor_0_pmp_1_cfg_l = io_dpath_pmp_1_cfg_l;
assign io_requestor_0_pmp_1_cfg_a = io_dpath_pmp_1_cfg_a;
assign io_requestor_0_pmp_1_cfg_w = io_dpath_pmp_1_cfg_w;
assign io_requestor_0_pmp_1_cfg_r = io_dpath_pmp_1_cfg_r;
assign io_requestor_0_pmp_1_addr = io_dpath_pmp_1_addr;
assign io_requestor_0_pmp_1_mask = io_dpath_pmp_1_mask;
assign io_requestor_0_pmp_2_cfg_l = io_dpath_pmp_2_cfg_l;
assign io_requestor_0_pmp_2_cfg_a = io_dpath_pmp_2_cfg_a;
assign io_requestor_0_pmp_2_cfg_w = io_dpath_pmp_2_cfg_w;
assign io_requestor_0_pmp_2_cfg_r = io_dpath_pmp_2_cfg_r;
assign io_requestor_0_pmp_2_addr = io_dpath_pmp_2_addr;
assign io_requestor_0_pmp_2_mask = io_dpath_pmp_2_mask;
assign io_requestor_0_pmp_3_cfg_l = io_dpath_pmp_3_cfg_l;
assign io_requestor_0_pmp_3_cfg_a = io_dpath_pmp_3_cfg_a;
assign io_requestor_0_pmp_3_cfg_w = io_dpath_pmp_3_cfg_w;
assign io_requestor_0_pmp_3_cfg_r = io_dpath_pmp_3_cfg_r;
assign io_requestor_0_pmp_3_addr = io_dpath_pmp_3_addr;
assign io_requestor_0_pmp_3_mask = io_dpath_pmp_3_mask;
assign io_requestor_0_pmp_4_cfg_l = io_dpath_pmp_4_cfg_l;
assign io_requestor_0_pmp_4_cfg_a = io_dpath_pmp_4_cfg_a;
assign io_requestor_0_pmp_4_cfg_w = io_dpath_pmp_4_cfg_w;
assign io_requestor_0_pmp_4_cfg_r = io_dpath_pmp_4_cfg_r;
assign io_requestor_0_pmp_4_addr = io_dpath_pmp_4_addr;
assign io_requestor_0_pmp_4_mask = io_dpath_pmp_4_mask;
assign io_requestor_0_pmp_5_cfg_l = io_dpath_pmp_5_cfg_l;
assign io_requestor_0_pmp_5_cfg_a = io_dpath_pmp_5_cfg_a;
assign io_requestor_0_pmp_5_cfg_w = io_dpath_pmp_5_cfg_w;
assign io_requestor_0_pmp_5_cfg_r = io_dpath_pmp_5_cfg_r;
assign io_requestor_0_pmp_5_addr = io_dpath_pmp_5_addr;
assign io_requestor_0_pmp_5_mask = io_dpath_pmp_5_mask;
assign io_requestor_0_pmp_6_cfg_l = io_dpath_pmp_6_cfg_l;
assign io_requestor_0_pmp_6_cfg_a = io_dpath_pmp_6_cfg_a;
assign io_requestor_0_pmp_6_cfg_w = io_dpath_pmp_6_cfg_w;
assign io_requestor_0_pmp_6_cfg_r = io_dpath_pmp_6_cfg_r;
assign io_requestor_0_pmp_6_addr = io_dpath_pmp_6_addr;
assign io_requestor_0_pmp_6_mask = io_dpath_pmp_6_mask;
assign io_requestor_0_pmp_7_cfg_l = io_dpath_pmp_7_cfg_l;
assign io_requestor_0_pmp_7_cfg_a = io_dpath_pmp_7_cfg_a;
assign io_requestor_0_pmp_7_cfg_w = io_dpath_pmp_7_cfg_w;
assign io_requestor_0_pmp_7_cfg_r = io_dpath_pmp_7_cfg_r;
assign io_requestor_0_pmp_7_addr = io_dpath_pmp_7_addr;
assign io_requestor_0_pmp_7_mask = io_dpath_pmp_7_mask;
assign io_requestor_1_status_debug = io_dpath_status_debug;
assign io_requestor_1_pmp_0_cfg_l = io_dpath_pmp_0_cfg_l;
assign io_requestor_1_pmp_0_cfg_a = io_dpath_pmp_0_cfg_a;
assign io_requestor_1_pmp_0_cfg_x = io_dpath_pmp_0_cfg_x;
assign io_requestor_1_pmp_0_addr = io_dpath_pmp_0_addr;
assign io_requestor_1_pmp_0_mask = io_dpath_pmp_0_mask;
assign io_requestor_1_pmp_1_cfg_l = io_dpath_pmp_1_cfg_l;
assign io_requestor_1_pmp_1_cfg_a = io_dpath_pmp_1_cfg_a;
assign io_requestor_1_pmp_1_cfg_x = io_dpath_pmp_1_cfg_x;
assign io_requestor_1_pmp_1_addr = io_dpath_pmp_1_addr;
assign io_requestor_1_pmp_1_mask = io_dpath_pmp_1_mask;
assign io_requestor_1_pmp_2_cfg_l = io_dpath_pmp_2_cfg_l;
assign io_requestor_1_pmp_2_cfg_a = io_dpath_pmp_2_cfg_a;
assign io_requestor_1_pmp_2_cfg_x = io_dpath_pmp_2_cfg_x;
assign io_requestor_1_pmp_2_addr = io_dpath_pmp_2_addr;
assign io_requestor_1_pmp_2_mask = io_dpath_pmp_2_mask;
assign io_requestor_1_pmp_3_cfg_l = io_dpath_pmp_3_cfg_l;
assign io_requestor_1_pmp_3_cfg_a = io_dpath_pmp_3_cfg_a;
assign io_requestor_1_pmp_3_cfg_x = io_dpath_pmp_3_cfg_x;
assign io_requestor_1_pmp_3_addr = io_dpath_pmp_3_addr;
assign io_requestor_1_pmp_3_mask = io_dpath_pmp_3_mask;
assign io_requestor_1_pmp_4_cfg_l = io_dpath_pmp_4_cfg_l;
assign io_requestor_1_pmp_4_cfg_a = io_dpath_pmp_4_cfg_a;
assign io_requestor_1_pmp_4_cfg_x = io_dpath_pmp_4_cfg_x;
assign io_requestor_1_pmp_4_addr = io_dpath_pmp_4_addr;
assign io_requestor_1_pmp_4_mask = io_dpath_pmp_4_mask;
assign io_requestor_1_pmp_5_cfg_l = io_dpath_pmp_5_cfg_l;
assign io_requestor_1_pmp_5_cfg_a = io_dpath_pmp_5_cfg_a;
assign io_requestor_1_pmp_5_cfg_x = io_dpath_pmp_5_cfg_x;
assign io_requestor_1_pmp_5_addr = io_dpath_pmp_5_addr;
assign io_requestor_1_pmp_5_mask = io_dpath_pmp_5_mask;
assign io_requestor_1_pmp_6_cfg_l = io_dpath_pmp_6_cfg_l;
assign io_requestor_1_pmp_6_cfg_a = io_dpath_pmp_6_cfg_a;
assign io_requestor_1_pmp_6_cfg_x = io_dpath_pmp_6_cfg_x;
assign io_requestor_1_pmp_6_addr = io_dpath_pmp_6_addr;
assign io_requestor_1_pmp_6_mask = io_dpath_pmp_6_mask;
assign io_requestor_1_pmp_7_cfg_l = io_dpath_pmp_7_cfg_l;
assign io_requestor_1_pmp_7_cfg_a = io_dpath_pmp_7_cfg_a;
assign io_requestor_1_pmp_7_cfg_x = io_dpath_pmp_7_cfg_x;
assign io_requestor_1_pmp_7_addr = io_dpath_pmp_7_addr;
assign io_requestor_1_pmp_7_mask = io_dpath_pmp_7_mask;
assign io_requestor_1_customCSRs_csrs_0_value = io_dpath_customCSRs_csrs_0_value;
endmodule
hardware/generated/genesys2-soc-verilog/PeripheryBus_cbus.sv
+1460
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hardware/generated/genesys2-soc-verilog/PeripheryBus_pbus.sv
+1160
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hardware/generated/genesys2-soc-verilog/PlusArgTimeout.sv
+36
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@@ -0,0 +1,36 @@
// Generated by CIRCT firtool-1.151.0
// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifndef PRINTF_COND_
`ifdef PRINTF_COND
`define PRINTF_COND_ (`PRINTF_COND)
`else // PRINTF_COND
`define PRINTF_COND_ 1
`endif // PRINTF_COND
`endif // not def PRINTF_COND_
module PlusArgTimeout(
input clock,
reset,
input [31:0] io_count
);
wire [31:0] _plusarg_reader_out;
wire _GEN = (|_plusarg_reader_out) & ~reset;
`ifndef SYNTHESIS
always @(posedge clock) begin
if ((`PRINTF_COND_) & _GEN & io_count >= _plusarg_reader_out)
$fwrite(32'h80000002,
"Assertion failed: Timeout exceeded: Kill the emulation after INT rdtime cycles. Off if 0.\n at PlusArg.scala:64 assert (io.count < max, s\"Timeout exceeded: $docstring\")\n");
end // always @(posedge)
`endif // not def SYNTHESIS
always @(posedge clock) begin
end // always @(posedge)
plusarg_reader #(
.DEFAULT(0),
.FORMAT("max_core_cycles=%d"),
.WIDTH(32)
) plusarg_reader (
.out (_plusarg_reader_out)
);
endmodule
hardware/generated/genesys2-soc-verilog/Queue1_RegMapperInput_i23_m8.sv
+50
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@@ -0,0 +1,50 @@
// Generated by CIRCT firtool-1.151.0
module Queue1_RegMapperInput_i23_m8(
input clock,
reset,
output io_enq_ready,
input io_enq_valid,
io_enq_bits_read,
input [22:0] io_enq_bits_index,
input [63:0] io_enq_bits_data,
input [7:0] io_enq_bits_mask,
input [5:0] io_enq_bits_extra_tlrr_extra_source,
input [1:0] io_enq_bits_extra_tlrr_extra_size,
input io_deq_ready,
output io_deq_valid,
io_deq_bits_read,
output [22:0] io_deq_bits_index,
output [63:0] io_deq_bits_data,
output [7:0] io_deq_bits_mask,
output [5:0] io_deq_bits_extra_tlrr_extra_source,
output [1:0] io_deq_bits_extra_tlrr_extra_size
);
reg [103:0] ram;
reg maybe_full;
always @(posedge clock) begin
automatic logic do_enq;
do_enq = ~maybe_full & io_enq_valid;
if (reset)
maybe_full <= 1'h0;
else if (do_enq != (io_deq_ready & maybe_full))
maybe_full <= do_enq;
if (do_enq)
ram <=
{io_enq_bits_read,
io_enq_bits_index,
io_enq_bits_data,
io_enq_bits_mask,
io_enq_bits_extra_tlrr_extra_source,
io_enq_bits_extra_tlrr_extra_size};
end // always @(posedge)
assign io_enq_ready = ~maybe_full;
assign io_deq_valid = maybe_full;
assign io_deq_bits_read = ram[103];
assign io_deq_bits_index = ram[102:80];
assign io_deq_bits_data = ram[79:16];
assign io_deq_bits_mask = ram[15:8];
assign io_deq_bits_extra_tlrr_extra_source = ram[7:2];
assign io_deq_bits_extra_tlrr_extra_size = ram[1:0];
endmodule
hardware/generated/genesys2-soc-verilog/Queue1_RegMapperInput_i9_m8.sv
+50
View File
@@ -0,0 +1,50 @@
// Generated by CIRCT firtool-1.151.0
module Queue1_RegMapperInput_i9_m8(
input clock,
reset,
output io_enq_ready,
input io_enq_valid,
io_enq_bits_read,
input [8:0] io_enq_bits_index,
input [63:0] io_enq_bits_data,
input [7:0] io_enq_bits_mask,
input [5:0] io_enq_bits_extra_tlrr_extra_source,
input [1:0] io_enq_bits_extra_tlrr_extra_size,
input io_deq_ready,
output io_deq_valid,
io_deq_bits_read,
output [8:0] io_deq_bits_index,
output [63:0] io_deq_bits_data,
output [7:0] io_deq_bits_mask,
output [5:0] io_deq_bits_extra_tlrr_extra_source,
output [1:0] io_deq_bits_extra_tlrr_extra_size
);
reg [89:0] ram;
reg maybe_full;
always @(posedge clock) begin
automatic logic do_enq;
do_enq = ~maybe_full & io_enq_valid;
if (reset)
maybe_full <= 1'h0;
else if (do_enq != (io_deq_ready & maybe_full))
maybe_full <= do_enq;
if (do_enq)
ram <=
{io_enq_bits_read,
io_enq_bits_index,
io_enq_bits_data,
io_enq_bits_mask,
io_enq_bits_extra_tlrr_extra_source,
io_enq_bits_extra_tlrr_extra_size};
end // always @(posedge)
assign io_enq_ready = ~maybe_full;
assign io_deq_valid = maybe_full;
assign io_deq_bits_read = ram[89];
assign io_deq_bits_index = ram[88:80];
assign io_deq_bits_data = ram[79:16];
assign io_deq_bits_mask = ram[15:8];
assign io_deq_bits_extra_tlrr_extra_source = ram[7:2];
assign io_deq_bits_extra_tlrr_extra_size = ram[1:0];
endmodule
hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv
+48
View File
@@ -0,0 +1,48 @@
// Generated by CIRCT firtool-1.151.0
module Queue1_TLBundleA_a14d64s2k1z4u(
input clock,
reset,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
io_enq_bits_param,
input [3:0] io_enq_bits_size,
input [1:0] io_enq_bits_source,
input [13:0] io_enq_bits_address,
input [7:0] io_enq_bits_mask,
input [63:0] io_enq_bits_data,
input io_enq_bits_corrupt,
io_deq_ready,
output io_deq_valid,
output [2:0] io_deq_bits_opcode,
output [3:0] io_deq_bits_size,
output [1:0] io_deq_bits_source
);
reg [98:0] ram;
reg maybe_full;
always @(posedge clock) begin
automatic logic do_enq;
do_enq = ~maybe_full & io_enq_valid;
if (reset)
maybe_full <= 1'h0;
else if (do_enq != (io_deq_ready & maybe_full))
maybe_full <= do_enq;
if (do_enq)
ram <=
{io_enq_bits_opcode,
io_enq_bits_param,
io_enq_bits_size,
io_enq_bits_source,
io_enq_bits_address,
io_enq_bits_mask,
io_enq_bits_data,
io_enq_bits_corrupt};
end // always @(posedge)
assign io_enq_ready = ~maybe_full;
assign io_deq_valid = maybe_full;
assign io_deq_bits_opcode = ram[98:96];
assign io_deq_bits_size = ram[92:89];
assign io_deq_bits_source = ram[88:87];
endmodule

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