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onur
2026-08-06 22:14:52 +03:00
parent 847523078b
commit b4920d31e3
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hardware/generated/genesys2-soc-verilog/BreakpointUnit.sv
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// Generated by CIRCT firtool-1.151.0
module BreakpointUnit(
input io_status_debug,
io_bp_0_control_action,
input [1:0] io_bp_0_control_tmatch,
input io_bp_0_control_x,
io_bp_0_control_w,
io_bp_0_control_r,
input [32:0] io_bp_0_address,
io_pc,
io_ea,
output io_xcpt_if,
io_xcpt_ld,
io_xcpt_st,
io_debug_if,
io_debug_ld,
io_debug_st
);
wire _w_T_2 = io_ea >= io_bp_0_address;
wire [32:0] _w_T_5 = ~io_ea;
wire _r_T_8 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];
wire _r_T_10 = _r_T_8 & io_bp_0_address[1];
wire [32:0] _x_T_15 = ~io_bp_0_address;
wire _r_T_18 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];
wire _r_T_20 = _r_T_18 & io_bp_0_address[1];
wire r =
~io_status_debug & io_bp_0_control_r
& (io_bp_0_control_tmatch[1]
? _w_T_2 ^ io_bp_0_control_tmatch[0]
: {_w_T_5[32:4],
_w_T_5[3:0]
| {_r_T_10 & io_bp_0_address[2],
_r_T_10,
_r_T_8,
io_bp_0_control_tmatch[0]}} == {_x_T_15[32:4],
_x_T_15[3:0]
| {_r_T_20 & io_bp_0_address[2],
_r_T_20,
_r_T_18,
io_bp_0_control_tmatch[0]}});
wire _w_T_8 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];
wire _w_T_10 = _w_T_8 & io_bp_0_address[1];
wire _w_T_18 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];
wire _w_T_20 = _w_T_18 & io_bp_0_address[1];
wire w =
~io_status_debug & io_bp_0_control_w
& (io_bp_0_control_tmatch[1]
? _w_T_2 ^ io_bp_0_control_tmatch[0]
: {_w_T_5[32:4],
_w_T_5[3:0]
| {_w_T_10 & io_bp_0_address[2],
_w_T_10,
_w_T_8,
io_bp_0_control_tmatch[0]}} == {_x_T_15[32:4],
_x_T_15[3:0]
| {_w_T_20 & io_bp_0_address[2],
_w_T_20,
_w_T_18,
io_bp_0_control_tmatch[0]}});
wire [32:0] _x_T_5 = ~io_pc;
wire _x_T_8 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];
wire _x_T_10 = _x_T_8 & io_bp_0_address[1];
wire _x_T_18 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];
wire _x_T_20 = _x_T_18 & io_bp_0_address[1];
wire x =
~io_status_debug & io_bp_0_control_x
& (io_bp_0_control_tmatch[1]
? io_pc >= io_bp_0_address ^ io_bp_0_control_tmatch[0]
: {_x_T_5[32:4],
_x_T_5[3:0]
| {_x_T_10 & io_bp_0_address[2],
_x_T_10,
_x_T_8,
io_bp_0_control_tmatch[0]}} == {_x_T_15[32:4],
_x_T_15[3:0]
| {_x_T_20 & io_bp_0_address[2],
_x_T_20,
_x_T_18,
io_bp_0_control_tmatch[0]}});
assign io_xcpt_if = x & ~io_bp_0_control_action;
assign io_xcpt_ld = r & ~io_bp_0_control_action;
assign io_xcpt_st = w & ~io_bp_0_control_action;
assign io_debug_if = x & io_bp_0_control_action;
assign io_debug_ld = r & io_bp_0_control_action;
assign io_debug_st = w & io_bp_0_control_action;
endmodule