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onur
2026-08-06 22:14:52 +03:00
parent 847523078b
commit b4920d31e3
288 changed files with 214687 additions and 18389 deletions
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hardware/generated/genesys2-soc-verilog/DCacheDataArray.sv
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// Generated by CIRCT firtool-1.151.0
module DCacheDataArray(
input clock,
io_req_valid,
input [19:0] io_req_bits_addr,
input io_req_bits_write,
input [63:0] io_req_bits_wdata,
input [7:0] io_req_bits_eccMask,
output [63:0] io_resp_0
);
wire rockettile_dcache_data_arrays_0_rdata_data_en;
wire rockettile_dcache_data_arrays_0_rdata_MPORT_en;
assign rockettile_dcache_data_arrays_0_rdata_MPORT_en =
io_req_valid & io_req_bits_write;
assign rockettile_dcache_data_arrays_0_rdata_data_en =
io_req_valid & ~io_req_bits_write;
rockettile_dcache_data_arrays_0_131072x64 rockettile_dcache_data_arrays_0_ext (
.RW0_addr (io_req_bits_addr[19:3]),
.RW0_en
(rockettile_dcache_data_arrays_0_rdata_data_en
| rockettile_dcache_data_arrays_0_rdata_MPORT_en),
.RW0_clk (clock),
.RW0_wmode (io_req_bits_write),
.RW0_wdata (io_req_bits_wdata),
.RW0_rdata (io_resp_0),
.RW0_wmask (io_req_bits_eccMask)
);
endmodule