max2771 spi liens has been added.
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// Generated by CIRCT firtool-1.151.0
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module MulAddRecFNToRaw_postMul(
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input io_fromPreMul_isSigNaNAny,
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io_fromPreMul_isNaNAOrB,
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io_fromPreMul_isInfA,
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io_fromPreMul_isZeroA,
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io_fromPreMul_isInfB,
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io_fromPreMul_isZeroB,
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io_fromPreMul_signProd,
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io_fromPreMul_isNaNC,
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io_fromPreMul_isInfC,
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io_fromPreMul_isZeroC,
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input [9:0] io_fromPreMul_sExpSum,
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input io_fromPreMul_doSubMags,
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io_fromPreMul_CIsDominant,
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input [4:0] io_fromPreMul_CDom_CAlignDist,
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input [25:0] io_fromPreMul_highAlignedSigC,
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input io_fromPreMul_bit0AlignedSigC,
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input [48:0] io_mulAddResult,
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input [2:0] io_roundingMode,
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output io_invalidExc,
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io_rawOut_isNaN,
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io_rawOut_isInf,
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io_rawOut_isZero,
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io_rawOut_sign,
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output [9:0] io_rawOut_sExp,
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output [26:0] io_rawOut_sig
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);
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wire roundingMode_min = io_roundingMode == 3'h2;
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wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags;
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wire [25:0] _sigSum_T_3 =
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io_mulAddResult[48]
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? io_fromPreMul_highAlignedSigC + 26'h1
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: io_fromPreMul_highAlignedSigC;
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wire [49:0] CDom_absSigSum =
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io_fromPreMul_doSubMags
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? ~{_sigSum_T_3, io_mulAddResult[47:24]}
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: {1'h0,
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io_fromPreMul_highAlignedSigC[25:24],
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_sigSum_T_3[23:0],
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io_mulAddResult[47:25]};
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wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist;
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wire [8:0] CDom_reduced4SigExtra_shift =
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$unsigned($signed(9'sh100 >>> ~(io_fromPreMul_CDom_CAlignDist[4:2])));
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wire [50:0] notCDom_absSigSum =
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_sigSum_T_3[2]
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? ~{_sigSum_T_3[1:0], io_mulAddResult[47:0], io_fromPreMul_bit0AlignedSigC}
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: {_sigSum_T_3[1:0], io_mulAddResult[47:0], io_fromPreMul_bit0AlignedSigC}
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+ {50'h0, io_fromPreMul_doSubMags};
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wire notCDom_reduced2AbsSigSum_reducedVec_1 = |(notCDom_absSigSum[3:2]);
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wire notCDom_reduced2AbsSigSum_reducedVec_2 = |(notCDom_absSigSum[5:4]);
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wire notCDom_reduced2AbsSigSum_reducedVec_3 = |(notCDom_absSigSum[7:6]);
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wire notCDom_reduced2AbsSigSum_reducedVec_4 = |(notCDom_absSigSum[9:8]);
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wire notCDom_reduced2AbsSigSum_reducedVec_5 = |(notCDom_absSigSum[11:10]);
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wire notCDom_reduced2AbsSigSum_reducedVec_6 = |(notCDom_absSigSum[13:12]);
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wire notCDom_reduced2AbsSigSum_reducedVec_7 = |(notCDom_absSigSum[15:14]);
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wire notCDom_reduced2AbsSigSum_reducedVec_8 = |(notCDom_absSigSum[17:16]);
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wire notCDom_reduced2AbsSigSum_reducedVec_9 = |(notCDom_absSigSum[19:18]);
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wire notCDom_reduced2AbsSigSum_reducedVec_10 = |(notCDom_absSigSum[21:20]);
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wire notCDom_reduced2AbsSigSum_reducedVec_11 = |(notCDom_absSigSum[23:22]);
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wire [4:0] notCDom_normDistReduced2 =
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notCDom_absSigSum[50]
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? 5'h0
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: (|(notCDom_absSigSum[49:48]))
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? 5'h1
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: (|(notCDom_absSigSum[47:46]))
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? 5'h2
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: (|(notCDom_absSigSum[45:44]))
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? 5'h3
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: (|(notCDom_absSigSum[43:42]))
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? 5'h4
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: (|(notCDom_absSigSum[41:40]))
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? 5'h5
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: (|(notCDom_absSigSum[39:38]))
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? 5'h6
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: (|(notCDom_absSigSum[37:36]))
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? 5'h7
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: (|(notCDom_absSigSum[35:34]))
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? 5'h8
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: (|(notCDom_absSigSum[33:32]))
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? 5'h9
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: (|(notCDom_absSigSum[31:30]))
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? 5'hA
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: (|(notCDom_absSigSum[29:28]))
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? 5'hB
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: (|(notCDom_absSigSum[27:26]))
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? 5'hC
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: (|(notCDom_absSigSum[25:24]))
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? 5'hD
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: notCDom_reduced2AbsSigSum_reducedVec_11
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? 5'hE
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: notCDom_reduced2AbsSigSum_reducedVec_10
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? 5'hF
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: notCDom_reduced2AbsSigSum_reducedVec_9
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? 5'h10
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: notCDom_reduced2AbsSigSum_reducedVec_8
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? 5'h11
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: notCDom_reduced2AbsSigSum_reducedVec_7
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? 5'h12
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: notCDom_reduced2AbsSigSum_reducedVec_6
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? 5'h13
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: notCDom_reduced2AbsSigSum_reducedVec_5
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? 5'h14
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: notCDom_reduced2AbsSigSum_reducedVec_4
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? 5'h15
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: notCDom_reduced2AbsSigSum_reducedVec_3
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? 5'h16
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: notCDom_reduced2AbsSigSum_reducedVec_2
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? 5'h17
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: {4'hC,
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~notCDom_reduced2AbsSigSum_reducedVec_1};
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wire [113:0] _notCDom_mainSig_T =
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{63'h0, notCDom_absSigSum} << {108'h0, notCDom_normDistReduced2, 1'h0};
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wire [16:0] notCDom_reduced4SigExtra_shift =
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$unsigned($signed(17'sh10000 >>> ~(notCDom_normDistReduced2[4:1])));
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wire notCDom_completeCancellation = _notCDom_mainSig_T[51:50] == 2'h0;
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wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB;
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wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC;
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wire notNaN_addZeros =
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(io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC;
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assign io_invalidExc =
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io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB
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| io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB
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& notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags;
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assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC;
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assign io_rawOut_isInf = notNaN_isInfOut;
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assign io_rawOut_isZero =
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notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation;
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assign io_rawOut_sign =
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notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC
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| notNaN_addZeros & io_roundingMode != 3'h2 & io_fromPreMul_signProd & opSignC
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| notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC)
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| ~notNaN_isInfOut & ~notNaN_addZeros
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& (io_fromPreMul_CIsDominant
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? opSignC
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: notCDom_completeCancellation
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? roundingMode_min
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: io_fromPreMul_signProd ^ _sigSum_T_3[2]);
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assign io_rawOut_sExp =
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io_fromPreMul_CIsDominant
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? io_fromPreMul_sExpSum - {9'h0, io_fromPreMul_doSubMags}
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: io_fromPreMul_sExpSum - {4'h0, notCDom_normDistReduced2, 1'h0};
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assign io_rawOut_sig =
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io_fromPreMul_CIsDominant
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? {_CDom_mainSig_T[49:24],
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(|{_CDom_mainSig_T[23:21],
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{|(CDom_absSigSum[20:17]),
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|(CDom_absSigSum[16:13]),
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|(CDom_absSigSum[12:9]),
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|(CDom_absSigSum[8:5]),
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|(CDom_absSigSum[4:1]),
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CDom_absSigSum[0]}
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& {CDom_reduced4SigExtra_shift[1],
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CDom_reduced4SigExtra_shift[2],
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CDom_reduced4SigExtra_shift[3],
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CDom_reduced4SigExtra_shift[4],
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CDom_reduced4SigExtra_shift[5],
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CDom_reduced4SigExtra_shift[6]}})
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| (io_fromPreMul_doSubMags
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? io_mulAddResult[23:0] != 24'hFFFFFF
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: (|(io_mulAddResult[24:0])))}
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: {_notCDom_mainSig_T[51:26],
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|{_notCDom_mainSig_T[25:23],
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{|{notCDom_reduced2AbsSigSum_reducedVec_11,
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notCDom_reduced2AbsSigSum_reducedVec_10},
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|{notCDom_reduced2AbsSigSum_reducedVec_9,
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notCDom_reduced2AbsSigSum_reducedVec_8},
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|{notCDom_reduced2AbsSigSum_reducedVec_7,
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notCDom_reduced2AbsSigSum_reducedVec_6},
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|{notCDom_reduced2AbsSigSum_reducedVec_5,
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notCDom_reduced2AbsSigSum_reducedVec_4},
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|{notCDom_reduced2AbsSigSum_reducedVec_3,
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notCDom_reduced2AbsSigSum_reducedVec_2},
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|{notCDom_reduced2AbsSigSum_reducedVec_1, |(notCDom_absSigSum[1:0])}}
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& {notCDom_reduced4SigExtra_shift[1],
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notCDom_reduced4SigExtra_shift[2],
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notCDom_reduced4SigExtra_shift[3],
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notCDom_reduced4SigExtra_shift[4],
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notCDom_reduced4SigExtra_shift[5],
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notCDom_reduced4SigExtra_shift[6]}}};
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endmodule
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