max2771 spi liens has been added.

2026-08-06 22:14:52 +03:00
parent 847523078b
commit b4920d31e3
288 changed files with 214687 additions and 18389 deletions
@@ -0,0 +1,121 @@
+// Generated by CIRCT firtool-1.151.0
+module TLDebugModuleOuter(
+  input         clock,
+                reset,
+  output        auto_dmi_in_a_ready,
+  input         auto_dmi_in_a_valid,
+  input  [2:0]  auto_dmi_in_a_bits_opcode,
+  input  [6:0]  auto_dmi_in_a_bits_address,
+  input  [31:0] auto_dmi_in_a_bits_data,
+  input         auto_dmi_in_d_ready,
+  output        auto_dmi_in_d_valid,
+  output [31:0] auto_dmi_in_d_bits_data,
+  output        auto_int_out_0,
+                io_ctrl_ndreset,
+                io_ctrl_dmactive,
+  input         io_ctrl_dmactiveAck,
+                io_innerCtrl_ready,
+  output        io_innerCtrl_valid,
+                io_innerCtrl_bits_resumereq,
+  output [9:0]  io_innerCtrl_bits_hartsel,
+  output        io_innerCtrl_bits_ackhavereset,
+                io_innerCtrl_bits_hrmask_0,
+  input         io_hgDebugInt_0
+);
+
+  wire resumereqWrEn;
+  wire DMCONTROLWrData_setresethaltreq;
+  wire DMCONTROLWrData_clrresethaltreq;
+  reg  DMCONTROLReg_haltreq;
+  reg  DMCONTROLReg_ndmreset;
+  reg  DMCONTROLReg_dmactive;
+  reg  hrmaskReg_0;
+  wire hrmask_0 =
+    ~(~DMCONTROLReg_dmactive | resumereqWrEn & DMCONTROLWrData_clrresethaltreq)
+    & (resumereqWrEn & DMCONTROLWrData_setresethaltreq | hrmaskReg_0);
+  wire _out_out_bits_data_WIRE_1 =
+    {auto_dmi_in_a_bits_address[4], auto_dmi_in_a_bits_address[2]} == 2'h0;
+  assign DMCONTROLWrData_clrresethaltreq = auto_dmi_in_a_bits_data[2];
+  assign DMCONTROLWrData_setresethaltreq = auto_dmi_in_a_bits_data[3];
+  assign resumereqWrEn =
+    auto_dmi_in_a_valid & auto_dmi_in_d_ready & auto_dmi_in_a_bits_opcode != 3'h4
+    & ~(auto_dmi_in_a_bits_address[3]) & _out_out_bits_data_WIRE_1;
+  reg  debugIntRegs_0;
+  reg  innerCtrlValidReg;
+  reg  innerCtrlResumeReqReg;
+  reg  innerCtrlAckHaveResetReg;
+  wire io_innerCtrl_valid_0 = resumereqWrEn | innerCtrlValidReg;
+  wire io_innerCtrl_bits_resumereq_0 =
+    resumereqWrEn & auto_dmi_in_a_bits_data[30] | innerCtrlResumeReqReg;
+  wire io_innerCtrl_bits_ackhavereset_0 =
+    resumereqWrEn & auto_dmi_in_a_bits_data[28] | innerCtrlAckHaveResetReg;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      DMCONTROLReg_haltreq <= 1'h0;
+      DMCONTROLReg_ndmreset <= 1'h0;
+      DMCONTROLReg_dmactive <= 1'h0;
+      hrmaskReg_0 <= 1'h0;
+      debugIntRegs_0 <= 1'h0;
+      innerCtrlValidReg <= 1'h0;
+      innerCtrlResumeReqReg <= 1'h0;
+      innerCtrlAckHaveResetReg <= 1'h0;
+    end
+    else begin
+      DMCONTROLReg_haltreq <=
+        DMCONTROLReg_dmactive
+        & (resumereqWrEn ? auto_dmi_in_a_bits_data[31] : DMCONTROLReg_haltreq);
+      DMCONTROLReg_ndmreset <=
+        DMCONTROLReg_dmactive
+        & (resumereqWrEn ? auto_dmi_in_a_bits_data[1] : DMCONTROLReg_ndmreset);
+      if (resumereqWrEn)
+        DMCONTROLReg_dmactive <= auto_dmi_in_a_bits_data[0];
+      hrmaskReg_0 <= hrmask_0;
+      debugIntRegs_0 <=
+        DMCONTROLReg_dmactive
+        & (resumereqWrEn ? auto_dmi_in_a_bits_data[31] : debugIntRegs_0);
+      innerCtrlValidReg <= io_innerCtrl_valid_0 & ~io_innerCtrl_ready;
+      innerCtrlResumeReqReg <= io_innerCtrl_bits_resumereq_0 & ~io_innerCtrl_ready;
+      innerCtrlAckHaveResetReg <= io_innerCtrl_bits_ackhavereset_0 & ~io_innerCtrl_ready;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    initial begin
+      if (reset) begin
+        DMCONTROLReg_haltreq = 1'h0;
+        DMCONTROLReg_ndmreset = 1'h0;
+        DMCONTROLReg_dmactive = 1'h0;
+        hrmaskReg_0 = 1'h0;
+        debugIntRegs_0 = 1'h0;
+        innerCtrlValidReg = 1'h0;
+        innerCtrlResumeReqReg = 1'h0;
+        innerCtrlAckHaveResetReg = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign auto_dmi_in_a_ready = auto_dmi_in_d_ready;
+  assign auto_dmi_in_d_valid = auto_dmi_in_a_valid;
+  assign auto_dmi_in_d_bits_data =
+    _out_out_bits_data_WIRE_1
+      ? (auto_dmi_in_a_bits_address[3]
+           ? 32'h112380
+           : {DMCONTROLReg_haltreq,
+              29'h0,
+              DMCONTROLReg_ndmreset,
+              DMCONTROLReg_dmactive & io_ctrl_dmactiveAck})
+      : 32'h0;
+  assign auto_int_out_0 = debugIntRegs_0 | io_hgDebugInt_0;
+  assign io_ctrl_ndreset = DMCONTROLReg_ndmreset;
+  assign io_ctrl_dmactive = DMCONTROLReg_dmactive;
+  assign io_innerCtrl_valid = io_innerCtrl_valid_0;
+  assign io_innerCtrl_bits_resumereq = io_innerCtrl_bits_resumereq_0;
+  assign io_innerCtrl_bits_hartsel = 10'h0;
+  assign io_innerCtrl_bits_ackhavereset = io_innerCtrl_bits_ackhavereset_0;
+  assign io_innerCtrl_bits_hrmask_0 = hrmask_0;
+endmodule
+