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max2771 spi liens has been added.

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onur
2026-08-06 22:14:52 +03:00
parent 847523078b
commit b4920d31e3
288 changed files with 214687 additions and 18389 deletions
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targets/fpga/genesys2/Makefile
+1
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@@ -233,6 +233,7 @@ chisel: software
"$(JAVA_HOME)/bin/java" \
-DROCKET_DTIM_BASE="$(DTIM_BASE)" \
-DROCKET_DTIM_SIZE="$(DTIM_SIZE)" \
-DROCKET_SOC_CLOCK_HZ="$(SOC_CLK_HZ)" \
-jar out/rocketchip/6.7.0/assembly.dest/out.jar \
--dir "$(FIRRTL_DIR)" \
--top freechips.rocketchip.fpga.VCU118RocketSystem \
targets/fpga/genesys2/README.md
+27
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@@ -127,6 +127,33 @@ pmod_spi_dq[3] AG30 JC8
Pin constraintleri `hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc`
dosyasindadir ve Vivado akisi tarafindan her RF modunda okunur.
MAX2771 icin generic PMOD SPI'dan bagimsiz, 48-clock/tek-SDATA hatli bir IP
`0x10016000` adresindedir. 50 MHz Genesys2 fabric saatinden yedi fabric cycle
yarim periyot ile 3.571 MHz SCLK uretilir; MAX2771'in 4 MHz ust siniri ve
250 ns minimum periyodu korunur.
```text
port FPGA pin PMOD pin yon
max2771_spi_sclk V30 JB2 output
max2771_spi_csn V25 JB3 output
max2771_spi_sdata W26 JB4 bidirectional
```
`SDATA` read header'indaki R/W bitinden sonraki falling edge'de input/high-Z
olur; uc turnaround clock ve 32 read-data clock'u boyunca FPGA bu tek hatti
okur. Constraintler
`hardware/fpga/genesys2/constraints/genesys2_max2771_spi.xdc` dosyasindadir.
EV kit uzerindeki MAX32625 PICO ayni hatlara baglidir; FPGA baglanmadan once
PICO SPI pinleri high-Z yapilmali veya controller fiziksel olarak ayrilmali ve
EV kit GUI ayni anda calistirilmamalidir.
Register test uygulamasi tum data-sheet default register tablosunu yazar ve
geri okuyup dogrular:
```bash
make -C targets/fpga/genesys2 debug-load APP=max2771_spi_test
```
Sensorden gelen external interrupt hatti SPI'dan bagimsizdir. Guncel pin
planinda `pmod_irq` PMOD JB pin 1'e cikar ve PLIC'te `BSP_PMOD_IRQ` (`11`)
ID'siyle gorunur. Eski `JC9/AK30` eslemesi 2026-07-14'te `JB1/V29` olarak
targets/fpga/genesys2/flow/vivado/scripts/build.tcl
+3
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@@ -120,6 +120,7 @@ read_verilog -sv $gps_files
puts "Reading Genesys2 shell RTL..."
set shell_files [list \
[file join $hardware_dir ip max2771_spi rtl max2771_spi_engine.sv] \
[file join $hardware_dir fpga vcu118 rtl axi4_ram_64.sv] \
[file join $hardware_dir fpga vcu118 rtl axi4_slave_tieoff_64.sv] \
[file join $hardware_dir fpga genesys2 rtl rocket_bscan_dmi_tunnel.sv] \
@@ -140,6 +141,8 @@ puts "Reading constraints..."
read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_rocket.xdc]
puts "Reading Genesys2 PMOD SPI constraints..."
read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_spi.xdc]
puts "Reading Genesys2 MAX2771 SPI constraints..."
read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_max2771_spi.xdc]
puts "Reading Genesys2 PMOD sensor IRQ constraints..."
read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_irq.xdc]
puts "Reading Genesys2 PMOD PPS constraints..."
targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
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targets/fpga/genesys2/out/build/checkpoints/post_opt.dcp
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targets/fpga/genesys2/out/build/checkpoints/post_phys_opt.dcp
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targets/fpga/genesys2/out/build/checkpoints/post_place.dcp
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targets/fpga/genesys2/out/build/checkpoints/post_route.dcp
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targets/fpga/genesys2/out/build/checkpoints/post_synth.dcp
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targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv
+17 -2
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@@ -355,7 +355,9 @@ module genesys2_rocket_top (
rocket_bscan_dmi_tunnel u_rocket_bscan_dmi_tunnel (
.tck(bscan_tck),
.reset(fabric_reset | bscan_reset),
// Keep the transport TAP alive while the fabric is in reset. Otherwise
// OpenOCD cannot examine the target to diagnose a PLL/reset-ready failure.
.reset(bscan_reset),
.bscan_capture(bscan_capture),
.bscan_sel(bscan_sel),
.bscan_shift(bscan_shift),
@@ -407,6 +409,19 @@ module genesys2_rocket_top (
assign pmod_spi_dq[2] = pmod_spi_dq_oe[2] ? pmod_spi_dq_o[2] : 1'bz;
assign pmod_spi_dq[3] = pmod_spi_dq_oe[3] ? pmod_spi_dq_o[3] : 1'bz;
// JB1 is asynchronous to the 50 MHz Rocket fabric. Keep this as three
// physical flip-flops: ASYNC_REG guides placement for metastability MTBF,
// and SHREG_EXTRACT prevents Vivado from collapsing stages into an SRL.
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
reg [2:0] pmod_irq_sync = 3'b000;
always @(posedge fabric_clk) begin
if (fabric_reset) begin
pmod_irq_sync <= 3'b000;
end else begin
pmod_irq_sync <= {pmod_irq_sync[1:0], pmod_irq};
end
end
assign io_aggregator_3_clock = fabric_clk;
assign io_aggregator_3_reset = soc_reset;
assign io_aggregator_2_clock = fabric_clk;
@@ -477,7 +492,7 @@ module genesys2_rocket_top (
.pmod_spi_dq_i(pmod_spi_dq_i),
.pmod_spi_dq_o(pmod_spi_dq_o),
.pmod_spi_dq_oe(pmod_spi_dq_oe),
.pmod_irq(pmod_irq),
.pmod_irq(pmod_irq_sync[2]),
.gps_acq_clk(gps_acq_clk),
.gps_trck_clk(gps_trck_clk),
.gps_rf_clk(gps_rf_clk),
targets/fpga/genesys2/out/logs/build_bitstream.jou
+17 -17
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@@ -3,22 +3,22 @@
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
# Start of session at: Sat Jul 11 19:52:11 2026
# Process ID : 310847
# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log
# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou
# Running On : onur
# Start of session at: Thu Aug 6 21:27:26 2026
# Process ID : 3049064
# Current directory : /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/logs
# Command line : vivado -mode batch -log /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/logs/build_bitstream.log -journal /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/logs/build_bitstream.jou -source /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
# Log file : /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/logs/build_bitstream.log
# Journal file : /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/logs/build_bitstream.jou
# Running On : ankalab04
# Platform : Ubuntu
# Operating System : Ubuntu 22.04.5 LTS
# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
# CPU Frequency : 4199.924 MHz
# CPU Physical cores : 12
# CPU Logical cores : 12
# Host memory : 22112 MB
# Swap memory : 2147 MB
# Total Virtual : 24260 MB
# Available Virtual : 21498 MB
# Operating System : Ubuntu 24.04.4 LTS
# Processor Detail : AMD Ryzen 9 9950X 16-Core Processor
# CPU Frequency : 3697.138 MHz
# CPU Physical cores : 16
# CPU Logical cores : 32
# Host memory : 64914 MB
# Swap memory : 8589 MB
# Total Virtual : 73504 MB
# Available Virtual : 44045 MB
#-----------------------------------------------------------
source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
source /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
targets/fpga/genesys2/out/logs/build_bitstream.log
+1529 -1548
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targets/fpga/genesys2/out/logs/build_bitstream_39651.backup.jou → targets/fpga/genesys2/out/logs/build_bitstream_310847.backup.jou
+3 -3
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@@ -3,8 +3,8 @@
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
# Start of session at: Sat Jul 11 17:17:03 2026
# Process ID : 39651
# Start of session at: Sat Jul 11 19:52:11 2026
# Process ID : 310847
# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/build_bitstream.log
@@ -19,6 +19,6 @@
# Host memory : 22112 MB
# Swap memory : 2147 MB
# Total Virtual : 24260 MB
# Available Virtual : 21714 MB
# Available Virtual : 21498 MB
#-----------------------------------------------------------
source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
targets/fpga/genesys2/out/reports/route_drc.rpt
+251 -161
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targets/fpga/genesys2/out/reports/route_power.rpt
+30 -30
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@@ -1,9 +1,9 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
| Date : Sat Jul 11 20:02:44 2026
| Host : onur running 64-bit Ubuntu 22.04.5 LTS
| Command : report_power -file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/reports/route_power.rpt
| Date : Thu Aug 6 21:33:45 2026
| Host : ankalab04 running 64-bit Ubuntu 24.04.4 LTS
| Command : report_power -file /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/reports/route_power.rpt
| Design : genesys2_rocket_top
| Device : xc7k325tffg900-2
| Design State : routed
@@ -30,14 +30,14 @@ Table of Contents
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 1.959 |
| Total On-Chip Power (W) | 2.022 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 1.763 |
| Dynamic (W) | 1.825 |
| Device Static (W) | 0.197 |
| Effective TJA (C/W) | 1.8 |
| Max Ambient (C) | 81.5 |
| Junction Temperature (C) | 28.5 |
| Max Ambient (C) | 81.4 |
| Junction Temperature (C) | 28.6 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
@@ -52,23 +52,23 @@ Table of Contents
+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks | 0.138 | 11 | --- | --- |
| Slice Logic | 0.265 | 125644 | --- | --- |
| LUT as Logic | 0.225 | 60358 | 203800 | 29.62 |
| CARRY4 | 0.030 | 6054 | 50950 | 11.88 |
| Register | 0.009 | 41422 | 407600 | 10.16 |
| LUT as Distributed RAM | <0.001 | 906 | 64000 | 1.42 |
| F7/F8 Muxes | <0.001 | 1938 | 203800 | 0.95 |
| Clocks | 0.155 | 11 | --- | --- |
| Slice Logic | 0.281 | 142277 | --- | --- |
| LUT as Logic | 0.237 | 64160 | 203800 | 31.48 |
| CARRY4 | 0.033 | 6514 | 50950 | 12.79 |
| Register | 0.010 | 52861 | 407600 | 12.97 |
| LUT as Distributed RAM | <0.001 | 898 | 64000 | 1.40 |
| F7/F8 Muxes | <0.001 | 2200 | 203800 | 1.08 |
| BUFG | <0.001 | 1 | 32 | 3.13 |
| LUT as Shift Register | <0.001 | 2 | 64000 | <0.01 |
| Others | 0.000 | 948 | --- | --- |
| Signals | 0.285 | 103161 | --- | --- |
| Block RAM | 0.533 | 417 | 445 | 93.71 |
| Others | 0.000 | 1053 | --- | --- |
| Signals | 0.313 | 116850 | --- | --- |
| Block RAM | 0.534 | 417 | 445 | 93.71 |
| MMCM | 0.363 | 3 | 10 | 30.00 |
| DSPs | 0.168 | 208 | 840 | 24.76 |
| I/O | 0.010 | 31 | 500 | 6.20 |
| DSPs | 0.170 | 208 | 840 | 24.76 |
| I/O | 0.009 | 31 | 500 | 6.20 |
| Static Power | 0.197 | | | |
| Total | 1.959 | | | |
| Total | 2.022 | | | |
+--------------------------+-----------+----------+-----------+-----------------+
@@ -78,7 +78,7 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint | 1.000 | 1.438 | 1.348 | 0.089 | NA | Unspecified | NA |
| Vccint | 1.000 | 1.501 | 1.411 | 0.090 | NA | Unspecified | NA |
| Vccaux | 1.800 | 0.233 | 0.204 | 0.029 | NA | Unspecified | NA |
| Vcco33 | 3.300 | 0.002 | 0.001 | 0.001 | NA | Unspecified | NA |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
@@ -156,21 +156,21 @@ Table of Contents
+----------------------------+-----------+
| Name | Power (W) |
+----------------------------+-----------+
| genesys2_rocket_top | 1.763 |
| u_rocket | 1.385 |
| genesys2_rocket_top | 1.825 |
| u_rocket | 1.448 |
| cbus | 0.004 |
| buffer | 0.002 |
| fbus | 0.001 |
| fpga_gps_domain | 1.135 |
| dev | 1.134 |
| tl2apb | 0.001 |
| fpga_gps_domain | 1.195 |
| dev | 1.192 |
| tl2apb | 0.003 |
| fpga_uart_domain | 0.001 |
| dev | 0.001 |
| pbus | 0.003 |
| tile_prci_domain | 0.229 |
| pbus | 0.004 |
| tile_prci_domain | 0.232 |
| buffer | 0.001 |
| element_reset_domain | 0.227 |
| tlDM | 0.002 |
| element_reset_domain | 0.230 |
| tlDM | 0.003 |
| dmInner | 0.002 |
+----------------------------+-----------+
targets/fpga/genesys2/out/reports/route_timing_summary.rpt
+547 -463
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File diff suppressed because it is too large Load Diff
targets/fpga/genesys2/out/reports/route_utilization.rpt
+45 -45
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@@ -1,9 +1,9 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
| Date : Sat Jul 11 20:02:19 2026
| Host : onur running 64-bit Ubuntu 22.04.5 LTS
| Command : report_utilization -file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/reports/route_utilization.rpt
| Date : Thu Aug 6 21:33:25 2026
| Host : ankalab04 running 64-bit Ubuntu 24.04.4 LTS
| Command : report_utilization -file /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/reports/route_utilization.rpt
| Design : genesys2_rocket_top
| Device : xc7k325tffg900-2
| Speed File : -2
@@ -32,17 +32,17 @@ Table of Contents
+----------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+-------+-------+------------+-----------+-------+
| Slice LUTs | 61266 | 0 | 0 | 203800 | 30.06 |
| LUT as Logic | 60358 | 0 | 0 | 203800 | 29.62 |
| LUT as Memory | 908 | 0 | 0 | 64000 | 1.42 |
| LUT as Distributed RAM | 906 | 0 | | | |
| Slice LUTs | 65060 | 0 | 0 | 203800 | 31.92 |
| LUT as Logic | 64160 | 0 | 0 | 203800 | 31.48 |
| LUT as Memory | 900 | 0 | 0 | 64000 | 1.41 |
| LUT as Distributed RAM | 898 | 0 | | | |
| LUT as Shift Register | 2 | 0 | | | |
| Slice Registers | 41422 | 0 | 0 | 407600 | 10.16 |
| Register as Flip Flop | 41413 | 0 | 0 | 407600 | 10.16 |
| Slice Registers | 52861 | 0 | 0 | 407600 | 12.97 |
| Register as Flip Flop | 52852 | 0 | 0 | 407600 | 12.97 |
| Register as Latch | 9 | 0 | 0 | 407600 | <0.01 |
| F7 Muxes | 1796 | 0 | 0 | 101900 | 1.76 |
| F8 Muxes | 142 | 0 | 0 | 50950 | 0.28 |
| Unique Control Sets | 1029 | | 0 | 50950 | 2.02 |
| F7 Muxes | 1956 | 0 | 0 | 101900 | 1.92 |
| F8 Muxes | 244 | 0 | 0 | 50950 | 0.48 |
| Unique Control Sets | 1095 | | 0 | 50950 | 2.15 |
+----------------------------+-------+-------+------------+-----------+-------+
* Warning! LUT value is adjusted to account for LUT combining.
** Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
@@ -60,10 +60,10 @@ Table of Contents
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 360 | Yes | - | Set |
| 30831 | Yes | - | Reset |
| 130 | Yes | Set | - |
| 10101 | Yes | Reset | - |
| 373 | Yes | - | Set |
| 42238 | Yes | - | Reset |
| 184 | Yes | Set | - |
| 10066 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -73,27 +73,27 @@ Table of Contents
+--------------------------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+--------------------------------------------+-------+-------+------------+-----------+-------+
| Slice | 19593 | 0 | 0 | 50950 | 38.46 |
| SLICEL | 13255 | 0 | | | |
| SLICEM | 6338 | 0 | | | |
| LUT as Logic | 60358 | 0 | 0 | 203800 | 29.62 |
| Slice | 22075 | 0 | 0 | 50950 | 43.33 |
| SLICEL | 15042 | 0 | | | |
| SLICEM | 7033 | 0 | | | |
| LUT as Logic | 64160 | 0 | 0 | 203800 | 31.48 |
| using O5 output only | 20 | | | | |
| using O6 output only | 47227 | | | | |
| using O5 and O6 | 13111 | | | | |
| LUT as Memory | 908 | 0 | 0 | 64000 | 1.42 |
| LUT as Distributed RAM | 906 | 0 | | | |
| using O6 output only | 50448 | | | | |
| using O5 and O6 | 13692 | | | | |
| LUT as Memory | 900 | 0 | 0 | 64000 | 1.41 |
| LUT as Distributed RAM | 898 | 0 | | | |
| using O5 output only | 0 | | | | |
| using O6 output only | 2 | | | | |
| using O5 and O6 | 904 | | | | |
| using O5 and O6 | 896 | | | | |
| LUT as Shift Register | 2 | 0 | | | |
| using O5 output only | 2 | | | | |
| using O6 output only | 0 | | | | |
| using O5 and O6 | 0 | | | | |
| Slice Registers | 41422 | 0 | 0 | 407600 | 10.16 |
| Register driven from within the Slice | 23051 | | | | |
| Register driven from outside the Slice | 18371 | | | | |
| LUT in front of the register is unused | 8475 | | | | |
| LUT in front of the register is used | 9896 | | | | |
| Slice Registers | 52861 | 0 | 0 | 407600 | 12.97 |
| Register driven from within the Slice | 25274 | | | | |
| Register driven from outside the Slice | 27587 | | | | |
| LUT in front of the register is unused | 14421 | | | | |
| LUT in front of the register is used | 13166 | | | | |
+--------------------------------------------+-------+-------+------------+-----------+-------+
@@ -192,23 +192,23 @@ Table of Contents
+------------+-------+---------------------+
| Ref Name | Used | Functional Category |
+------------+-------+---------------------+
| FDCE | 30822 | Flop & Latch |
| LUT6 | 24456 | LUT |
| LUT2 | 15148 | LUT |
| LUT5 | 12247 | LUT |
| LUT3 | 11204 | LUT |
| FDRE | 10101 | Flop & Latch |
| LUT4 | 7554 | LUT |
| CARRY4 | 6054 | CarryLogic |
| LUT1 | 2860 | LUT |
| MUXF7 | 1796 | MuxFx |
| RAMD32 | 1360 | Distributed Memory |
| RAMS32 | 450 | Distributed Memory |
| FDCE | 42229 | Flop & Latch |
| LUT6 | 24946 | LUT |
| LUT2 | 17047 | LUT |
| LUT5 | 13328 | LUT |
| LUT3 | 11258 | LUT |
| FDRE | 10066 | Flop & Latch |
| LUT4 | 8378 | LUT |
| CARRY4 | 6514 | CarryLogic |
| LUT1 | 2895 | LUT |
| MUXF7 | 1956 | MuxFx |
| RAMD32 | 1350 | Distributed Memory |
| RAMS32 | 444 | Distributed Memory |
| RAMB36E1 | 415 | Block Memory |
| FDPE | 360 | Flop & Latch |
| FDPE | 373 | Flop & Latch |
| MUXF8 | 244 | MuxFx |
| DSP48E1 | 208 | Block Arithmetic |
| MUXF8 | 142 | MuxFx |
| FDSE | 130 | Flop & Latch |
| FDSE | 184 | Flop & Latch |
| IBUF | 16 | IO |
| OBUF | 13 | IO |
| LDCE | 9 | Flop & Latch |
targets/fpga/genesys2/out/reports/synth_timing_summary.rpt
+169 -171
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@@ -1,14 +1,14 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
| Date : Sat Jul 11 19:55:22 2026
| Host : onur running 64-bit Ubuntu 22.04.5 LTS
| Command : report_timing_summary -file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/reports/synth_timing_summary.rpt
| Date : Thu Aug 6 21:29:37 2026
| Host : ankalab04 running 64-bit Ubuntu 24.04.4 LTS
| Command : report_timing_summary -file /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/reports/synth_timing_summary.rpt
| Design : genesys2_rocket_top
| Device : 7k325t-ffg900
| Speed File : -2 PRODUCTION 1.12 2017-02-17
| Design State : Synthesized
----------------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------------
Timing Summary Report
@@ -64,8 +64,6 @@ Table of Contents
1. checking no_clock (392)
--------------------------
There are 9 register/latch pins with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/apbReset_gps_apb_reset/io_sync_reset_chain/output_chain/sync_0_reg/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/code_freq_vld_reg/Q (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/prn_o_reg[0]/Q (HIGH)
@@ -210,6 +208,8 @@ Table of Contents
There is 1 register/latch pin with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/stop_in_trk_r3_reg/Q (HIGH)
There are 9 register/latch pins with no clock driven by root clock pin: u_rocket/fpga_gps_domain/dev/trckReset_gps_trck_reset/io_sync_reset_chain/output_chain/sync_0_reg/Q (HIGH)
There are 311 register/latch pins with no clock driven by root clock pin: u_rocket_bscan/TCK (HIGH)
@@ -284,7 +284,7 @@ Table of Contents
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
1.198 0.000 0 123398 -0.072 -27.056 1838 123398 1.100 0.000 0 43569
1.296 0.000 0 150889 -0.072 -27.118 1823 150889 1.100 0.000 0 54992
Timing constraints are not met.
@@ -320,10 +320,10 @@ pmod_rf_clk 58.914 0.000 0
pll_gps_ref_clk 6.000 0.000 0 3
gps_clkfb 16.592 0.000 0 3
pll_gps_acq_clk 1.769 0.000 0 6634 0.041 0.000 0 6634 5.900 0.000 0 1372
pll_gps_trck_clk 1.198 0.000 0 36466 -0.006 -0.303 51 36466 3.650 0.000 0 17889
pll_gps_trck_clk 1.296 0.000 0 42650 -0.006 -0.303 51 42650 3.650 0.000 0 20888
sysclk_200 1.100 0.000 0 1
fabric_clkfb 3.592 0.000 0 3
pll_fabric_clk 10.181 0.000 0 48882 -0.072 -26.485 1742 48882 9.232 0.000 0 23313
pll_fabric_clk 10.235 0.000 0 58121 -0.072 -26.547 1727 58121 9.232 0.000 0 31737
------------------------------------------------------------------------------------------------
@@ -342,10 +342,10 @@ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
**async_default** pll_fabric_clk pll_fabric_clk 17.802 0.000 0 11747 0.208 0.000 0 11747
**async_default** pll_fabric_clk pll_fabric_clk 18.135 0.000 0 20168 0.209 0.000 0 20168
**async_default** pll_gps_acq_clk pll_gps_acq_clk 10.783 0.000 0 997 0.545 0.000 0 997
**async_default** pll_gps_trck_clk pll_gps_trck_clk 5.838 0.000 0 17349 0.361 0.000 0 17349
**async_default** pmod_rf_clk pmod_rf_clk 59.496 0.000 0 172 0.502 0.000 0 172
**async_default** pll_gps_trck_clk pll_gps_trck_clk 5.838 0.000 0 20789 0.361 0.000 0 20789
**async_default** pmod_rf_clk pmod_rf_clk 59.399 0.000 0 379 0.502 0.000 0 379
------------------------------------------------------------------------------------------------
@@ -799,7 +799,7 @@ High Pulse Width Slow FDCE/C n/a 0.350 6.250
From Clock: pll_gps_trck_clk
To Clock: pll_gps_trck_clk
Setup : 0 Failing Endpoints, Worst Slack 1.198ns, Total Violation 0.000ns
Setup : 0 Failing Endpoints, Worst Slack 1.296ns, Total Violation 0.000ns
Hold : 51 Failing Endpoints, Worst Slack -0.006ns, Total Violation -0.303ns
PW : 0 Failing Endpoints, Worst Slack 3.650ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
@@ -807,7 +807,7 @@ PW : 0 Failing Endpoints, Worst Slack 3.650ns, Total Vio
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 1.198ns (required time - arrival time)
Slack (MET) : 1.296ns (required time - arrival time)
Source: u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds_work_reg[3]/C
(rising edge-triggered cell FDCE clocked by pll_gps_trck_clk {rise@0.000ns fall@4.000ns period=8.000ns})
Destination: u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[0]/D
@@ -815,7 +815,7 @@ Slack (MET) : 1.198ns (required time - arrival time)
Path Group: pll_gps_trck_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 8.000ns (pll_gps_trck_clk rise@8.000ns - pll_gps_trck_clk rise@0.000ns)
Data Path Delay: 6.612ns (logic 3.463ns (52.374%) route 3.149ns (47.626%))
Data Path Delay: 6.514ns (logic 3.436ns (52.748%) route 3.078ns (47.252%))
Logic Levels: 34 (CARRY4=29 LUT3=2 LUT5=1 LUT6=2)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.330ns = ( 10.330 - 8.000 )
@@ -845,7 +845,7 @@ Slack (MET) : 1.198ns (required time - arrival time)
-1.143 1.497 r u_gps_domain_mmcm/CLKOUT1
net (fo=1, unplaced) 0.466 1.963 pll_gps_trck_clk
BUFG (Prop_bufg_I_O) 0.093 2.056 r u_gps_trck_clk_buf/O
net (fo=17887, unplaced) 0.584 2.640 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/gps_trck_clk
net (fo=20886, unplaced) 0.584 2.640 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/gps_trck_clk
FDCE r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds_work_reg[3]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.233 2.873 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_seconds_work_reg[3]/Q
@@ -892,61 +892,61 @@ Slack (MET) : 1.198ns (required time - arrival time)
CARRY4 (Prop_carry4_CI_CO[3])
0.054 4.369 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_129/CO[3]
net (fo=1, unplaced) 0.000 4.369 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_129_n_0
CARRY4 (Prop_carry4_CI_O[3])
0.157 4.526 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_78/O[3]
net (fo=6, unplaced) 0.526 5.052 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_calculation2[59]
LUT3 (Prop_lut3_I2_O) 0.120 5.172 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[63]_i_145/O
net (fo=1, unplaced) 0.000 5.172 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[63]_i_145_n_0
CARRY4 (Prop_carry4_S[3]_CO[3])
0.180 5.352 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_92/CO[3]
net (fo=1, unplaced) 0.000 5.352 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_92_n_0
CARRY4 (Prop_carry4_CI_CO[1])
0.089 5.441 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_46/CO[1]
net (fo=34, unplaced) 0.424 5.865 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_46_n_2
LUT6 (Prop_lut6_I4_O) 0.124 5.989 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[55]_i_11/O
net (fo=2, unplaced) 0.281 6.270 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[55]_i_11_n_0
LUT6 (Prop_lut6_I5_O) 0.043 6.313 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[55]_i_5/O
net (fo=2, unplaced) 0.508 6.821 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[55]_i_5_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 4.423 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_78/CO[3]
net (fo=1, unplaced) 0.000 4.423 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_78_n_0
CARRY4 (Prop_carry4_CI_O[0])
0.114 4.537 f u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_34/O[0]
net (fo=6, unplaced) 0.448 4.985 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_calculation2[60]
LUT3 (Prop_lut3_I0_O) 0.123 5.108 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[63]_i_97/O
net (fo=1, unplaced) 0.000 5.108 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[63]_i_97_n_0
CARRY4 (Prop_carry4_S[0]_CO[1])
0.228 5.336 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_47/CO[1]
net (fo=45, unplaced) 0.431 5.767 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/p_0_in0
LUT6 (Prop_lut6_I4_O) 0.124 5.891 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[55]_i_11/O
net (fo=2, unplaced) 0.281 6.172 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[55]_i_11_n_0
LUT6 (Prop_lut6_I5_O) 0.043 6.215 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[55]_i_5/O
net (fo=2, unplaced) 0.508 6.723 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[55]_i_5_n_0
CARRY4 (Prop_carry4_DI[1]_CO[3])
0.253 7.074 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[55]_i_2/CO[3]
net (fo=1, unplaced) 0.000 7.074 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[55]_i_2_n_0
0.253 6.976 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[55]_i_2/CO[3]
net (fo=1, unplaced) 0.000 6.976 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[55]_i_2_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 7.128 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[59]_i_2/CO[3]
net (fo=1, unplaced) 0.000 7.128 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[59]_i_2_n_0
0.054 7.030 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[59]_i_2/CO[3]
net (fo=1, unplaced) 0.000 7.030 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[59]_i_2_n_0
CARRY4 (Prop_carry4_CI_O[3])
0.157 7.285 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_6/O[3]
net (fo=6, unplaced) 0.526 7.811 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_calculation[63]
LUT3 (Prop_lut3_I2_O) 0.124 7.935 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[63]_i_436/O
net (fo=1, unplaced) 0.000 7.935 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[63]_i_436_n_0
0.157 7.187 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_6/O[3]
net (fo=6, unplaced) 0.526 7.713 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_calculation[63]
LUT3 (Prop_lut3_I0_O) 0.124 7.837 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[63]_i_436/O
net (fo=1, unplaced) 0.000 7.837 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[63]_i_436_n_0
CARRY4 (Prop_carry4_DI[0]_CO[3])
0.293 8.228 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_386/CO[3]
net (fo=1, unplaced) 0.007 8.235 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_386_n_0
0.293 8.130 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_386/CO[3]
net (fo=1, unplaced) 0.007 8.137 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_386_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 8.289 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_331/CO[3]
net (fo=1, unplaced) 0.000 8.289 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_331_n_0
0.054 8.191 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_331/CO[3]
net (fo=1, unplaced) 0.000 8.191 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_331_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 8.343 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_275/CO[3]
net (fo=1, unplaced) 0.000 8.343 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_275_n_0
0.054 8.245 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_275/CO[3]
net (fo=1, unplaced) 0.000 8.245 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_275_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 8.397 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_219/CO[3]
net (fo=1, unplaced) 0.000 8.397 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_219_n_0
0.054 8.299 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_219/CO[3]
net (fo=1, unplaced) 0.000 8.299 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_219_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 8.451 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_163/CO[3]
net (fo=1, unplaced) 0.000 8.451 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_163_n_0
0.054 8.353 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_163/CO[3]
net (fo=1, unplaced) 0.000 8.353 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_163_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 8.505 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_111/CO[3]
net (fo=1, unplaced) 0.000 8.505 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_111_n_0
0.054 8.407 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_111/CO[3]
net (fo=1, unplaced) 0.000 8.407 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_111_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 8.559 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_60/CO[3]
net (fo=1, unplaced) 0.000 8.559 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_60_n_0
0.054 8.461 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_60/CO[3]
net (fo=1, unplaced) 0.000 8.461 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_60_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 8.613 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_23/CO[3]
net (fo=1, unplaced) 0.000 8.613 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_23_n_0
0.054 8.515 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_23/CO[3]
net (fo=1, unplaced) 0.000 8.515 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_23_n_0
CARRY4 (Prop_carry4_CI_CO[0])
0.147 8.760 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_8/CO[0]
net (fo=66, unplaced) 0.356 9.116 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_8_n_3
LUT5 (Prop_lut5_I0_O) 0.136 9.252 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[0]_i_1/O
net (fo=1, unplaced) 0.000 9.252 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[0]_i_1_n_0
0.147 8.662 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_8/CO[0]
net (fo=66, unplaced) 0.356 9.018 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[63]_i_8_n_3
LUT5 (Prop_lut5_I0_O) 0.136 9.154 r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[0]_i_1/O
net (fo=1, unplaced) 0.000 9.154 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work[0]_i_1_n_0
FDCE r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[0]/D
------------------------------------------------------------------- -------------------
@@ -967,16 +967,16 @@ Slack (MET) : 1.198ns (required time - arrival time)
-0.964 9.365 r u_gps_domain_mmcm/CLKOUT1
net (fo=1, unplaced) 0.442 9.808 pll_gps_trck_clk
BUFG (Prop_bufg_I_O) 0.083 9.891 r u_gps_trck_clk_buf/O
net (fo=17887, unplaced) 0.439 10.330 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/gps_trck_clk
net (fo=20886, unplaced) 0.439 10.330 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/gps_trck_clk
FDCE r u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[0]/C
clock pessimism 0.165 10.495
clock uncertainty -0.081 10.414
FDCE (Setup_fdce_C_D) 0.036 10.450 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/phase_work_reg[0]
-------------------------------------------------------------------
required time 10.450
arrival time -9.252
arrival time -9.154
-------------------------------------------------------------------
slack 1.198
slack 1.296
@@ -1018,7 +1018,7 @@ Slack (VIOLATED) : -0.006ns (arrival time - required time)
-0.371 0.422 r u_gps_domain_mmcm/CLKOUT1
net (fo=1, unplaced) 0.231 0.653 pll_gps_trck_clk
BUFG (Prop_bufg_I_O) 0.026 0.679 r u_gps_trck_clk_buf/O
net (fo=17887, unplaced) 0.114 0.793 u_rocket/fpga_gps_domain/dev/pps/gps_trck_clk
net (fo=20886, unplaced) 0.114 0.793 u_rocket/fpga_gps_domain/dev/pps/gps_trck_clk
FDCE r u_rocket/fpga_gps_domain/dev/pps/control_sync1_p_reg[0]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.104 0.897 r u_rocket/fpga_gps_domain/dev/pps/control_sync1_p_reg[0]/Q
@@ -1043,7 +1043,7 @@ Slack (VIOLATED) : -0.006ns (arrival time - required time)
-0.532 0.618 r u_gps_domain_mmcm/CLKOUT1
net (fo=1, unplaced) 0.243 0.861 pll_gps_trck_clk
BUFG (Prop_bufg_I_O) 0.030 0.891 r u_gps_trck_clk_buf/O
net (fo=17887, unplaced) 0.259 1.150 u_rocket/fpga_gps_domain/dev/pps/gps_trck_clk
net (fo=20886, unplaced) 0.259 1.150 u_rocket/fpga_gps_domain/dev/pps/gps_trck_clk
FDCE r u_rocket/fpga_gps_domain/dev/pps/control_sync2_p_reg[0]/C
clock pessimism -0.212 0.938
FDCE (Hold_fdce_C_D) 0.019 0.957 u_rocket/fpga_gps_domain/dev/pps/control_sync2_p_reg[0]
@@ -1067,8 +1067,8 @@ Sources: { u_gps_domain_mmcm/CLKOUT1 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a DSP48E1/CLK n/a 1.538 8.000 6.462 u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__0/CLK
Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 8.000 205.360 u_gps_domain_mmcm/CLKOUT1
Low Pulse Width Slow FDCE/C n/a 0.350 4.000 3.650 u_rocket/integrator_candidate_work_reg[111]_i_20/C
High Pulse Width Slow FDCE/C n/a 0.350 4.000 3.650 u_rocket/integrator_candidate_work_reg[111]_i_20/C
Low Pulse Width Slow FDCE/C n/a 0.350 4.000 3.650 u_rocket/integrator_candidate_work_reg[15]_i_15/C
High Pulse Width Slow FDCE/C n/a 0.350 4.000 3.650 u_rocket/integrator_candidate_work_reg[15]_i_15/C
@@ -1124,15 +1124,15 @@ Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 5.000
From Clock: pll_fabric_clk
To Clock: pll_fabric_clk
Setup : 0 Failing Endpoints, Worst Slack 10.181ns, Total Violation 0.000ns
Hold : 1742 Failing Endpoints, Worst Slack -0.072ns, Total Violation -26.485ns
Setup : 0 Failing Endpoints, Worst Slack 10.235ns, Total Violation 0.000ns
Hold : 1727 Failing Endpoints, Worst Slack -0.072ns, Total Violation -26.547ns
PW : 0 Failing Endpoints, Worst Slack 9.232ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 10.181ns (required time - arrival time)
Slack (MET) : 10.235ns (required time - arrival time)
Source: u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/in_in2_reg[61]/C
(rising edge-triggered cell FDRE clocked by pll_fabric_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[105]/D
@@ -1140,7 +1140,7 @@ Slack (MET) : 10.181ns (required time - arrival time)
Path Group: pll_fabric_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (pll_fabric_clk rise@20.000ns - pll_fabric_clk rise@0.000ns)
Data Path Delay: 9.656ns (logic 7.139ns (73.931%) route 2.517ns (26.069%))
Data Path Delay: 9.602ns (logic 7.084ns (73.774%) route 2.518ns (26.226%))
Logic Levels: 21 (CARRY4=15 DSP48E1=3 LUT3=2 LUT6=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -2.081ns = ( 17.919 - 20.000 )
@@ -1163,71 +1163,71 @@ Slack (MET) : 10.181ns (required time - arrival time)
-5.216 -3.726 r u_clock_mmcm/CLKOUT1
net (fo=1, unplaced) 0.466 -3.260 pll_fabric_clk
BUFG (Prop_bufg_I_O) 0.093 -3.167 r u_fabric_clk_buf/O
net (fo=23331, unplaced) 0.584 -2.583 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/io_aggregator_0_clock
net (fo=31755, unplaced) 0.584 -2.583 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/io_aggregator_0_clock
FDRE r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/in_in2_reg[61]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.223 -2.360 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/in_in2_reg[61]/Q
net (fo=17, unplaced) 0.472 -1.888 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/Q[27]
LUT3 (Prop_lut3_I0_O) 0.123 -1.765 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_i_18/O
net (fo=3, unplaced) 0.466 -1.300 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_i_18_n_0
net (fo=18, unplaced) 0.473 -1.887 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/Q[27]
LUT3 (Prop_lut3_I0_O) 0.123 -1.764 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_i_19/O
net (fo=3, unplaced) 0.466 -1.299 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_i_19_n_0
DSP48E1 (Prop_dsp48e1_A[18]_PCOUT[47])
2.879 1.579 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__2/PCOUT[47]
net (fo=1, unplaced) 0.050 1.629 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__2_n_106
2.879 1.580 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__2/PCOUT[47]
net (fo=1, unplaced) 0.050 1.630 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__2_n_106
DSP48E1 (Prop_dsp48e1_PCIN[47]_PCOUT[47])
1.219 2.848 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__3/PCOUT[47]
net (fo=1, unplaced) 0.000 2.848 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__3_n_106
1.219 2.849 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__3/PCOUT[47]
net (fo=1, unplaced) 0.000 2.849 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__3_n_106
DSP48E1 (Prop_dsp48e1_PCIN[47]_P[18])
1.077 3.925 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__4/P[18]
net (fo=3, unplaced) 0.466 4.391 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__4_n_87
LUT3 (Prop_lut3_I1_O) 0.050 4.441 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/i___1_carry__4_i_4/O
net (fo=2, unplaced) 0.311 4.752 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/i___1_carry__4_i_4_n_0
CARRY4 (Prop_carry4_DI[0]_CO[3])
0.374 5.126 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_inferred__1/i___1_carry__4/CO[3]
net (fo=1, unplaced) 0.000 5.126 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_inferred__1/i___1_carry__4_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 5.180 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_inferred__1/i___1_carry__5/CO[3]
net (fo=1, unplaced) 0.000 5.180 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_inferred__1/i___1_carry__5_n_0
CARRY4 (Prop_carry4_CI_O[2])
0.120 5.300 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_inferred__1/i___1_carry__6/O[2]
net (fo=2, unplaced) 0.753 6.053 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_preMul/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[67][2]
LUT6 (Prop_lut6_I3_O) 0.127 6.180 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_preMul/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b[63]_i_2/O
net (fo=1, unplaced) 0.000 6.180 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_preMul_n_117
1.077 3.926 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__4/P[18]
net (fo=3, unplaced) 0.466 4.392 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__4_n_87
LUT3 (Prop_lut3_I1_O) 0.050 4.442 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b[59]_i_10/O
net (fo=2, unplaced) 0.311 4.753 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b[59]_i_10_n_0
CARRY4 (Prop_carry4_DI[0]_O[2])
0.385 5.138 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[59]_i_2/O[2]
net (fo=2, unplaced) 0.753 5.891 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[59]_i_2_n_5
LUT6 (Prop_lut6_I3_O) 0.127 6.018 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b[55]_i_3/O
net (fo=1, unplaced) 0.000 6.018 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b[55]_i_3_n_0
CARRY4 (Prop_carry4_S[3]_CO[3])
0.180 6.360 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[63]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.360 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[63]_i_1_n_0
0.180 6.198 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[55]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.198 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[55]_i_1_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 6.414 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[67]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.414 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[67]_i_1_n_0
0.054 6.252 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[59]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.252 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[59]_i_1_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 6.468 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[71]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.468 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[71]_i_1_n_0
0.054 6.306 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[63]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.306 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[63]_i_1_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 6.522 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[75]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.522 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[75]_i_1_n_0
0.054 6.360 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[67]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.360 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[67]_i_1_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 6.576 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[79]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.576 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[79]_i_1_n_0
0.054 6.414 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[71]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.414 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[71]_i_1_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 6.630 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[83]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.630 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[83]_i_1_n_0
0.054 6.468 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[75]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.468 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[75]_i_1_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 6.684 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[87]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.684 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[87]_i_1_n_0
0.054 6.522 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[79]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.522 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[79]_i_1_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 6.738 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[91]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.738 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[91]_i_1_n_0
0.054 6.576 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[83]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.576 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[83]_i_1_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 6.792 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[95]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.792 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[95]_i_1_n_0
0.054 6.630 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[87]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.630 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[87]_i_1_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 6.846 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[99]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.846 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[99]_i_1_n_0
0.054 6.684 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[91]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.684 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[91]_i_1_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 6.900 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[103]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.900 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[103]_i_1_n_0
0.054 6.738 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[95]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.738 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[95]_i_1_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 6.792 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[99]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.792 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[99]_i_1_n_0
CARRY4 (Prop_carry4_CI_CO[3])
0.054 6.846 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[103]_i_1/CO[3]
net (fo=1, unplaced) 0.000 6.846 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[103]_i_1_n_0
CARRY4 (Prop_carry4_CI_O[1])
0.173 7.073 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[106]_i_1/O[1]
net (fo=1, unplaced) 0.000 7.073 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[106]_i_1_n_6
0.173 7.019 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[106]_i_1/O[1]
net (fo=1, unplaced) 0.000 7.019 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[106]_i_1_n_6
FDRE r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[105]/D
------------------------------------------------------------------- -------------------
@@ -1241,16 +1241,16 @@ Slack (MET) : 10.181ns (required time - arrival time)
-4.287 16.955 r u_clock_mmcm/CLKOUT1
net (fo=1, unplaced) 0.442 17.397 pll_fabric_clk
BUFG (Prop_bufg_I_O) 0.083 17.480 r u_fabric_clk_buf/O
net (fo=23331, unplaced) 0.439 17.919 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/io_aggregator_0_clock
net (fo=31755, unplaced) 0.439 17.919 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/io_aggregator_0_clock
FDRE r u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[105]/C
clock pessimism -0.648 17.272
clock uncertainty -0.073 17.198
FDRE (Setup_fdre_C_D) 0.055 17.253 u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b_reg[105]
-------------------------------------------------------------------
required time 17.253
arrival time -7.073
arrival time -7.019
-------------------------------------------------------------------
slack 10.181
slack 10.235
@@ -1261,7 +1261,7 @@ Min Delay Paths
Slack (VIOLATED) : -0.072ns (arrival time - required time)
Source: u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/refill_paddr_reg[12]/C
(rising edge-triggered cell FDRE clocked by pll_fabric_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_0_ext/Memory_reg/DIADI[0]
Destination: u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_ext/Memory_reg/DIADI[0]
(rising edge-triggered cell RAMB18E1 clocked by pll_fabric_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: pll_fabric_clk
Path Type: Hold (Min at Fast Process Corner)
@@ -1285,12 +1285,12 @@ Slack (VIOLATED) : -0.072ns (arrival time - required time)
-1.786 -1.283 r u_clock_mmcm/CLKOUT1
net (fo=1, unplaced) 0.231 -1.053 pll_fabric_clk
BUFG (Prop_bufg_I_O) 0.026 -1.027 r u_fabric_clk_buf/O
net (fo=23331, unplaced) 0.114 -0.913 u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/io_aggregator_0_clock
net (fo=31755, unplaced) 0.114 -0.913 u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/io_aggregator_0_clock
FDRE r u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/refill_paddr_reg[12]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.100 -0.813 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/refill_paddr_reg[12]/Q
net (fo=2, unplaced) 0.231 -0.582 u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_0_ext/Q[6]
RAMB18E1 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_0_ext/Memory_reg/DIADI[0]
net (fo=2, unplaced) 0.231 -0.582 u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_ext/Q[6]
RAMB18E1 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_ext/Memory_reg/DIADI[0]
------------------------------------------------------------------- -------------------
(clock pll_fabric_clk rise edge)
@@ -1303,11 +1303,11 @@ Slack (VIOLATED) : -0.072ns (arrival time - required time)
-2.090 -1.361 r u_clock_mmcm/CLKOUT1
net (fo=1, unplaced) 0.243 -1.118 pll_fabric_clk
BUFG (Prop_bufg_I_O) 0.030 -1.088 r u_fabric_clk_buf/O
net (fo=23331, unplaced) 0.259 -0.829 u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_0_ext/io_aggregator_0_clock
RAMB18E1 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_0_ext/Memory_reg/CLKARDCLK
net (fo=31755, unplaced) 0.259 -0.829 u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_ext/io_aggregator_0_clock
RAMB18E1 r u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_ext/Memory_reg/CLKARDCLK
clock pessimism 0.062 -0.768
RAMB18E1 (Hold_ramb18e1_CLKARDCLK_DIADI[0])
0.258 -0.510 u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_0_ext/Memory_reg
0.258 -0.510 u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/icache/rockettile_icache_tag_array_ext/Memory_reg
-------------------------------------------------------------------
required time 0.510
arrival time -0.582
@@ -1338,23 +1338,23 @@ Path Group: **async_default**
From Clock: pll_fabric_clk
To Clock: pll_fabric_clk
Setup : 0 Failing Endpoints, Worst Slack 17.802ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.208ns, Total Violation 0.000ns
Setup : 0 Failing Endpoints, Worst Slack 18.135ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.209ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 17.802ns (required time - arrival time)
Slack (MET) : 18.135ns (required time - arrival time)
Source: reset_shift_reg[15]/C
(rising edge-triggered cell FDSE clocked by pll_fabric_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: u_rocket/tlDM/dmInner/dmiXing/nodeIn_d_source/source_valid_0/io_out_source_valid_0/output_chain/sync_0_reg/CLR
Destination: u_rocket/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR
(recovery check against rising-edge clock pll_fabric_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 20.000ns (pll_fabric_clk rise@20.000ns - pll_fabric_clk rise@0.000ns)
Data Path Delay: 1.766ns (logic 0.389ns (22.027%) route 1.377ns (77.973%))
Logic Levels: 2 (LUT2=2)
Data Path Delay: 1.433ns (logic 0.346ns (24.145%) route 1.087ns (75.855%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): -2.081ns = ( 17.919 - 20.000 )
Source Clock Delay (SCD): -2.583ns
@@ -1376,16 +1376,14 @@ Slack (MET) : 17.802ns (required time - arrival time)
-5.216 -3.726 r u_clock_mmcm/CLKOUT1
net (fo=1, unplaced) 0.466 -3.260 pll_fabric_clk
BUFG (Prop_bufg_I_O) 0.093 -3.167 r u_fabric_clk_buf/O
net (fo=23331, unplaced) 0.584 -2.583 fabric_clk
net (fo=31755, unplaced) 0.584 -2.583 fabric_clk
FDSE r reset_shift_reg[15]/C
------------------------------------------------------------------- -------------------
FDSE (Prop_fdse_C_Q) 0.223 -2.360 f reset_shift_reg[15]/Q
net (fo=57, unplaced) 0.353 -2.007 u_rocket_bscan_dmi_tunnel/led_OBUF[1]
LUT2 (Prop_lut2_I0_O) 0.123 -1.884 f u_rocket_bscan_dmi_tunnel/u_rocket_i_2/O
net (fo=228, unplaced) 0.390 -1.494 u_rocket/tlDM/dmInner/dmiXing/nodeIn_d_source/source_valid_1/io_out_source_valid_0/output_chain/debug_clockeddmi_dmiReset
LUT2 (Prop_lut2_I1_O) 0.043 -1.451 f u_rocket/tlDM/dmInner/dmiXing/nodeIn_d_source/source_valid_1/io_out_source_valid_0/output_chain/sync_2_i_1/O
net (fo=9, unplaced) 0.634 -0.817 u_rocket/tlDM/dmInner/dmiXing/nodeIn_d_source/source_valid_0/io_out_source_valid_0/output_chain/sync_0_reg_1
FDCE f u_rocket/tlDM/dmInner/dmiXing/nodeIn_d_source/source_valid_0/io_out_source_valid_0/output_chain/sync_0_reg/CLR
net (fo=60, unplaced) 0.354 -2.006 led_OBUF[4]
LUT2 (Prop_lut2_I0_O) 0.123 -1.883 f u_rocket_i_1/O
net (fo=919, unplaced) 0.733 -1.150 u_rocket/clint_domain/intsource/reg_0/io_aggregator_1_reset
FDCE f u_rocket/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR
------------------------------------------------------------------- -------------------
(clock pll_fabric_clk rise edge)
@@ -1398,16 +1396,16 @@ Slack (MET) : 17.802ns (required time - arrival time)
-4.287 16.955 r u_clock_mmcm/CLKOUT1
net (fo=1, unplaced) 0.442 17.397 pll_fabric_clk
BUFG (Prop_bufg_I_O) 0.083 17.480 r u_fabric_clk_buf/O
net (fo=23331, unplaced) 0.439 17.919 u_rocket/tlDM/dmInner/dmiXing/nodeIn_d_source/source_valid_0/io_out_source_valid_0/output_chain/debug_clock
FDCE r u_rocket/tlDM/dmInner/dmiXing/nodeIn_d_source/source_valid_0/io_out_source_valid_0/output_chain/sync_0_reg/C
net (fo=31755, unplaced) 0.439 17.919 u_rocket/clint_domain/intsource/reg_0/io_aggregator_1_clock
FDCE r u_rocket/clint_domain/intsource/reg_0/reg_0_reg[0]/C
clock pessimism -0.648 17.272
clock uncertainty -0.073 17.198
FDCE (Recov_fdce_C_CLR) -0.214 16.984 u_rocket/tlDM/dmInner/dmiXing/nodeIn_d_source/source_valid_0/io_out_source_valid_0/output_chain/sync_0_reg
FDCE (Recov_fdce_C_CLR) -0.214 16.984 u_rocket/clint_domain/intsource/reg_0/reg_0_reg[0]
-------------------------------------------------------------------
required time 16.984
arrival time 0.817
arrival time 1.150
-------------------------------------------------------------------
slack 17.802
slack 18.135
@@ -1415,7 +1413,7 @@ Slack (MET) : 17.802ns (required time - arrival time)
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.208ns (arrival time - required time)
Slack (MET) : 0.209ns (arrival time - required time)
Source: reset_shift_reg[15]/C
(rising edge-triggered cell FDSE clocked by pll_fabric_clk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: u_rocket/tlDM/dmInner/dmInner/hartIsInResetSync_0_debug_hartReset_0/output_chain/sync_0_reg/CLR
@@ -1423,7 +1421,7 @@ Slack (MET) : 0.208ns (arrival time - required time)
Path Group: **async_default**
Path Type: Removal (Min at Fast Process Corner)
Requirement: 0.000ns (pll_fabric_clk rise@0.000ns - pll_fabric_clk rise@0.000ns)
Data Path Delay: 0.246ns (logic 0.100ns (40.602%) route 0.146ns (59.398%))
Data Path Delay: 0.247ns (logic 0.100ns (40.521%) route 0.147ns (59.479%))
Logic Levels: 0
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): -0.829ns
@@ -1442,11 +1440,11 @@ Slack (MET) : 0.208ns (arrival time - required time)
-1.786 -1.283 r u_clock_mmcm/CLKOUT1
net (fo=1, unplaced) 0.231 -1.053 pll_fabric_clk
BUFG (Prop_bufg_I_O) 0.026 -1.027 r u_fabric_clk_buf/O
net (fo=23331, unplaced) 0.114 -0.913 fabric_clk
net (fo=31755, unplaced) 0.114 -0.913 fabric_clk
FDSE r reset_shift_reg[15]/C
------------------------------------------------------------------- -------------------
FDSE (Prop_fdse_C_Q) 0.100 -0.813 f reset_shift_reg[15]/Q
net (fo=57, unplaced) 0.146 -0.666 u_rocket/tlDM/dmInner/dmInner/hartIsInResetSync_0_debug_hartReset_0/output_chain/debug_reset
net (fo=60, unplaced) 0.147 -0.666 u_rocket/tlDM/dmInner/dmInner/hartIsInResetSync_0_debug_hartReset_0/output_chain/debug_reset
FDCE f u_rocket/tlDM/dmInner/dmInner/hartIsInResetSync_0_debug_hartReset_0/output_chain/sync_0_reg/CLR
------------------------------------------------------------------- -------------------
@@ -1460,7 +1458,7 @@ Slack (MET) : 0.208ns (arrival time - required time)
-2.090 -1.361 r u_clock_mmcm/CLKOUT1
net (fo=1, unplaced) 0.243 -1.118 pll_fabric_clk
BUFG (Prop_bufg_I_O) 0.030 -1.088 r u_fabric_clk_buf/O
net (fo=23331, unplaced) 0.259 -0.829 u_rocket/tlDM/dmInner/dmInner/hartIsInResetSync_0_debug_hartReset_0/output_chain/debug_clock
net (fo=31755, unplaced) 0.259 -0.829 u_rocket/tlDM/dmInner/dmInner/hartIsInResetSync_0_debug_hartReset_0/output_chain/debug_clock
FDCE r u_rocket/tlDM/dmInner/dmInner/hartIsInResetSync_0_debug_hartReset_0/output_chain/sync_0_reg/C
clock pessimism 0.062 -0.768
FDCE (Remov_fdce_C_CLR) -0.107 -0.875 u_rocket/tlDM/dmInner/dmInner/hartIsInResetSync_0_debug_hartReset_0/output_chain/sync_0_reg
@@ -1468,7 +1466,7 @@ Slack (MET) : 0.208ns (arrival time - required time)
required time 0.875
arrival time -0.666
-------------------------------------------------------------------
slack 0.208
slack 0.209
@@ -1693,7 +1691,7 @@ Slack (MET) : 5.838ns (required time - arrival time)
-1.143 1.497 r u_gps_domain_mmcm/CLKOUT1
net (fo=1, unplaced) 0.466 1.963 pll_gps_trck_clk
BUFG (Prop_bufg_I_O) 0.093 2.056 r u_gps_trck_clk_buf/O
net (fo=17887, unplaced) 0.584 2.640 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/gps_trck_clk
net (fo=20886, unplaced) 0.584 2.640 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/gps_trck_clk
FDCE r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/stop_in_trk_r3_reg/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.223 2.863 r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/stop_in_trk_r3_reg/Q
@@ -1722,7 +1720,7 @@ Slack (MET) : 5.838ns (required time - arrival time)
-0.964 9.365 r u_gps_domain_mmcm/CLKOUT1
net (fo=1, unplaced) 0.442 9.808 pll_gps_trck_clk
BUFG (Prop_bufg_I_O) 0.083 9.891 r u_gps_trck_clk_buf/O
net (fo=17887, unplaced) 0.439 10.330 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/gps_trck_clk
net (fo=20886, unplaced) 0.439 10.330 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/gps_trck_clk
FDCE r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/chip_o_reg_C/C
clock pessimism 0.165 10.495
clock uncertainty -0.081 10.414
@@ -1773,7 +1771,7 @@ Slack (MET) : 0.361ns (arrival time - required time)
-0.371 0.422 r u_gps_domain_mmcm/CLKOUT1
net (fo=1, unplaced) 0.231 0.653 pll_gps_trck_clk
BUFG (Prop_bufg_I_O) 0.026 0.679 r u_gps_trck_clk_buf/O
net (fo=17887, unplaced) 0.114 0.793 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/gps_trck_clk
net (fo=20886, unplaced) 0.114 0.793 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/gps_trck_clk
FDCE r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/prn_o_reg[4]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.100 0.893 r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/prn_o_reg[4]/Q
@@ -1800,7 +1798,7 @@ Slack (MET) : 0.361ns (arrival time - required time)
-0.532 0.618 r u_gps_domain_mmcm/CLKOUT1
net (fo=1, unplaced) 0.243 0.861 pll_gps_trck_clk
BUFG (Prop_bufg_I_O) 0.030 0.891 r u_gps_trck_clk_buf/O
net (fo=17887, unplaced) 0.259 1.150 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/gps_trck_clk
net (fo=20886, unplaced) 0.259 1.150 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/gps_trck_clk
FDPE r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/chip_o_reg_P/C
clock pessimism -0.212 0.938
FDPE (Remov_fdpe_C_PRE) -0.074 0.864 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_code_i/cacode_gen_trck_i/chip_o_reg_P
@@ -1819,23 +1817,23 @@ Path Group: **async_default**
From Clock: pmod_rf_clk
To Clock: pmod_rf_clk
Setup : 0 Failing Endpoints, Worst Slack 59.496ns, Total Violation 0.000ns
Setup : 0 Failing Endpoints, Worst Slack 59.399ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.502ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 59.496ns (required time - arrival time)
Slack (MET) : 59.399ns (required time - arrival time)
Source: u_rocket/fpga_gps_domain/dev/afeReset_gps_afe_reset/io_sync_reset_chain/output_chain/sync_0_reg/C
(rising edge-triggered cell FDCE clocked by pmod_rf_clk {rise@0.000ns fall@30.548ns period=61.095ns})
Destination: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_en_reg/CLR
Destination: u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/wptr_q_reg[0]/CLR
(recovery check against rising-edge clock pmod_rf_clk {rise@0.000ns fall@30.548ns period=61.095ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 61.095ns (pmod_rf_clk rise@61.095ns - pmod_rf_clk rise@0.000ns)
Data Path Delay: 1.205ns (logic 0.346ns (28.714%) route 0.859ns (71.286%))
Logic Levels: 1 (LUT1=1)
Data Path Delay: 1.302ns (logic 0.346ns (26.575%) route 0.956ns (73.425%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.330ns = ( 63.425 - 61.095 )
Source Clock Delay (SCD): 2.640ns
@@ -1859,10 +1857,10 @@ Slack (MET) : 59.496ns (required time - arrival time)
FDCE r u_rocket/fpga_gps_domain/dev/afeReset_gps_afe_reset/io_sync_reset_chain/output_chain/sync_0_reg/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.223 2.863 r u_rocket/fpga_gps_domain/dev/afeReset_gps_afe_reset/io_sync_reset_chain/output_chain/sync_0_reg/Q
net (fo=1, unplaced) 0.191 3.054 u_rocket/fpga_gps_domain/dev/afeReset_gps_afe_reset/io_sync_reset_chain/output_chain/sync_0_reg_n_0
LUT1 (Prop_lut1_I0_O) 0.123 3.177 f u_rocket/fpga_gps_domain/dev/afeReset_gps_afe_reset/io_sync_reset_chain/output_chain/start_r1_i_2/O
net (fo=37, unplaced) 0.668 3.845 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_end_reg_0
FDCE f u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_en_reg/CLR
net (fo=10, unplaced) 0.310 3.173 u_rocket/fpga_gps_domain/dev/tracking_0/reg_q_reg[1]
LUT2 (Prop_lut2_I0_O) 0.123 3.296 f u_rocket/fpga_gps_domain/dev/tracking_0/i___202/O
net (fo=15, unplaced) 0.646 3.942 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/reg_q_reg[1]
FDCE f u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/wptr_q_reg[0]/CLR
------------------------------------------------------------------- -------------------
(clock pmod_rf_clk rise edge)
@@ -1872,16 +1870,16 @@ Slack (MET) : 59.496ns (required time - arrival time)
U27 IBUF (Prop_ibuf_I_O) 1.365 62.460 r u_rf_clk_pmod_ibuf/O
net (fo=1, unplaced) 0.442 62.903 rf_clk_pmod_ibuf
BUFG (Prop_bufg_I_O) 0.083 62.986 r u_rf_clk_pmod_buf/O
net (fo=982, unplaced) 0.439 63.425 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/gps_rf_clk
FDCE r u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_en_reg/C
net (fo=982, unplaced) 0.439 63.425 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gps_rf_clk
FDCE r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/wptr_q_reg[0]/C
clock pessimism 0.165 63.590
clock uncertainty -0.035 63.554
FDCE (Recov_fdce_C_CLR) -0.214 63.340 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/wr_mem_en_reg
FDCE (Recov_fdce_C_CLR) -0.214 63.340 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/wptr_q_reg[0]
-------------------------------------------------------------------
required time 63.340
arrival time -3.845
arrival time -3.942
-------------------------------------------------------------------
slack 59.496
slack 59.399
@@ -1918,7 +1916,7 @@ Slack (MET) : 0.502ns (arrival time - required time)
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.100 0.893 r u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/reset_synch_i/afe_r2_reg/Q
net (fo=1, unplaced) 0.095 0.988 u_rocket/fpga_gps_domain/dev/tracking_0/trck_cntrl_i/afe_soft_rstn
LUT2 (Prop_lut2_I1_O) 0.064 1.052 f u_rocket/fpga_gps_domain/dev/tracking_0/i___183/O
LUT2 (Prop_lut2_I1_O) 0.064 1.052 f u_rocket/fpga_gps_domain/dev/tracking_0/i___202/O
net (fo=15, unplaced) 0.320 1.372 u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/reg_q_reg[1]_15
FDCE f u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/cdc_fifo_gray_i/i_src/gen_sync[0].i_sync/reg_q_reg[0]/CLR
------------------------------------------------------------------- -------------------
targets/fpga/genesys2/out/reports/synth_utilization.rpt
+31 -31
View File
@@ -1,9 +1,9 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
| Date : Sat Jul 11 19:55:13 2026
| Host : onur running 64-bit Ubuntu 22.04.5 LTS
| Command : report_utilization -file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/reports/synth_utilization.rpt
| Date : Thu Aug 6 21:29:32 2026
| Host : ankalab04 running 64-bit Ubuntu 24.04.4 LTS
| Command : report_utilization -file /home/ankaoc/Desktop/tmp/gps/targets/fpga/genesys2/out/reports/synth_utilization.rpt
| Design : genesys2_rocket_top
| Device : xc7k325tffg900-2
| Speed File : -2
@@ -31,17 +31,17 @@ Table of Contents
+----------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+-------+-------+------------+-----------+-------+
| Slice LUTs* | 62346 | 0 | 0 | 203800 | 30.59 |
| LUT as Logic | 61434 | 0 | 0 | 203800 | 30.14 |
| LUT as Memory | 912 | 0 | 0 | 64000 | 1.43 |
| LUT as Distributed RAM | 910 | 0 | | | |
| Slice LUTs* | 66125 | 0 | 0 | 203800 | 32.45 |
| LUT as Logic | 65217 | 0 | 0 | 203800 | 32.00 |
| LUT as Memory | 908 | 0 | 0 | 64000 | 1.42 |
| LUT as Distributed RAM | 906 | 0 | | | |
| LUT as Shift Register | 2 | 0 | | | |
| Slice Registers | 41428 | 0 | 0 | 407600 | 10.16 |
| Register as Flip Flop | 41419 | 0 | 0 | 407600 | 10.16 |
| Slice Registers | 52867 | 0 | 0 | 407600 | 12.97 |
| Register as Flip Flop | 52858 | 0 | 0 | 407600 | 12.97 |
| Register as Latch | 9 | 0 | 0 | 407600 | <0.01 |
| F7 Muxes | 1796 | 0 | 0 | 101900 | 1.76 |
| F8 Muxes | 142 | 0 | 0 | 50950 | 0.28 |
| Unique Control Sets | 1029 | | 0 | 50950 | 2.02 |
| F7 Muxes | 1956 | 0 | 0 | 101900 | 1.92 |
| F8 Muxes | 244 | 0 | 0 | 50950 | 0.48 |
| Unique Control Sets | 1095 | | 0 | 50950 | 2.15 |
+----------------------------+-------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
Warning! LUT value is adjusted to account for LUT combining.
@@ -61,10 +61,10 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 360 | Yes | - | Set |
| 30837 | Yes | - | Reset |
| 130 | Yes | Set | - |
| 10101 | Yes | Reset | - |
| 373 | Yes | - | Set |
| 42244 | Yes | - | Reset |
| 184 | Yes | Set | - |
| 10066 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -163,23 +163,23 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
+------------+-------+---------------------+
| Ref Name | Used | Functional Category |
+------------+-------+---------------------+
| FDCE | 30828 | Flop & Latch |
| LUT6 | 24589 | LUT |
| LUT2 | 15080 | LUT |
| LUT5 | 12169 | LUT |
| LUT3 | 10675 | LUT |
| FDRE | 10101 | Flop & Latch |
| LUT4 | 8029 | LUT |
| CARRY4 | 6055 | CarryLogic |
| LUT1 | 2902 | LUT |
| MUXF7 | 1796 | MuxFx |
| RAMD32 | 1360 | Distributed Memory |
| RAMS32 | 450 | Distributed Memory |
| FDCE | 42235 | Flop & Latch |
| LUT6 | 25074 | LUT |
| LUT2 | 16979 | LUT |
| LUT5 | 13248 | LUT |
| LUT3 | 10731 | LUT |
| FDRE | 10066 | Flop & Latch |
| LUT4 | 8858 | LUT |
| CARRY4 | 6514 | CarryLogic |
| LUT1 | 2938 | LUT |
| MUXF7 | 1956 | MuxFx |
| RAMD32 | 1350 | Distributed Memory |
| RAMS32 | 444 | Distributed Memory |
| RAMB36E1 | 415 | Block Memory |
| FDPE | 360 | Flop & Latch |
| FDPE | 373 | Flop & Latch |
| MUXF8 | 244 | MuxFx |
| DSP48E1 | 208 | Block Arithmetic |
| MUXF8 | 142 | MuxFx |
| FDSE | 130 | Flop & Latch |
| FDSE | 184 | Flop & Latch |
| IBUF | 16 | IO |
| OBUF | 13 | IO |
| LDCE | 9 | Flop & Latch |
targets/fpga/genesys2/out/reports/synth_utilization_hier.rpt
+573 -512
View File
File diff suppressed because it is too large Load Diff
targets/fpga/genesys2/tools/gen_genesys2_wrapper.py
+30 -2
View File
@@ -144,7 +144,11 @@ def main():
ports = parse_ports(args.rocket_top)
port_by_name = {name: (direction, width) for direction, width, name in ports}
top_passthrough_ports = {
name for name in ["pmod_spi_sck", "pmod_spi_csn", "pmod_irq", "gps_pps"]
name for name in [
"pmod_spi_sck", "pmod_spi_csn",
"max2771_spi_sclk", "max2771_spi_csn",
"pmod_irq", "gps_pps",
]
if name in port_by_name
}
@@ -212,6 +216,8 @@ def main():
continue
elif name == "pmod_spi_dq_i":
continue
elif name == "max2771_spi_sdata_i":
continue
elif name.startswith("mem_axi4_0_") or name.startswith("mmio_axi4_0_"):
continue
else:
@@ -363,6 +369,27 @@ def main():
assign pmod_spi_dq[3] = pmod_spi_dq_oe[3] ? pmod_spi_dq_o[3] : 1'bz;
"""
has_max2771_spi = all(name in port_by_name for name in [
"max2771_spi_sclk",
"max2771_spi_csn",
"max2771_spi_sdata_i",
"max2771_spi_sdata_o",
"max2771_spi_sdata_oe",
])
max2771_spi_top_ports = ""
max2771_spi_block = ""
if has_max2771_spi:
max2771_spi_top_ports = """\
output wire max2771_spi_sclk,
output wire max2771_spi_csn,
inout wire max2771_spi_sdata,
"""
max2771_spi_block = """\
assign max2771_spi_sdata_i = max2771_spi_sdata;
assign max2771_spi_sdata = max2771_spi_sdata_oe ? max2771_spi_sdata_o : 1'bz;
"""
pmod_irq_top_ports = ""
pmod_irq_block = ""
if "pmod_irq" in port_by_name:
@@ -546,7 +573,7 @@ module genesys2_rocket_top (
// Digilent labels these from the PC/FTDI side: TX_IN is FPGA RX, RX_OUT is FPGA TX.
input wire uart_tx_in,
output wire uart_rx_out,
{rf_top_ports}{eth_top_ports}{pmod_spi_top_ports}{pmod_irq_top_ports}{pps_top_ports}\
{rf_top_ports}{eth_top_ports}{pmod_spi_top_ports}{max2771_spi_top_ports}{pmod_irq_top_ports}{pps_top_ports}\
inout wire [3:0] qspi_d,
output wire qspi_csn,
output wire [7:0] led
@@ -806,6 +833,7 @@ module genesys2_rocket_top (
{bscan_block}
{startup_block}
{pmod_spi_block}
{max2771_spi_block}
{pmod_irq_block}
{chr(10).join(assigns)}
targets/fpga/vcu118/Makefile
+1
View File
@@ -229,6 +229,7 @@ chisel: software
"$(JAVA_HOME)/bin/java" \
-DROCKET_DTIM_BASE="$(DTIM_BASE)" \
-DROCKET_DTIM_SIZE="$(DTIM_SIZE)" \
-DROCKET_SOC_CLOCK_HZ="$(SOC_CLK_HZ)" \
-jar out/rocketchip/6.7.0/assembly.dest/out.jar \
--dir "$(FIRRTL_DIR)" \
--top freechips.rocketchip.fpga.VCU118RocketSystem \
targets/fpga/vcu118/README.md
+25
View File
@@ -163,6 +163,31 @@ J53 connector tarafi 3.3 V'tur; FPGA U1 tarafinda U42 level shifter sonrasi
`hardware/fpga/vcu118/constraints/vcu118_pmod_spi.xdc` dosyasindadir ve Vivado
akisi tarafindan her RF modunda okunur.
MAX2771 icin generic PMOD SPI'dan bagimsiz, 48-clock/tek-SDATA hatli bir IP
`0x10016000` adresindedir. PMOD0/J52'nin GPS RF tarafindan kullanilmayan son uc
hatti secilmistir. Bu hatlar U41 uzerinden connector tarafinda 3.3 V seviyesine
cevrilir. 100 MHz VCU118 fabric saatinden 13 fabric cycle yarim periyot ile
3.846 MHz SCLK uretilir.
```text
port FPGA pin PMOD pin yon
max2771_spi_sclk AU16 PMOD0_5 J52.4 output
max2771_spi_csn AT15 PMOD0_6 J52.6 output
max2771_spi_sdata AT16 PMOD0_7 J52.8 bidirectional
```
Constraintler `hardware/fpga/vcu118/constraints/vcu118_max2771_spi.xdc`
dosyasindadir. Ayni test uygulamasi hardware'in raporladigi board clock ve
SCLK degerlerini kontrol eder:
```bash
make -C targets/fpga/vcu118 debug-load APP=max2771_spi_test
```
EV kit uzerindeki MAX32625 PICO ayni uc SPI hattina baglidir. FPGA master
baglanirken PICO pinleri high-Z olmali veya PICO fiziksel olarak ayrilmali;
iki master ayni anda surulmemelidir.
Sensorden gelen external interrupt hatti SPI'dan bagimsizdir. `pmod_irq`
olarak PMOD1_6/J53.6'ya cikar ve PLIC'te `BSP_PMOD_IRQ` (`11`) ID'siyle
gorunur.
targets/fpga/vcu118/flow/vivado/scripts/build.tcl
+3
View File
@@ -159,6 +159,7 @@ read_verilog -sv $gps_files
puts "Reading VCU118 shell RTL..."
set shell_files [list \
[file join $hardware_dir ip max2771_spi rtl max2771_spi_engine.sv] \
[file join $hardware_dir fpga vcu118 rtl axi4_ram_64.sv] \
[file join $hardware_dir fpga vcu118 rtl axi4_slave_tieoff_64.sv] \
[file join $hardware_dir fpga vcu118 rtl rocket_bscan_dmi_tunnel.sv] \
@@ -185,6 +186,8 @@ puts "Reading constraints..."
read_xdc [file join $hardware_dir fpga vcu118 constraints vcu118_rocket.xdc]
puts "Reading VCU118 PMOD SPI constraints..."
read_xdc [file join $hardware_dir fpga vcu118 constraints vcu118_pmod_spi.xdc]
puts "Reading VCU118 MAX2771 SPI constraints..."
read_xdc [file join $hardware_dir fpga vcu118 constraints vcu118_max2771_spi.xdc]
puts "Reading VCU118 PMOD sensor IRQ constraints..."
read_xdc [file join $hardware_dir fpga vcu118 constraints vcu118_pmod_irq.xdc]
puts "Reading VCU118 PMOD PPS constraints..."
targets/fpga/vcu118/tools/gen_vcu118_wrapper.py
+30 -2
View File
@@ -143,7 +143,11 @@ def main():
return all(name in port_by_name for name in required)
top_passthrough_ports = {
name for name in ["pmod_spi_sck", "pmod_spi_csn", "pmod_irq", "gps_pps"]
name for name in [
"pmod_spi_sck", "pmod_spi_csn",
"max2771_spi_sclk", "max2771_spi_csn",
"pmod_irq", "gps_pps",
]
if name in port_by_name
}
assigns = []
@@ -210,6 +214,8 @@ def main():
continue
elif name == "pmod_spi_dq_i":
continue
elif name == "max2771_spi_sdata_i":
continue
elif name.startswith("mem_axi4_0_") or name.startswith("mmio_axi4_0_"):
continue
else:
@@ -395,6 +401,27 @@ def main():
assign pmod_spi_dq[3] = pmod_spi_dq_oe[3] ? pmod_spi_dq_o[3] : 1'bz;
"""
has_max2771_spi = all(name in port_by_name for name in [
"max2771_spi_sclk",
"max2771_spi_csn",
"max2771_spi_sdata_i",
"max2771_spi_sdata_o",
"max2771_spi_sdata_oe",
])
max2771_spi_top_ports = ""
max2771_spi_block = ""
if has_max2771_spi:
max2771_spi_top_ports = """\
output wire max2771_spi_sclk,
output wire max2771_spi_csn,
inout wire max2771_spi_sdata,
"""
max2771_spi_block = """\
assign max2771_spi_sdata_i = max2771_spi_sdata;
assign max2771_spi_sdata = max2771_spi_sdata_oe ? max2771_spi_sdata_o : 1'bz;
"""
pmod_irq_top_ports = ""
if "pmod_irq" in port_by_name:
pmod_irq_top_ports = """\
@@ -558,7 +585,7 @@ module vcu118_rocket_top (
input wire cpu_reset,
input wire rs232_uart_rxd,
output wire rs232_uart_txd,
{rf_top_ports}{eth_top_ports}{pmod_spi_top_ports}{pmod_irq_top_ports}{pps_top_ports}\
{rf_top_ports}{eth_top_ports}{pmod_spi_top_ports}{max2771_spi_top_ports}{pmod_irq_top_ports}{pps_top_ports}\
output wire [7:0] led
);
wire sysclk_300;
@@ -814,6 +841,7 @@ module vcu118_rocket_top (
{startup_block}
{pmod_spi_block}
{max2771_spi_block}
{eth_block}