124 lines
5.1 KiB
Scala
124 lines
5.1 KiB
Scala
// See LICENSE for license details.
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import microsites.{ConfigYml, MicrositeEditButton, MicrositeFavicon, ExtraMdFileConfig}
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import Version._
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val commonSettings = Seq.empty
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fork := true
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val technologies: String =
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"""|
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| - first: ["Scala", "Chisel is powered by Scala and brings all the power of object-oriented and functional programming to type-safe hardware design and generation."]
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| - second: ["Chisel", "Chisel, the Chisel standard library, and Chisel testing infrastructure enable agile, expressive, and reusable hardware design methodologies."]
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| - third: ["FIRRTL", "The FIRRTL circuit compiler starts after Chisel and enables backend (FPGA, ASIC, technology) specialization, automated circuit transformation, and Verilog generation."]
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|""".stripMargin
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val determineContributors = taskKey[Unit]("determine contributors for subprojects")
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lazy val micrositeSettings = Seq(
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scalaVersion := "2.12.12",
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micrositeName := "Chisel/FIRRTL",
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micrositeDescription := "Chisel/FIRRTL\nHardware Compiler Framework",
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micrositeUrl := "https://chipsalliance.github.io/",
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micrositeBaseUrl := "",
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micrositeConfigYaml := ConfigYml(
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yamlCustomProperties = Map("plugins" -> Seq("jekyll-redirect-from"))
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),
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micrositeAuthor := "the Chisel/FIRRTL Developers",
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micrositeTwitter := "@chisel_lang",
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micrositeGithubOwner := "chipsalliance",
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micrositeGithubRepo := "chisel",
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micrositeGithubLinks := false,
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micrositeShareOnSocial := false,
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micrositeDocumentationUrl := "chisel3/",
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micrositeDocumentationLabelDescription := "Documentation",
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micrositeGitterChannelUrl := "chipsalliance/chisel",
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micrositeHighlightLanguages ++= Seq("verilog"),
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mdocIn := file("docs/src/main/tut"),
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/* Copy markdown files from each of the submodules to build out the website:
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* - Chisel3 README becomes the landing page
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* - Other READMEs become the landing pages of each sub-project's documentation
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*/
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micrositeExtraMdFiles := Map(
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file("../README.md") -> ExtraMdFileConfig(
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"index.md", "home",
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Map("title" -> "Home",
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"section" -> "home",
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"technologies" -> technologies))
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),
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micrositeExtraMdFilesOutput := resourceManaged.value / "main" / "jekyll",
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micrositeStaticDirectory := file("docs/target/site/api"),
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/* Known colors:
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* - Chisel logo: #212560
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* - FIRRTL logo: #136527
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*/
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micrositeTheme := "pattern",
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micrositePalette := Map(
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"brand-primary" -> "#7B95A2",
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"brand-secondary" -> "#1A3C79",
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"brand-tertiary" -> "#1A1C54",
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"gray-dark" -> "#453E46",
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"gray" -> "#837F84",
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"gray-light" -> "#E3E2E3",
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"gray-lighter" -> "#F4F3F4",
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"white-color" -> "#FFFFFF"),
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micrositeAnalyticsToken := "UA-145179088-1",
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micrositeEditButton := None,
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autoAPIMappings := true,
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ghpagesNoJekyll := false,
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ghpagesRepository := file("build/gh-pages"),
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ghpagesBranch := "gh-pages",
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git.remoteRepo := "git@github.com:chipsalliance/chisel.git",
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includeFilter in makeSite := "*.html" | "*.css" | "*.png" | "*.jpg" | "*.gif" | "*.js" | "*.swf" | "*.yml" | "*.md" |
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"*.svg" | "*.woff" | "*.ttf",
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includeFilter in Jekyll := (includeFilter in makeSite).value,
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excludeFilter in ghpagesCleanSite :=
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new FileFilter{
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def accept(f: File) = (ghpagesRepository.value / "CNAME").getCanonicalPath == f.getCanonicalPath
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} || "versions.html",
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addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full)
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)
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resolvers ++= Seq(
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Resolver.sonatypeRepo("snapshots"),
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Resolver.sonatypeRepo("releases")
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)
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lazy val contributors =
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project
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.settings(
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determineContributors := {
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import java.io.{File, PrintWriter}
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val uniqueContributors =
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// Even though we no longer host all these projects,
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// we still honor their contributions
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Seq( GitHubRepository("chipsalliance", "chisel"),
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GitHubRepository("chipsalliance", "firrtl"),
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GitHubRepository("chipsalliance", "treadle"),
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GitHubRepository("ucb-bar", "chiseltest"),
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GitHubRepository("ucb-bar", "chisel2-deprecated"),
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GitHubRepository("freechipsproject", "chisel-bootcamp"),
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GitHubRepository("freechipsproject", "chisel-template"),
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GitHubRepository("freechipsproject", "chisel-testers"),
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GitHubRepository("freechipsproject", "diagrammer"),
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GitHubRepository("freechipsproject", "firrtl-interpreter"),
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GitHubRepository("freechipsproject", "www.chisel-lang.org") )
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.flatMap(Contributors.contributors)
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.map(b => (b.login, b.html_url))
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.distinct
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val writer = new PrintWriter(new File("docs/src/main/tut/contributors.md"))
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writer.write(s"""|<!-- Automatically generated by build.sbt 'contributors' task -->
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|${Contributors.contributorsMarkdown(uniqueContributors)}""".stripMargin)
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writer.close()
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}
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)
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lazy val docs = project
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.enablePlugins(MicrositesPlugin)
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.settings(commonSettings)
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.settings(micrositeSettings)
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.settings(scalacOptions ++= (Seq("-Xsource:2.11")))
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.dependsOn(contributors)
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