gps/targets/fpga/vcu118

VCU118 Rocket FPGA Flow

Bu dizin VCU118 uzerinde Rocket SoC uretmek, bitstream almak ve kart flash'ina bitstream/app image yazmak icin sade bir make agaci saglar.

Dizinler

soc/
  Makefile                  # ortak SoC girisi
  software/                 # bootloader, BSP ve bare-metal uygulamalar
  out/                      # ortak ELF, BootROM ve app flash imajlari

hardware/
  upstream/rocket-chip/     # upstream Rocket Scala/resources symlink gorunumu
  soc/scala/                # proje Scala/Chisel Rocket SoC katmani
  generated/                # FIRRTL ve split SystemVerilog dump alani
  fpga/vcu118/rtl/          # FPGA shell yardimci RTL
  fpga/vcu118/constraints/  # VCU118 XDC
  sim/fpga/vcu118/          # FPGA smoke/sim girisi
  external/gps/rtl/         # GPS RTL kaynaklari ve filelist

targets/fpga/vcu118/
  Makefile                  # VCU118 FPGA akisi giris noktasi
  docs/                     # detayli HTML dokuman
  flow/vivado/              # Vivado non-project Make/Tcl akisi
  tools/                    # VCU118 wrapper generator
  out/                      # uretilen tum FPGA ciktilari
    bitstream/
    build/
    flash/
    logs/
    reports/

Ana Komutlar

Her katman kendi klasorunden de calistirilabilir:

make -C soc hw
make -C soc/software all
make -C hardware/soc firrtl
make -C hardware/fpga/vcu118/rtl generated
make -C targets/fpga/vcu118/flow/vivado bitstream
make -C targets/fpga/vcu118/flow/vivado flash-app
make -C hardware/sim/fpga/vcu118 smoke

Kok Makefile ayni hedefleri tek yerden de sunar:

make -C targets/fpga/vcu118 software
make -C targets/fpga/vcu118 chisel
make -C targets/fpga/vcu118 rtl
make -C targets/fpga/vcu118 soc
make -C targets/fpga/vcu118 bitstream
make -C targets/fpga/vcu118 program-fpga
make -C targets/fpga/vcu118 program-flash
make -C targets/fpga/vcu118 program-flash-bitstream
make -C targets/fpga/vcu118 program-flash-combined
make -C targets/fpga/vcu118 prune

Gundelik uygulama gelistirme icin:

make -C targets/fpga/vcu118 program-flash
make -C targets/fpga/vcu118 program-fpga

Bitstream SRAM'e atildiktan sonra GDB ile RAM'e uygulama yuklemek icin:

make -C targets/fpga/vcu118 debug-openocd
make -C targets/fpga/vcu118 uart-listen UART_PORT=/dev/ttyUSB2
make -C targets/fpga/vcu118 debug-load APP=hello_uart
make -C targets/fpga/vcu118 debug-load APP=gps_system

Bu akista OpenOCD, Xilinx BSCAN uzerinden Rocket DMI portuna gider. FPGA bitstream'inde rocket_bscan_dmi_tunnel.sv bulunmalidir.

RF girisi

SoC/fabric saati kartin 300 MHz kristalinden uretilmeye devam eder. GPS acquisition ve tracking/PPS saatleri secili RF sample clock'tan beslenen iki MMCM kademesinden uretilir. Varsayilan 16.367981 MHz RF referansi once 55.555556 MHz'e, ardindan 100 MHz acquisition ve 125 MHz tracking saatine cevrilir; nominal tracking oran hatasi yaklasik 0.007 ppm'dir. Reset ancak fabric ve iki GPS MMCM lock olduktan sonra kalkar.

RF, acquisition ve tracking domainleri ortak frekans referansina ragmen CDC sinirlaridir. Vivado timing scripti bunlari ayri asynchronous gruplar olarak tutar; bu ayar RF-referansli frekans coherency'sini degil, mevcut CDC protokolunun analiz modelini ifade eder.

VCU118 FPGA top'u tools/gen_vcu118_wrapper.py ile uretilir. RF kaynagi RF_INPUT_MODE ile secilir:

pmod       Varsayilan. Harici RF clock + 4-bit RF data PMOD0/J52'den SoC GPS RF portuna gider ve GPS PLL'lerini referanslar.
generated  Dahili RF clock uretilir, RF data 4'd0 olur.
ethernet   Eski raw-Ethernet RF streamer path'i ve PCS/PMA IP aktif olur.

Varsayilan PMOD akisi:

make -C targets/fpga/vcu118 bitstream

Eski Ethernet RF akisi sadece RF_INPUT_MODE=ethernet bitstream ile kullanilir:

make -C targets/fpga/vcu118 bitstream RF_INPUT_MODE=ethernet
sudo make -C targets/fpga/vcu118 eth-rf-send

pmod ve generated modlarinda Vivado flow Ethernet PCS/PMA IP'yi uretmez, hardware/fpga/vcu118/rtl/ethernet_rf altindaki RTL'i okumaz ve top-level Ethernet PHY portlarini olusturmaz.

PMOD0/J52 connector tarafi 3.3 V'tur. FPGA U1 tarafinda U41 level shifter nedeniyle pinler 1.8 V bankta LVCMOS18 olarak constrain edilir:

port              FPGA pin  PMOD pin       FPGA I/O   PMOD header level
rf_clk_pmod       AY14      PMOD0_0 J52.1  LVCMOS18   3.3 V
rf_data_pmod[0]   AY15      PMOD0_1 J52.3  LVCMOS18   3.3 V
rf_data_pmod[1]   AW15      PMOD0_2 J52.5  LVCMOS18   3.3 V
rf_data_pmod[2]   AV15      PMOD0_3 J52.7  LVCMOS18   3.3 V
rf_data_pmod[3]   AV16      PMOD0_4 J52.2  LVCMOS18   3.3 V

Disaridan sinyal baglarken 3.3 V seviyeyi J52 PMOD header tarafina ver. FPGA U1 package pinlerine dogrudan 3.3 V uygulanmaz; o tarafta level shifter sonrasi LVCMOS18 vardir.

PMOD pin constraintleri hardware/fpga/vcu118/constraints/vcu118_pmod_rf.xdc dosyasindadir ve sadece RF_INPUT_MODE=pmod iken okunur. Ethernet PHY pinleri ise hardware/fpga/vcu118/constraints/vcu118_ethernet.xdc altindadir ve sadece RF_INPUT_MODE=ethernet iken okunur.

PMOD SPI portu her RF modunda aktiftir. SoC register adresi 0x10015000'dir; kart konfig flash'ina bagli mevcut SPI 0x10014000 adresinde kalir. SPI, RF icin kullanilan PMOD0/J52 yerine PMOD1/J53'e atanir. Driver single/quad calisma modunu secer; single modda sadece dq[0] MOSI ve dq[1] MISO kullanilir.

port              FPGA pin  PMOD pin
pmod_spi_csn      N28       PMOD1_0 J53.1
pmod_spi_dq[0]    M30       PMOD1_1 J53.3 MOSI
pmod_spi_dq[1]    N30       PMOD1_2 J53.5 MISO
pmod_spi_sck      P30       PMOD1_3 J53.7 SCK
pmod_spi_dq[2]    P29       PMOD1_4 J53.2
pmod_spi_dq[3]    L31       PMOD1_5 J53.4

J53 connector tarafi 3.3 V'tur; FPGA U1 tarafinda U42 level shifter sonrasi LVCMOS12 kullanilir. Pin constraintleri hardware/fpga/vcu118/constraints/vcu118_pmod_spi.xdc dosyasindadir ve Vivado akisi tarafindan her RF modunda okunur.

MAX2771 icin generic PMOD SPI'dan bagimsiz, 48-clock/tek-SDATA hatli bir IP 0x10016000 adresindedir. PMOD0/J52'nin GPS RF tarafindan kullanilmayan son uc hatti secilmistir. Bu hatlar U41 uzerinden connector tarafinda 3.3 V seviyesine cevrilir. 100 MHz VCU118 fabric saatinden 13 fabric cycle yarim periyot ile 3.846 MHz SCLK uretilir.

port                 FPGA pin  PMOD pin       yon
max2771_spi_sclk     AU16      PMOD0_5 J52.4 output
max2771_spi_csn      AT15      PMOD0_6 J52.6 output
max2771_spi_sdata    AT16      PMOD0_7 J52.8 bidirectional

Constraintler hardware/fpga/vcu118/constraints/vcu118_max2771_spi.xdc dosyasindadir. Ayni test uygulamasi hardware'in raporladigi board clock ve SCLK degerlerini kontrol eder:

make -C targets/fpga/vcu118 debug-load APP=max2771_spi_test

EV kit uzerindeki MAX32625 PICO ayni uc SPI hattina baglidir. FPGA master baglanirken PICO pinleri high-Z olmali veya PICO fiziksel olarak ayrilmali; iki master ayni anda surulmemelidir.

Sensorden gelen external interrupt hatti SPI'dan bagimsizdir. pmod_irq olarak PMOD1_6/J53.6'ya cikar ve PLIC'te BSP_PMOD_IRQ (11) ID'siyle gorunur.

port       FPGA pin  PMOD pin
pmod_irq  M31       PMOD1_6 J53.6

Pin constraintleri hardware/fpga/vcu118/constraints/vcu118_pmod_irq.xdc dosyasindadir ve Vivado akisi tarafindan her RF modunda okunur.

fpga-config ve help ciktisi aktif RF_INPUT_MODE degerini gosterir.

Bitstream flash'a kalici yazilacaksa, uzun suren tek seferlik hedef:

make -C targets/fpga/vcu118 program-flash-bitstream

Gereksiz buyuk ara ciktilari temizlemek, ama mevcut bitstream/app ciktilarini korumak icin:

make -C targets/fpga/vcu118 prune

Detayli aciklama:

targets/fpga/vcu118/docs/vcu118_rocket_flash_boot_guide.html