19 lines
624 B
Makefile
19 lines
624 B
Makefile
.PHONY: help all smoke clean
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help:
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@echo "VCU118 simulation targets:"
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@echo " make smoke # generate RTL and check expected generated files exist"
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@echo " make clean # remove generated simulation inputs"
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@echo ""
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@echo "A full Verilator/FPGA-board simulation harness has not been added yet."
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all: smoke
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smoke:
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@make -C ../../../../targets/fpga/vcu118 rtl
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test -f ../../../generated/vcu118-soc-verilog/VCU118RocketSystem.sv
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test -f ../../../../targets/fpga/vcu118/out/build/generated/vcu118_rocket_top.sv
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clean:
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rm -rf ../../../generated/vcu118-soc-verilog ../../../../targets/fpga/vcu118/out/build/generated
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