155 lines
6.3 KiB
C++
155 lines
6.3 KiB
C++
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|* AttrDef Declarations *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_ATTRDEF_CLASSES
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#undef GET_ATTRDEF_CLASSES
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namespace mlir {
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class AsmParser;
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class AsmPrinter;
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} // namespace mlir
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namespace mlir::amdgpu {
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/// AMDGPU-specific address spaces
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/// AMDGPU-specific memory spaces that may not have exact analogues on other
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/// GPU targets or backends.
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///
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/// - `fat_raw_buffer` is the memory space used when a memref is stored as
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/// as a "buffer fat pointer" - that is, a buffer resource (that is set up to
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/// use raw byte-level indexing) along with its offset. The AMDGPU backend
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/// implements `ptr addrspace(7)` to represent these fat pointers so that
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/// buffer resources (which allow advanced features like bounds checking or
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/// cache swizzling) can be used like ordinary LLVM pointers or memrefs.
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/// See also the `fat_raw_buffer_cast` operation
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/// - `buffer_rsrc` is the memory space for `ptr addrspace(8)`, representing a
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/// buffer resource. It should not be used for memrefs, since it does not support
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/// indexing
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/// - `fat_structured_buffer` represents `ptr addrspace(9)`, a buffer resource
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/// that carries both an index and offset field, which are used for complex
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/// structured indexing that is primarily seen in graphics applications. This
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/// is also incompatible with the simple indexing model supported by memref.
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class AddressSpaceAttr;
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/// The possible permutations for a DPP operation
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/// Enum cases:
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/// * quad_perm (`quad_perm`)
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/// * row_shl (`row_shl`)
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/// * row_shr (`row_shr`)
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/// * row_ror (`row_ror`)
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/// * wave_shl (`wave_shl`)
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/// * wave_shr (`wave_shr`)
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/// * wave_ror (`wave_ror`)
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/// * wave_rol (`wave_rol`)
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/// * row_mirror (`row_mirror`)
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/// * row_half_mirror (`row_half_mirror`)
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/// * row_bcast_15 (`row_bcast_15`)
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/// * row_bcast_31 (`row_bcast_31`)
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class DPPPermAttr;
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/// AMDGPU-specific prefetch temporal hints for load instructions. RT - regular temporal for both near and far caches; NT - non-temporal for both near and far caches; HT - high-priority temporal for both near and far caches; LU - last-use; NT_RT - non-temporal for near cache(s) and regular for far caches; RT_NT - regular for near cache(s) and non-temporal for far caches; NT_HT - non-temporal for near cache(s) and high-priority temporal for far caches
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/// Enum cases:
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/// * RT (`RT`)
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/// * NT (`NT`)
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/// * HT (`HT`)
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/// * LU (`LU`)
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/// * NT_RT (`NT_RT`)
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/// * RT_NT (`RT_NT`)
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/// * NT_HT (`NT_HT`)
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class LoadTemporalHintAttr;
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/// AMDGPU-specific cache scopes. WGP - workgroup processor (CUs); SE - shader engine (GL2); DEV - device; SYS - system
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/// Enum cases:
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/// * WGP (`WGP`)
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/// * SE (`SE`)
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/// * DEV (`DEV`)
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/// * SYS (`SYS`)
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class ScopeAttr;
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namespace detail {
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struct AddressSpaceAttrStorage;
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} // namespace detail
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class AddressSpaceAttr : public ::mlir::Attribute::AttrBase<AddressSpaceAttr, ::mlir::Attribute, detail::AddressSpaceAttrStorage> {
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public:
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using Base::Base;
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static constexpr ::llvm::StringLiteral name = "amdgpu.address_space";
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static constexpr ::llvm::StringLiteral dialectName = "amdgpu";
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static AddressSpaceAttr get(::mlir::MLIRContext *context, ::mlir::amdgpu::AddressSpace value);
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static constexpr ::llvm::StringLiteral getMnemonic() {
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return {"address_space"};
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}
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static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
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void print(::mlir::AsmPrinter &odsPrinter) const;
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::mlir::amdgpu::AddressSpace getValue() const;
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};
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namespace detail {
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struct DPPPermAttrStorage;
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} // namespace detail
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class DPPPermAttr : public ::mlir::Attribute::AttrBase<DPPPermAttr, ::mlir::Attribute, detail::DPPPermAttrStorage> {
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public:
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using Base::Base;
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static constexpr ::llvm::StringLiteral name = "amdgpu.dpp_perm";
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static constexpr ::llvm::StringLiteral dialectName = "amdgpu";
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static DPPPermAttr get(::mlir::MLIRContext *context, ::mlir::amdgpu::DPPPerm value);
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static constexpr ::llvm::StringLiteral getMnemonic() {
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return {"dpp_perm"};
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}
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static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
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void print(::mlir::AsmPrinter &odsPrinter) const;
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::mlir::amdgpu::DPPPerm getValue() const;
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};
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namespace detail {
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struct LoadTemporalHintAttrStorage;
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} // namespace detail
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class LoadTemporalHintAttr : public ::mlir::Attribute::AttrBase<LoadTemporalHintAttr, ::mlir::Attribute, detail::LoadTemporalHintAttrStorage> {
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public:
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using Base::Base;
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static constexpr ::llvm::StringLiteral name = "amdgpu.load_temporal_hint";
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static constexpr ::llvm::StringLiteral dialectName = "amdgpu";
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static LoadTemporalHintAttr get(::mlir::MLIRContext *context, ::mlir::amdgpu::LoadTemporalHint value);
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static constexpr ::llvm::StringLiteral getMnemonic() {
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return {"load_temporal_hint"};
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}
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static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
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void print(::mlir::AsmPrinter &odsPrinter) const;
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::mlir::amdgpu::LoadTemporalHint getValue() const;
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};
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namespace detail {
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struct ScopeAttrStorage;
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} // namespace detail
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class ScopeAttr : public ::mlir::Attribute::AttrBase<ScopeAttr, ::mlir::Attribute, detail::ScopeAttrStorage> {
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public:
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using Base::Base;
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static constexpr ::llvm::StringLiteral name = "amdgpu.cache_scope";
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static constexpr ::llvm::StringLiteral dialectName = "amdgpu";
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static ScopeAttr get(::mlir::MLIRContext *context, ::mlir::amdgpu::Scope value);
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static constexpr ::llvm::StringLiteral getMnemonic() {
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return {"cache_scope"};
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}
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static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
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void print(::mlir::AsmPrinter &odsPrinter) const;
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::mlir::amdgpu::Scope getValue() const;
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};
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} // namespace mlir::amdgpu
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MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::amdgpu::AddressSpaceAttr)
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MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::amdgpu::DPPPermAttr)
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MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::amdgpu::LoadTemporalHintAttr)
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MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::amdgpu::ScopeAttr)
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#endif // GET_ATTRDEF_CLASSES
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