onur
172 lines
6.7 KiB
Systemverilog
172 lines
6.7 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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// Users can define 'PRINTF_COND' to add an extra gate to prints.
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`ifndef PRINTF_COND_
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`ifdef PRINTF_COND
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`define PRINTF_COND_ (`PRINTF_COND)
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`else // PRINTF_COND
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`define PRINTF_COND_ 1
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`endif // PRINTF_COND
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`endif // not def PRINTF_COND_
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module SBToTL(
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input clock,
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reset,
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auto_out_a_ready,
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output auto_out_a_valid,
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output [2:0] auto_out_a_bits_opcode,
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output [3:0] auto_out_a_bits_size,
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output [31:0] auto_out_a_bits_address,
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output [7:0] auto_out_a_bits_data,
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output auto_out_d_ready,
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input auto_out_d_valid,
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input [2:0] auto_out_d_bits_opcode,
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input [1:0] auto_out_d_bits_param,
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input [3:0] auto_out_d_bits_size,
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input auto_out_d_bits_sink,
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auto_out_d_bits_denied,
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input [7:0] auto_out_d_bits_data,
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input auto_out_d_bits_corrupt,
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io_rdEn,
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io_wrEn,
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input [127:0] io_addrIn,
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io_dataIn,
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input [2:0] io_sizeIn,
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output io_rdLegal,
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io_wrLegal,
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io_rdDone,
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io_wrDone,
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io_respError,
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output [7:0] io_dataOut,
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output io_rdLoad_0,
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io_rdLoad_1,
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io_rdLoad_2,
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io_rdLoad_3,
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io_rdLoad_4,
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io_rdLoad_5,
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io_rdLoad_6,
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io_rdLoad_7,
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output [2:0] io_sbStateOut
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);
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wire _d_q_io_deq_valid;
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wire _d_q_io_deq_bits_denied;
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wire _d_q_io_deq_bits_corrupt;
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reg [2:0] sbState;
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wire _rdTxValid_T = sbState == 3'h3;
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wire _io_wrDone_T = sbState == 3'h4;
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wire d_q_io_deq_ready = _rdTxValid_T | _io_wrDone_T;
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reg [3:0] counter;
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wire [7:0][7:0] _GEN =
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{{io_dataIn[63:56]},
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{io_dataIn[55:48]},
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{io_dataIn[47:40]},
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{io_dataIn[39:32]},
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{io_dataIn[31:24]},
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{io_dataIn[23:16]},
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{io_dataIn[15:8]},
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{io_dataIn[7:0]}};
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wire _GEN_0 = |(io_addrIn[127:12]);
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wire _GEN_1 = |{io_addrIn[127:14], ~(io_addrIn[13:12])};
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wire _GEN_2 = |{io_addrIn[127:26], io_addrIn[25:16] ^ 10'h200};
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wire _GEN_3 = |{io_addrIn[127:28], ~(io_addrIn[27:26])};
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wire _GEN_4 = |{io_addrIn[127:29], io_addrIn[28:12] ^ 17'h10013};
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wire _GEN_5 = |{io_addrIn[127:29], io_addrIn[28:13] ^ 16'h800A};
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wire _GEN_6 = |{io_addrIn[127:29], io_addrIn[28:15] ^ 14'h2004};
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wire _GEN_7 = |{io_addrIn[127:29], io_addrIn[28:13] ^ 16'h8014};
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wire _GEN_8 = |{io_addrIn[127:29], io_addrIn[28:12] ^ 17'h1002A};
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wire _GEN_9 = |{io_addrIn[127:32], io_addrIn[31:20] ^ 12'h800};
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wire io_rdLegal_0 =
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~_GEN_0 | ~_GEN_1 | {io_addrIn[127:17], ~(io_addrIn[16])} == 112'h0 | ~_GEN_2
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| ~_GEN_3 | ~_GEN_4 | ~_GEN_5 | ~_GEN_6 | ~_GEN_7 | ~_GEN_8 | ~_GEN_9;
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wire io_wrLegal_0 =
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~_GEN_0 | ~_GEN_1 | ~_GEN_2 | ~_GEN_3 | ~_GEN_4 | ~_GEN_5 | ~_GEN_6 | ~_GEN_7
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| ~_GEN_8 | ~_GEN_9;
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wire _nodeOut_a_valid_T = sbState == 3'h1;
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wire _nodeOut_a_valid_T_1 = sbState == 3'h2;
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wire rdTxValid = _rdTxValid_T & _d_q_io_deq_valid & d_q_io_deq_ready;
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wire txLast = {4'h0, counter} == (8'h1 << io_sizeIn) - 8'h1;
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wire _GEN_10 = sbState == 3'h0;
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wire nodeOut_a_valid = _nodeOut_a_valid_T | _nodeOut_a_valid_T_1;
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wire _GEN_11 =
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_GEN_10 | _nodeOut_a_valid_T | _nodeOut_a_valid_T_1 | _rdTxValid_T | _io_wrDone_T;
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`ifndef SYNTHESIS
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always @(posedge clock) begin
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if ((`PRINTF_COND_) & ~reset & ~_GEN_11)
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$fwrite(32'h80000002,
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"Assertion failed: SBA state machine in undefined state\n at SBA.scala:373 assert (sbState === Idle.id.U ||\n");
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end // always @(posedge)
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`endif // not def SYNTHESIS
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always @(posedge clock) begin
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if (reset) begin
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sbState <= 3'h0;
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counter <= 4'h0;
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end
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else begin
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automatic logic wrTxValid;
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automatic logic _counter_T_2;
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wrTxValid = _nodeOut_a_valid_T_1 & nodeOut_a_valid & auto_out_a_ready;
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_counter_T_2 = wrTxValid | rdTxValid;
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if (_GEN_10) begin
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if (io_rdEn & io_rdLegal_0)
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sbState <= 3'h1;
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else if (io_wrEn & io_wrLegal_0)
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sbState <= 3'h2;
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end
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else if (_nodeOut_a_valid_T) begin
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if (nodeOut_a_valid & auto_out_a_ready)
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sbState <= 3'h3;
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end
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else if (_nodeOut_a_valid_T_1) begin
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if (wrTxValid & txLast)
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sbState <= 3'h4;
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end
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else if (_rdTxValid_T
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? rdTxValid & txLast
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: _io_wrDone_T & _d_q_io_deq_valid & d_q_io_deq_ready)
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sbState <= 3'h0;
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if (_counter_T_2 & txLast)
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counter <= 4'h0;
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else if (_counter_T_2)
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counter <= counter + 4'h1;
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end
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end // always @(posedge)
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Queue2_TLBundleD_a32d8s1k1z4u d_q (
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.clock (clock),
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.reset (reset),
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.io_enq_ready (auto_out_d_ready),
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.io_enq_valid (auto_out_d_valid),
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.io_enq_bits_opcode (auto_out_d_bits_opcode),
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.io_enq_bits_param (auto_out_d_bits_param),
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.io_enq_bits_size (auto_out_d_bits_size),
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.io_enq_bits_sink (auto_out_d_bits_sink),
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.io_enq_bits_denied (auto_out_d_bits_denied),
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.io_enq_bits_data (auto_out_d_bits_data),
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.io_enq_bits_corrupt (auto_out_d_bits_corrupt),
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.io_deq_ready (d_q_io_deq_ready),
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.io_deq_valid (_d_q_io_deq_valid),
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.io_deq_bits_denied (_d_q_io_deq_bits_denied),
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.io_deq_bits_data (io_dataOut),
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.io_deq_bits_corrupt (_d_q_io_deq_bits_corrupt)
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);
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assign auto_out_a_valid = nodeOut_a_valid;
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assign auto_out_a_bits_opcode = {_nodeOut_a_valid_T, 2'h0};
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assign auto_out_a_bits_size = {1'h0, io_sizeIn};
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assign auto_out_a_bits_address = io_addrIn[31:0];
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assign auto_out_a_bits_data = _nodeOut_a_valid_T ? 8'h0 : _GEN[counter[2:0]];
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assign io_rdLegal = io_rdLegal_0;
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assign io_wrLegal = io_wrLegal_0;
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assign io_rdDone = rdTxValid & txLast;
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assign io_wrDone = _io_wrDone_T & _d_q_io_deq_valid & d_q_io_deq_ready;
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assign io_respError = _d_q_io_deq_bits_denied | _d_q_io_deq_bits_corrupt;
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assign io_rdLoad_0 = rdTxValid & counter == 4'h0;
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assign io_rdLoad_1 = rdTxValid & counter == 4'h1;
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assign io_rdLoad_2 = rdTxValid & counter == 4'h2;
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assign io_rdLoad_3 = rdTxValid & counter == 4'h3;
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assign io_rdLoad_4 = rdTxValid & counter == 4'h4;
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assign io_rdLoad_5 = rdTxValid & counter == 4'h5;
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assign io_rdLoad_6 = rdTxValid & counter == 4'h6;
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assign io_rdLoad_7 = rdTxValid & counter == 4'h7;
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assign io_sbStateOut = sbState;
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endmodule
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