42 lines
1.8 KiB
Markdown
42 lines
1.8 KiB
Markdown
# Project Layout
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This tree keeps upstream Rocket Chip code, project hardware, software, target
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flows, and local tools in separate functional areas.
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```text
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dependencies/ Chisel, diplomacy, cde, hardfloat build dependencies
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hardware/ All project hardware sources, dumps, sim assets
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upstream/rocket-chip/src/ Required upstream Rocket-Chip Scala/resources
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upstream/rocket-chip/bootrom/
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Required upstream default BootROM image/source
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soc/scala/ Project Rocket SoC Chisel/Scala layer
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generated/ FIRRTL and split SystemVerilog dump area
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fpga/vcu118/rtl/ Hand-written VCU118 shell/helper RTL
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fpga/vcu118/constraints/ VCU118 XDC constraints
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fpga/genesys2/rtl/ Hand-written Genesys2 shell/helper RTL
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fpga/genesys2/constraints/ Genesys2 XDC constraints
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sim/fpga/vcu118/ FPGA-oriented smoke/sim entry points
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sim/asic/rocket/ ASIC testbench, models, and wave setup
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external/gps/rtl/ GPS RTL sources and file list used by FPGA/ASIC
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soc/software/ Bootloader, BSP, bare-metal apps, flash image tools
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gps_system/ GPS bare-metal acquisition/tracking/navigation app
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targets/fpga/vcu118/ VCU118 build/programming flow entry point
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targets/fpga/genesys2/ Genesys2 build/programming flow entry point
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flow/debug/ OpenOCD BSCAN and GDB load scripts
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targets/asic/rocket/ ASIC wrapper/filelist/simulation flow entry point
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tools/local/ Local mill, JDK, firtool/CIRCT, and Z3 installs
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```
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Generated/cache directories are disposable:
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```text
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out/
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soc/out/
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hardware/generated/
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targets/**/out/
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targets/**/work/
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.Xil/
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cong/
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tools/local/*-download/
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```
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