gps/README.md

Rocket Project

Bu agac VCU118/Genesys2 FPGA ve ASIC-style Rocket akislari icin sade proje duzenidir. Upstream Rocket-Chip kaynaklari daginik kok klasorlerde tutulmaz; gerekli upstream kaynaklar hardware/upstream/rocket-chip/ altindadir.

Kisa Harita

hardware/
  soc/scala/                  Proje Scala/Chisel SoC katmani
  generated/                  FIRRTL ve SystemVerilog dump alani
  fpga/vcu118/rtl/            VCU118 ek RTL
  fpga/vcu118/constraints/    VCU118 XDC
  fpga/genesys2/rtl/          Genesys2 ek RTL
  fpga/genesys2/constraints/  Genesys2 XDC
  sim/fpga/vcu118/            FPGA smoke/sim girisi
  sim/asic/rocket/            ASIC testbench, modeller, wave.do
  external/gps/rtl/           GPS RTL kaynaklari ve filelist
  upstream/rocket-chip/       Gerekli upstream Rocket-Chip src ve bootrom

soc/software/                 Bootloader, BSP, uygulamalar, flash image tool
targets/fpga/vcu118/          VCU118 build/programlama akisi
targets/fpga/genesys2/        Genesys2 build/programlama akisi
targets/asic/rocket/          ASIC wrapper/filelist/sim akisi
setup_tools.sh                /tools/soc-tools host araci kurulum betigi

Gelistirme Araclari

Mill, JDK, CIRCT/firtool ve Z3 makineye/işletim sistemine ozel binary paketlerdir; Git'e eklenmezler. Linux x86-64 host araclarini sabit surum ve SHA256 kontrolleriyle /tools/soc-tools altina kurmak icin:

./setup_tools.sh

Proje araclarini ve RISC-V bare-metal toolchain'i shell'e eklemek icin:

source source.sh
make doctor

source.sh, RISC-V GCC'yi sirasiyla RISCV_TOOLCHAIN, TOOLCHAIN, proje-ici tools/local/riscv/bin, /tools/toolchain/bin, /tools/toolchains/bin ve PATH icinde arar. Standart olmayan bir kurulum icin:

RISCV_TOOLCHAIN=/opt/riscv source source.sh

Ayni ayar shell'i degistirmeden Make'e de verilebilir:

make fpga-rtl RISCV_TOOLCHAIN=/opt/riscv

setup_tools.sh host tarafindaki Scala/Chisel uretim araclarini kurar. RISC-V bare-metal toolchain buyuk ve ayri bir urun oldugu icin indirilmez; source.sh tarafindan mevcut /tools/toolchains kurulumundan veya RISCV_TOOLCHAIN degiskeninden bulunur.

Ana Komutlar

make help
make fpga-rtl
make fpga-bitstream
make fpga-elf-flash-image
make fpga-mcs
make fpga-program
make fpga-flash
make fpga-flash-bitstream
make fpga-flash-mcs
make fpga-flash-all
make asic-rtl
make asic-sim

GPS bare-metal uygulamasini derlemek ve FPGA uzerinde GDB ile RAM'e yuklemek:

make -C soc/software app APP=gps_system
make -C targets/fpga/vcu118 debug-load APP=gps_system

GPS Firmware Profilleri: ESKF ve GPS-only

gps_system varsayilan olarak ESKF acik (GPS_ESKF_ENABLE=1) ve UART 460800 baud olacak sekilde derlenir. Kok Makefile'in kart varsayilani VCU118 oldugu icin Genesys2 komutlarinda FPGA_BOARD=genesys2 acikca yazilmalidir.

TDK ICM42688 + GPS + ESKF iceren birlesik Genesys2 MCS/BIN:

make FPGA_BOARD=genesys2 APP=gps_system \
  GPS_ESKF_ENABLE=1 IMU_SENSOR=tdk fpga-mcs

Yalniz GPS acquisition/tracking, WLS, Doppler velocity ve PPS calistiran; IMU/ESKF baslatmayan firmware:

make FPGA_BOARD=genesys2 APP=gps_system \
  GPS_ESKF_ENABLE=0 fpga-mcs

GPS_ESKF_ENABLE verilmezse deger 1'dir. Iki komut ayni targets/fpga/genesys2/out/flash/genesys2_rocket.mcs ve .bin yollarini kullanir; ikinci build birincinin ciktisinin uzerine yazar. Iki profili saklamak gerekiyorsa her build'den sonra dosyayi profil adiyla kopyalayin.

Cold scan, sky-guided search, independent unknown-orbit discovery, hot reacquisition, ephemeris cache ve mevcut almanak siniri dahil acquisition algoritmasinin tam aciklamasi soc/software/gps_system/README.md altindadir.

fpga-mcs mevcut .bit dosyasini kullanip bootloader ve uygulamayi yeniden derler. Yalniz software profili veya baud degisikligi icin sentez gerekmez. Tracking/PPS RTL veya Chisel degistiyse once:

make FPGA_BOARD=genesys2 APP=gps_system fpga-bitstream
make FPGA_BOARD=genesys2 APP=gps_system GPS_ESKF_ENABLE=1 \
  IMU_SENSOR=tdk fpga-mcs

Firmware ve host UART dinleyicisinin varsayilani birlikte 460800'dur:

make FPGA_BOARD=genesys2 fpga-uart

Doppler, WLS ve ESKF veri yolu

tracking loop, her 20 ms:
  carrier Q7 + 20 prompt I/Q + wideband power + ABS_SAMPLE/code phase
      -> sabit tracking snapshot
      -> synchronizer + APB-domain atomik register + interrupt
      -> C/N0 ve Doppler/range-rate donusumu
      -> ham Doppler + tek-kanal FDE ile C/N0-weighted velocity WLS
      -> ECEF velocity + 3x3 covariance + receiver clock drift
      -> ECEF->ENU adapter
      -> ayri velocity NIS gate
      -> ayni capture epoch'unda 15-state ESKF update
      -> daha yeni IMU history replay

RTL Doppler veya C/N0 uzerinde IIR yapmaz; ham ve 20 ms sabit snapshot'i software'e verir. Software ayni PRN icin C/N0'yi alpha=0.2 ile yumusatir; Doppler'in hem ham de alpha=0.05 IIR sonucu korunur. L1 range-rate -doppler_hz * c / 1575420000 ile hesaplanir. Ham yol tek-kanal leave-one-out FDE'li velocity WLS'ten ESKF'ye, filtreli yol ayri velocity WLS'ten yalniz PPS clock-bias drift predictor'una gider. PPS'in ana faz/zaman olcumu position WLS clock_bias_m sonucudur; Doppler yalniz 200 ms epoch'lar arasindaki turev prediction'ina ve kalite siniflandirmasina yardim eder. Her iki velocity WLS state'i [vx, vy, vz, receiver_clock_drift_mps]'dir; uydu LOS hizi ve broadcast satellite clock drift observation'dan ayrilir. C/N0, range-rate agirligini belirler; post-fit residual gerekirse formal covariance'i yalniz buyutur.

Klasik mutlak-pseudorange GNSS modelinde receiver zaman hatasi delta_t_r(t) ise:

code WLS 4. state:     b_r     = c * delta_t_r             [metre]
Doppler WLS 4. state:  bdot_r  = c * d(delta_t_r)/dt       [metre/saniye]
b_r(t + dt) ~= b_r(t) + bdot_r * dt

Burada bdot_r, receiver oscillator frequency error'inin range-rate birimindeki ortak etkisidir. Ornegin 0.1 ppm yaklasik 29.98 m/s eder; Doppler WLS bu ortak terimi uydu yonune gore degisen gercek vx/vy/vz hareketinden ayirir.

Bu projede position WLS gozlemleri, ortak RF sample counter ve ayni anda yakalanan fractional code-NCO residue ile decode edilmis satellite transmit time'in sabit bir referans kanala gore farkindan uretilir:

S_i   = unwrap32(ABS_SAMPLE_i) - REM_CODE_PHASE_i / 1.023e6
P_i/c = (S_i - S_ref)/16.367981e6 - (T_tx_i - T_tx_ref)

16.367981 MHz integer counter tek basina 61.095 ns/18.31 m adimlidir; fractional NCO residue bu sample quantization'ini giderir. 64-bit 125 MHz counter position range'i yerine epoch assembly, GPS-time/PPS ankraji ve holdover icin kullanilir. Bu nedenle startup'a bagli sabit bir flight-time offset'i yoktur. solution.clock_bias_m, saf c*delta_t_r degil, yaklasik -reference_range + c*reference_satellite_clock_correction olan referans-uyduya bagli goreli datumdur. Doppler WLS'nin dorduncu bilinmeyeni yine uydulara ortak receiver clock/frequency drift'tir; fakat iki fit arasinda clock_bias_m(t+dt)=clock_bias_m(t)+clock_drift_mps*dt kisiti kurulmaz. Fit'ler ayri measurement/normal-equation kullanir. Doppler WLS, LOS vektorleri icin position WLS'nin guncel receiver konumuna baglidir.

ESKF; ENU position/velocity, quaternion attitude, accel bias ve gyro bias iceren 15 hata durumlu filtredir. Her timestamp'li IMU ornegi prediction'a girer. Gecikmis GPS position ve Doppler velocity olcumleri kendi capture epoch'unda uygulanir, ardindan daha yeni IMU history replay edilir. Position ve velocity'nin ayri NIS kapilari vardir; kotu Doppler ayni epoch'taki gecerli position update'ini iptal etmez. Durağanlik supervisor'u uygun oldugunda ZUPT ve zero-gyro update uygular; GPS kesintisinde filtre sahte konum olcumu uretmeden dead-reckoning yapar ve covariance buyur.

C/N0, geometri, WLS clock sigma, integrity ve Doppler residual metrikleri PPS software'inin acquire/precision/robust/holdover profilini de secer. PPS donanimi bu metrikleri dogrudan yorumlamaz; software v2.2 mailbox ile PI Kp/Ki, slew ve lock esiklerini atomik olarak gunceller. Ayrintilar:

• hardware/external/gps/rtl/trck_src/README.md
• soc/software/gps_system/README.md
• soc/software/fusion/README.md
• hardware/external/gps/rtl/pps/README.md
• soc/software/pps_python/README.md

Alt girisler:

make -C hardware/soc help
make -C hardware/fpga/vcu118/rtl help
make -C hardware/sim/fpga/vcu118 help
make -C targets/fpga/vcu118 help
make -C targets/fpga/genesys2 help
make -C targets/asic/rocket help

FPGA Kart Secimi ve RF Girisi

FPGA karti kok Makefile'dan FPGA_BOARD ile secilir:

make FPGA_BOARD=vcu118 fpga-config
make FPGA_BOARD=genesys2 fpga-config

Top-level BOARD=... alias'i da desteklenir. Orneklerde Genesys2 kullanilir:

make BOARD=genesys2 fpga-config

Top-level hedeflerde tireli isimler tercih edilir (fpga-program gibi). Yanlislikla underscore kullanilmasi durumunda yaygin FPGA hedefleri icin alias'lar da vardir (fpga_program, fpga_debug_openocd gibi).

fpga-config secilen kartin clock, flash, UART, DTIM ve RF ayarlarini gosterir. RF kaynagi RF_INPUT_MODE ile secilir:

RF_INPUT_MODE=pmod       Varsayilan. Harici 4-bit RF data + RF clock PMOD'dan gelir.
RF_INPUT_MODE=generated  Dahili RF clock uretilir, RF data sifira baglanir.
RF_INPUT_MODE=ethernet   Kart bazli raw-Ethernet RF streamer path'i.

Top-level FPGA wrapper'lar elle yazilmaz; targets/fpga/*/tools/gen_*_wrapper.py scriptleri tarafindan uretilir. Bu yuzden RF secimi RTL ifdef ile degil, generator parametresi ile yapilir. make rtl ve Vivado build.tcl ayni RF_INPUT_MODE degerini wrapper generator'a gecirir.

Varsayilan pmod modunda Ethernet RF IP/RTL okunmaz ve top'ta Ethernet PHY portlari olusmaz. Ethernet RF akisi gerektiginde:

make -C targets/fpga/vcu118 bitstream RF_INPUT_MODE=ethernet
sudo make -C targets/fpga/vcu118 eth-rf-send

make -C targets/fpga/genesys2 bitstream RF_INPUT_MODE=ethernet
sudo make -C targets/fpga/genesys2 eth-rf-send

PMOD RF pinleri ve voltajlari:

Genesys2 JA, connector ve FPGA tarafi 3.3 V:
  port              FPGA pin  PMOD pin  FPGA I/O   PMOD header level
  rf_clk_pmod       U27       JA[0]     LVCMOS33   3.3 V
  rf_data_pmod[0]   U28       JA[1]     LVCMOS33   3.3 V
  rf_data_pmod[1]   T26       JA[2]     LVCMOS33   3.3 V
  rf_data_pmod[2]   T27       JA[3]     LVCMOS33   3.3 V
  rf_data_pmod[3]   T22       JA[4]     LVCMOS33   3.3 V

VCU118 PMOD0/J52, connector tarafi 3.3 V, FPGA U1 tarafi U41 level shifter
uzerinden 1.8 V bank/LVCMOS18:
  port              FPGA pin  PMOD pin       FPGA I/O   PMOD header level
  rf_clk_pmod       AY14      PMOD0_0 J52.1  LVCMOS18   3.3 V
  rf_data_pmod[0]   AY15      PMOD0_1 J52.3  LVCMOS18   3.3 V
  rf_data_pmod[1]   AW15      PMOD0_2 J52.5  LVCMOS18   3.3 V
  rf_data_pmod[2]   AV15      PMOD0_3 J52.7  LVCMOS18   3.3 V
  rf_data_pmod[3]   AV16      PMOD0_4 J52.2  LVCMOS18   3.3 V

VCU118'de disaridan PMOD header'a 3.3 V seviye verilir. FPGA U1 package pinlerine dogrudan 3.3 V uygulanmaz; o tarafta XDC LVCMOS18 kullanir.

PMOD SPI portu her RF modunda aktiftir ve ayri MMIO register block olarak 0x10015000 adresindedir. Kart uzerindeki konfig flash SPI'si 0x10014000 adresinde kalir. Yazilim driver'i single/quad calisma modunu ctrl.bit2 uzerinden secer; single modda dq[0] MOSI, dq[1] MISO olarak kullanilir ve dq[2:3] high-Z kalir. Quad modda dq[3:0] birlikte kullanilir.

Genesys2 PMOD JC, connector ve FPGA tarafi 3.3 V:
  port              FPGA pin  PMOD pin  FPGA I/O   PMOD header level
  pmod_spi_csn      AC26      JC1       LVCMOS33   3.3 V
  pmod_spi_dq[0]    AJ27      JC2 MOSI  LVCMOS33   3.3 V
  pmod_spi_dq[1]    AH30      JC3 MISO  LVCMOS33   3.3 V
  pmod_spi_sck      AK29      JC4 SCK   LVCMOS33   3.3 V
  pmod_spi_dq[2]    AD26      JC7       LVCMOS33   3.3 V
  pmod_spi_dq[3]    AG30      JC8       LVCMOS33   3.3 V

VCU118 PMOD1/J53, connector tarafi 3.3 V, FPGA U1 tarafi U42 level shifter
uzerinden 1.2 V bank/LVCMOS12:
  port              FPGA pin  PMOD pin          FPGA I/O   PMOD header level
  pmod_spi_csn      N28       PMOD1_0 J53.1     LVCMOS12   3.3 V
  pmod_spi_dq[0]    M30       PMOD1_1 J53.3 MOSI LVCMOS12  3.3 V
  pmod_spi_dq[1]    N30       PMOD1_2 J53.5 MISO LVCMOS12  3.3 V
  pmod_spi_sck      P30       PMOD1_3 J53.7 SCK  LVCMOS12  3.3 V
  pmod_spi_dq[2]    P29       PMOD1_4 J53.2     LVCMOS12   3.3 V
  pmod_spi_dq[3]    L31       PMOD1_5 J53.4     LVCMOS12   3.3 V

Sensorden gelen external interrupt hatti SPI'dan bagimsizdir. pmod_irq top-level input'u olarak PMOD'a alinir ve PLIC'te BSP_PMOD_IRQ (11) ID'siyle gorunur.

Genesys2:
  port       FPGA pin  PMOD pin  FPGA I/O   PMOD header level
  pmod_irq  AK30      JC9       LVCMOS33   3.3 V

VCU118:
  port       FPGA pin  PMOD pin        FPGA I/O   PMOD header level
  pmod_irq  M31       PMOD1_6 J53.6   LVCMOS12   3.3 V

Bu pinler mod bazli companion XDC dosyalarinda tutulur: hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc, hardware/fpga/vcu118/constraints/vcu118_pmod_rf.xdc, hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc, hardware/fpga/vcu118/constraints/vcu118_pmod_spi.xdc, hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc, hardware/fpga/vcu118/constraints/vcu118_pmod_irq.xdc, hardware/fpga/genesys2/constraints/genesys2_ethernet.xdc ve hardware/fpga/vcu118/constraints/vcu118_ethernet.xdc.

FPGA Flash ve MCS Akislari

Bu hedefler kok Makefile'dan secilen karta yonlenir. Genesys2 icin BOARD=genesys2, VCU118 icin BOARD=vcu118 kullanilir. APP verilmezse varsayilan uygulama hello_uart olur.

Sadece ELF'i derleyip bootloader'in okuyacagi flash-format app imajina cevirmek:

make BOARD=genesys2 APP=hello_uart fpga-elf-flash-image

Bu akista ELF dogrudan MCS'e girmez. Once su dosya uretilir:

soc/out/flash/hello_uart.flash.bin

Yeni bitstream ve yeni aplikasyon ile birlesik MCS/BIN olusturmak:

make BOARD=genesys2 APP=hello_uart fpga-bitstream fpga-mcs

Genesys2 ciktilari:

targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
targets/fpga/genesys2/out/flash/genesys2_rocket.bin

Birlesik MCS'i olusturup kart flash'ina yazmak:

make BOARD=genesys2 APP=hello_uart fpga-flash-mcs

Yeni bitstream de uretilsin, sonra birlesik MCS flash'a yazilsin:

make BOARD=genesys2 APP=hello_uart fpga-bitstream fpga-flash-mcs

Sadece bitstream region'ini kart flash'ina yazmak:

make BOARD=genesys2 fpga-flash-bitstream

Yeni bitstream uretip sadece bitstream region'ini yazmak:

make BOARD=genesys2 fpga-bitstream fpga-flash-bitstream

ELF'i flash formatina cevirip sadece app region'ini kart flash'ina yazmak:

make BOARD=genesys2 APP=hello_uart fpga-flash-app

fpga-flash, fpga-flash-app icin alias'tir:

make BOARD=genesys2 APP=hello_uart fpga-flash

Degisen bitstream ve app region'larini ayri MCS'lerle programlamak:

make BOARD=genesys2 APP=hello_uart fpga-flash-all

Flash programlama bittikten sonra FPGA her zaman otomatik olarak flash'taki kullanici bitstream'inden yeniden baslamaz. Kartin kalici flash'tan boot etmesini test etmek icin power-cycle/reconfigure yapin; sadece RAM/SRAM'e hemen yuklemek icin fpga-program kullanin:

make BOARD=genesys2 fpga-program

OpenOCD baslarken LIBUSB_ERROR_BUSY gorulurse JTAG kablosunu Vivado hw_server tutuyordur. Hardware Manager'i kapatin veya bu prosesleri durdurun:

pkill -u "$USER" -x hw_server || true
pkill -u "$USER" -x cs_server || true
make BOARD=genesys2 fpga-debug-openocd

Genesys2 flash yerlesimi:

bitstream offset: 0x00000000
app offset:       0x01800000
flash size:       32 MiB
interface:        SPIx4

GPS Reset Davranisi

OpenOCD/GDB monitor reset yolu Rocket debug module ndmreset sinyalini assert eder. FPGA top wrapper'lari bu sinyali SoC resetine katar; bu reset hem Rocket core'a hem APB peripheral tarafina gider.

GPS APB entegrasyonu reseti tek tel olarak kullanmaz. APBGpsBlock icinde ResetCatchAndSync ile APB/PCLK, acquisition 80 MHz, tracking 125 MHz ve RF/AFE clock domainleri icin ayri active-low resetler uretilir. Assert async, deassert ilgili clock domaininde 3 kademe senkronizedir. APB register wrapper lari PRESETN ile resetlenir; acq_top, trck_top ve afe_top ise kendi clock domain resetleriyle resetlenir.

Not: Senkron deassert icin ilgili clock calismalidir. PMOD/RF clock yoksa RF/AFE domain reseti release olmaz; bu reset acisindan beklenen davranistir.

Detayli dosya haritasi icin PROJECT_LAYOUT.md ve hardware/README.md.