onur
30179df8e6
Remove the fixed pseudorange start offset, preserve per-PRN navigation assistance across RF loss and power cycles, and seed coherent navigation measurement phase on reacquisition. Add full LNAV almanac visibility scheduling, power-safe QSPI journaling, RF-domain reset isolation, and PPS Gray CDC hardening with Linux, sanitizer, RTL, and end-to-end coverage.
842 lines
23 KiB
Python
842 lines
23 KiB
Python
#!/usr/bin/env python3
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import argparse
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import re
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from pathlib import Path
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def width_bits(width):
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if not width:
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return 1
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match = re.fullmatch(r"\[(\d+):(\d+)\]", width.strip())
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if not match:
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raise ValueError(f"unsupported width: {width}")
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left = int(match.group(1))
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right = int(match.group(2))
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return abs(left - right) + 1
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def parse_ports(verilog_path):
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text = Path(verilog_path).read_text()
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module_name = Path(verilog_path).stem
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start = text.index(f"module {module_name}(")
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end = text.index(");", start)
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header = re.sub(r"//.*", "", text[start:end])
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pieces = re.split(r"\b(input|output)\b", header)[1:]
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ports = []
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for direction, body in zip(pieces[0::2], pieces[1::2]):
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body = body.replace("\n", " ")
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body = re.split(r"\b(input|output)\b", body)[0]
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default_width = ""
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width_match = re.match(r"\s*(\[[^\]]+\])\s*(.*)", body)
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if width_match:
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default_width = width_match.group(1)
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rest = width_match.group(2)
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else:
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rest = body
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for item in rest.split(","):
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item = item.strip()
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if not item:
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continue
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item_match = re.match(r"(\[[^\]]+\])\s*(\w+)$", item)
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if item_match:
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width = item_match.group(1)
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name = item_match.group(2)
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else:
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width = default_width
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name = item.split()[-1]
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if re.fullmatch(r"\w+", name):
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ports.append((direction, width, name))
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return ports
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def const_for(width):
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bits = width_bits(width)
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return "1'b0" if bits == 1 else f"{bits}'d0"
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def is_clock(name):
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return name.endswith("_clock") or name in {
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"debug_clock",
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"debug_clockeddmi_dmiClock",
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}
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def is_reset(name):
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return name.endswith("_reset") or name in {
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"debug_reset",
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"debug_clockeddmi_dmiReset",
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}
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def decl(width, name):
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return f" wire {width + ' ' if width else ''}{name};"
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def axi_slave(prefix, module_name, addr_width):
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return "\n".join([
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f" {module_name} #(",
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f" .ADDR_WIDTH({addr_width}),",
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" .ID_WIDTH(4)",
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f" ) u_{prefix}_slave (",
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" .clk(fabric_clk),",
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" .reset(fabric_reset),",
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f" .aw_ready({prefix}_axi4_0_aw_ready),",
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f" .aw_valid({prefix}_axi4_0_aw_valid),",
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f" .aw_bits_id({prefix}_axi4_0_aw_bits_id),",
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f" .aw_bits_addr({prefix}_axi4_0_aw_bits_addr),",
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f" .aw_bits_len({prefix}_axi4_0_aw_bits_len),",
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f" .aw_bits_size({prefix}_axi4_0_aw_bits_size),",
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f" .aw_bits_burst({prefix}_axi4_0_aw_bits_burst),",
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f" .w_ready({prefix}_axi4_0_w_ready),",
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f" .w_valid({prefix}_axi4_0_w_valid),",
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f" .w_bits_data({prefix}_axi4_0_w_bits_data),",
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f" .w_bits_strb({prefix}_axi4_0_w_bits_strb),",
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f" .w_bits_last({prefix}_axi4_0_w_bits_last),",
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f" .b_ready({prefix}_axi4_0_b_ready),",
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f" .b_valid({prefix}_axi4_0_b_valid),",
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f" .b_bits_id({prefix}_axi4_0_b_bits_id),",
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f" .b_bits_resp({prefix}_axi4_0_b_bits_resp),",
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f" .ar_ready({prefix}_axi4_0_ar_ready),",
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f" .ar_valid({prefix}_axi4_0_ar_valid),",
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f" .ar_bits_id({prefix}_axi4_0_ar_bits_id),",
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f" .ar_bits_addr({prefix}_axi4_0_ar_bits_addr),",
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f" .ar_bits_len({prefix}_axi4_0_ar_bits_len),",
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f" .ar_bits_size({prefix}_axi4_0_ar_bits_size),",
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f" .ar_bits_burst({prefix}_axi4_0_ar_bits_burst),",
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f" .r_ready({prefix}_axi4_0_r_ready),",
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f" .r_valid({prefix}_axi4_0_r_valid),",
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f" .r_bits_id({prefix}_axi4_0_r_bits_id),",
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f" .r_bits_data({prefix}_axi4_0_r_bits_data),",
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f" .r_bits_resp({prefix}_axi4_0_r_bits_resp),",
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f" .r_bits_last({prefix}_axi4_0_r_bits_last)",
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" );",
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])
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def has_axi_slave(prefix, port_by_name):
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required = [
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f"{prefix}_axi4_0_aw_ready",
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f"{prefix}_axi4_0_aw_valid",
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f"{prefix}_axi4_0_w_ready",
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f"{prefix}_axi4_0_w_valid",
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f"{prefix}_axi4_0_b_ready",
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f"{prefix}_axi4_0_b_valid",
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f"{prefix}_axi4_0_ar_ready",
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f"{prefix}_axi4_0_ar_valid",
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f"{prefix}_axi4_0_r_ready",
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f"{prefix}_axi4_0_r_valid",
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]
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return all(name in port_by_name for name in required)
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def main():
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parser = argparse.ArgumentParser()
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parser.add_argument("--rocket-top", required=True)
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parser.add_argument("--out", required=True)
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parser.add_argument(
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"--rf-input-mode",
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choices=["pmod", "generated", "ethernet"],
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default="pmod",
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help="GPS RF source: pmod uses external PMOD clock/data, generated keeps the old internal RF clock with zero data, ethernet enables the Genesys2 RGMII RF streamer path.",
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)
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args = parser.parse_args()
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ports = parse_ports(args.rocket_top)
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port_by_name = {name: (direction, width) for direction, width, name in ports}
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top_passthrough_ports = {
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name for name in ["pmod_spi_sck", "pmod_spi_csn", "pmod_irq", "gps_pps"]
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if name in port_by_name
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}
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assigns = []
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for direction, width, name in ports:
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if direction != "input":
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continue
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if name in top_passthrough_ports:
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continue
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if name == "debug_systemjtag_reset":
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value = "fabric_reset | bscan_reset"
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elif name.startswith("debug_clockeddmi_dmi_req") or name == "debug_clockeddmi_dmi_resp_ready":
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continue
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elif name in {
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"debug_clockeddmi_dmiClock",
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"debug_clockeddmi_dmiReset",
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}:
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continue
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elif is_clock(name):
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value = "fabric_clk"
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elif name == "debug_reset":
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value = "fabric_reset"
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elif name == "resetctrl_hartIsInReset_0":
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value = "soc_reset"
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elif is_reset(name):
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value = "soc_reset"
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elif name == "gps_acq_clk":
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value = "gps_acq_clk_gen"
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elif name == "gps_trck_clk":
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value = "gps_trck_clk_gen"
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elif name == "gps_rf_clk":
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value = "gps_rf_clk_selected"
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elif name == "gps_rf_data":
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value = "gps_rf_data_selected"
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elif name == "gps_clock_ready":
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value = "gps_clock_locked & gps_rf_ready"
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elif name == "gps_afe_clk":
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value = "gps_rf_clk_selected"
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elif name == "debug_systemjtag_jtag_TCK":
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value = "bscan_tck"
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elif name == "debug_systemjtag_jtag_TMS":
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value = "bscan_tms"
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elif name == "debug_systemjtag_jtag_TDI":
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value = "bscan_tdi"
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elif name == "debug_systemjtag_mfr_id":
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value = "11'd0"
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elif name == "debug_systemjtag_part_number":
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value = "16'd0"
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elif name == "debug_systemjtag_version":
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value = "4'd0"
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elif name == "debug_clockeddmi_dmi_resp_ready":
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value = "1'b1"
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elif name == "debug_dmactiveAck":
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value = "debug_dmactive"
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elif name.startswith("debug_clockeddmi_dmi_req"):
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value = const_for(width)
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elif name.startswith("l2_frontend_bus_axi4_0_"):
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if name.endswith("_b_ready") or name.endswith("_r_ready"):
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value = "1'b1"
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else:
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value = const_for(width)
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elif name == "interrupts":
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value = "2'b00"
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elif name == "uart_rxd":
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value = "uart_tx_in"
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elif name == "spi_dq_i":
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continue
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elif name == "pmod_spi_dq_i":
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continue
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elif name.startswith("mem_axi4_0_") or name.startswith("mmio_axi4_0_"):
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continue
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else:
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value = const_for(width)
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assigns.append(f" assign {name} = {value};")
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port_map = ",\n".join(
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f" .{name}({'pmod_irq_sync[2]' if name == 'pmod_irq' else name})"
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for _, _, name in ports
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)
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led_debug = []
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for candidate in ["debug_ndreset", "debug_dmactive", "debug_clockeddmi_dmi_req_ready"]:
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if candidate in port_by_name:
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led_debug.append(candidate)
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while len(led_debug) < 3:
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led_debug.append("1'b0")
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has_clocked_dmi = all(name in port_by_name for name in [
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"debug_clockeddmi_dmi_req_ready",
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"debug_clockeddmi_dmi_req_valid",
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"debug_clockeddmi_dmi_req_bits_addr",
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"debug_clockeddmi_dmi_req_bits_data",
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"debug_clockeddmi_dmi_req_bits_op",
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"debug_clockeddmi_dmi_resp_ready",
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"debug_clockeddmi_dmi_resp_valid",
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"debug_clockeddmi_dmi_resp_bits_data",
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"debug_clockeddmi_dmi_resp_bits_resp",
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"debug_clockeddmi_dmiClock",
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"debug_clockeddmi_dmiReset",
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])
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bscan_block = ""
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if has_clocked_dmi:
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bscan_block = """\
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wire bscan_capture;
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wire bscan_drck;
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wire bscan_reset;
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wire bscan_runtest;
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wire bscan_sel;
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wire bscan_shift;
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wire bscan_tck;
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wire bscan_tdi;
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wire bscan_tms;
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wire bscan_tdo;
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wire bscan_update;
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BSCANE2 #(
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.DISABLE_JTAG("FALSE"),
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.JTAG_CHAIN(4)
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) u_rocket_bscan (
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.CAPTURE(bscan_capture),
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.DRCK(bscan_drck),
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.RESET(bscan_reset),
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.RUNTEST(bscan_runtest),
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.SEL(bscan_sel),
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.SHIFT(bscan_shift),
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.TCK(bscan_tck),
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.TDI(bscan_tdi),
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.TMS(bscan_tms),
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.UPDATE(bscan_update),
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.TDO(bscan_tdo)
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);
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rocket_bscan_dmi_tunnel u_rocket_bscan_dmi_tunnel (
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.tck(bscan_tck),
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// Keep the transport TAP alive while the fabric is in reset. Otherwise
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// OpenOCD cannot examine the target to diagnose a PLL/reset-ready failure.
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.reset(bscan_reset),
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.bscan_capture(bscan_capture),
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.bscan_sel(bscan_sel),
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.bscan_shift(bscan_shift),
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.bscan_tdi(bscan_tdi),
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.bscan_update(bscan_update),
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.bscan_tdo(bscan_tdo),
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.dmi_clock(debug_clockeddmi_dmiClock),
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.dmi_reset(debug_clockeddmi_dmiReset),
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.dmi_req_ready(debug_clockeddmi_dmi_req_ready),
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.dmi_req_valid(debug_clockeddmi_dmi_req_valid),
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.dmi_req_addr(debug_clockeddmi_dmi_req_bits_addr),
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.dmi_req_data(debug_clockeddmi_dmi_req_bits_data),
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.dmi_req_op(debug_clockeddmi_dmi_req_bits_op),
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.dmi_resp_ready(debug_clockeddmi_dmi_resp_ready),
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.dmi_resp_valid(debug_clockeddmi_dmi_resp_valid),
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.dmi_resp_data(debug_clockeddmi_dmi_resp_bits_data),
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.dmi_resp_resp(debug_clockeddmi_dmi_resp_bits_resp)
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);
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"""
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has_spi_flash = all(name in port_by_name for name in [
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"spi_sck",
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"spi_csn",
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"spi_dq_i",
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"spi_dq_o",
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"spi_dq_oe",
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])
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startup_block = ""
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if has_spi_flash:
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startup_block = """\
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assign spi_dq_i = qspi_d;
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assign qspi_d[0] = spi_dq_oe[0] ? spi_dq_o[0] : 1'bz;
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assign qspi_d[1] = spi_dq_oe[1] ? spi_dq_o[1] : 1'bz;
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assign qspi_d[2] = spi_dq_oe[2] ? spi_dq_o[2] : 1'bz;
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assign qspi_d[3] = spi_dq_oe[3] ? spi_dq_o[3] : 1'bz;
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assign qspi_csn = spi_csn;
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STARTUPE2 #(
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.PROG_USR("FALSE"),
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.SIM_CCLK_FREQ(0.0)
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) u_cfg_flash_startup (
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.CFGCLK(),
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.CFGMCLK(),
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.EOS(),
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.PREQ(),
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.CLK(1'b0),
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.GSR(1'b0),
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.GTS(1'b0),
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.KEYCLEARB(1'b1),
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.PACK(1'b0),
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.USRCCLKO(spi_sck),
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.USRCCLKTS(1'b0),
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.USRDONEO(1'b1),
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.USRDONETS(1'b1)
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);
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"""
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has_pmod_spi = all(name in port_by_name for name in [
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"pmod_spi_sck",
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"pmod_spi_csn",
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"pmod_spi_dq_i",
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"pmod_spi_dq_o",
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"pmod_spi_dq_oe",
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])
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pmod_spi_top_ports = ""
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pmod_spi_block = ""
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if has_pmod_spi:
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pmod_spi_top_ports = """\
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output wire pmod_spi_sck,
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output wire pmod_spi_csn,
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inout wire [3:0] pmod_spi_dq,
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"""
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pmod_spi_block = """\
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assign pmod_spi_dq_i = pmod_spi_dq;
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assign pmod_spi_dq[0] = pmod_spi_dq_oe[0] ? pmod_spi_dq_o[0] : 1'bz;
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assign pmod_spi_dq[1] = pmod_spi_dq_oe[1] ? pmod_spi_dq_o[1] : 1'bz;
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assign pmod_spi_dq[2] = pmod_spi_dq_oe[2] ? pmod_spi_dq_o[2] : 1'bz;
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assign pmod_spi_dq[3] = pmod_spi_dq_oe[3] ? pmod_spi_dq_o[3] : 1'bz;
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"""
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pmod_irq_top_ports = ""
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pmod_irq_block = ""
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if "pmod_irq" in port_by_name:
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pmod_irq_top_ports = """\
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input wire pmod_irq,
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"""
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pmod_irq_block = """\
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// JB1 is asynchronous to the 50 MHz Rocket fabric. Keep this as three
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// physical flip-flops: ASYNC_REG guides placement for metastability MTBF,
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// and SHREG_EXTRACT prevents Vivado from collapsing stages into an SRL.
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(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
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reg [2:0] pmod_irq_sync = 3'b000;
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always @(posedge fabric_clk) begin
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if (fabric_reset) begin
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pmod_irq_sync <= 3'b000;
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end else begin
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pmod_irq_sync <= {pmod_irq_sync[1:0], pmod_irq};
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end
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end
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"""
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pps_top_ports = ""
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if port_by_name.get("gps_pps") == ("output", ""):
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pps_top_ports = """\
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output wire gps_pps,
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"""
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rocket_module = Path(args.rocket_top).stem
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rf_top_ports = ""
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eth_top_ports = ""
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rf_extra_wires = ""
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eth_block = ""
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led_prefix = "heartbeat[25], heartbeat[24], ~cpu_resetn, fabric_reset"
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if args.rf_input_mode == "pmod":
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rf_top_ports = """\
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// External RF PMOD input. The connector side is 3.3 V; XDC sets the FPGA I/O standard.
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input wire rf_clk_pmod,
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input wire [3:0] rf_data_pmod,
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"""
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rf_clock_block = """\
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wire rf_clk_pmod_ibuf;
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// PMOD mode feeds the GPS RF domain directly from the external sampler.
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IBUF u_rf_clk_pmod_ibuf (
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.I(rf_clk_pmod),
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.O(rf_clk_pmod_ibuf)
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);
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BUFG u_rf_clk_pmod_buf (
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.I(rf_clk_pmod_ibuf),
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.O(gps_rf_clk_selected)
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);
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assign gps_rf_data_selected = rf_data_pmod;
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assign gps_rf_ready = 1'b1;
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"""
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else:
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rf_extra_wires = """\
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wire gps_rf_clk_gen;
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wire gps_rf_clkfb;
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wire gps_rf_clkfb_buf;
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wire pll_gps_rf_exact_clk;
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wire gps_rf_pll_locked;
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"""
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rf_clock_block = """\
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// Generated mode is useful when no RF PMOD source is connected.
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MMCME2_ADV #(
|
|
.BANDWIDTH("OPTIMIZED"),
|
|
.CLKFBOUT_MULT_F(17.125),
|
|
.CLKFBOUT_PHASE(0.000),
|
|
.CLKIN1_PERIOD(5.000),
|
|
.CLKIN2_PERIOD(0.000),
|
|
.CLKOUT0_DIVIDE_F(69.750),
|
|
.CLKOUT0_PHASE(0.000),
|
|
.CLKOUT0_DUTY_CYCLE(0.500),
|
|
.DIVCLK_DIVIDE(3),
|
|
.REF_JITTER1(0.010),
|
|
.REF_JITTER2(0.010),
|
|
.STARTUP_WAIT("FALSE")
|
|
) u_gps_rf_mmcm (
|
|
.CLKIN1(sysclk_200),
|
|
.CLKIN2(1'b0),
|
|
.CLKINSEL(1'b1),
|
|
.CLKFBIN(gps_rf_clkfb_buf),
|
|
.CLKFBOUT(gps_rf_clkfb),
|
|
.CLKFBOUTB(),
|
|
.CLKOUT0(pll_gps_rf_exact_clk),
|
|
.CLKOUT0B(),
|
|
.CLKOUT1(),
|
|
.CLKOUT1B(),
|
|
.CLKOUT2(),
|
|
.CLKOUT2B(),
|
|
.CLKOUT3(),
|
|
.CLKOUT3B(),
|
|
.CLKOUT4(),
|
|
.CLKOUT5(),
|
|
.CLKOUT6(),
|
|
.DADDR(7'd0),
|
|
.DCLK(1'b0),
|
|
.DEN(1'b0),
|
|
.DI(16'd0),
|
|
.DWE(1'b0),
|
|
.DO(),
|
|
.DRDY(),
|
|
.LOCKED(gps_rf_pll_locked),
|
|
.PSCLK(1'b0),
|
|
.PSEN(1'b0),
|
|
.PSINCDEC(1'b0),
|
|
.PSDONE(),
|
|
.PWRDWN(1'b0),
|
|
.RST(board_reset)
|
|
);
|
|
|
|
BUFG u_gps_rf_feedback_buf (
|
|
.I(gps_rf_clkfb),
|
|
.O(gps_rf_clkfb_buf)
|
|
);
|
|
|
|
BUFG u_gps_rf_clk_buf (
|
|
.I(pll_gps_rf_exact_clk),
|
|
.O(gps_rf_clk_gen)
|
|
);
|
|
|
|
assign gps_rf_clk_selected = gps_rf_clk_gen;
|
|
assign gps_rf_ready = gps_rf_pll_locked;
|
|
"""
|
|
if args.rf_input_mode == "ethernet":
|
|
eth_top_ports = """\
|
|
input wire eth_rxck,
|
|
input wire [3:0] eth_rxd,
|
|
input wire eth_rxctl,
|
|
output wire eth_txck,
|
|
output wire [3:0] eth_txd,
|
|
output wire eth_txctl,
|
|
output wire eth_phyrst_n,
|
|
input wire eth_int_b,
|
|
input wire eth_pme_b,
|
|
inout wire eth_mdio,
|
|
output wire eth_mdc,
|
|
"""
|
|
eth_block = """\
|
|
wire [3:0] ethernet_rf_data;
|
|
wire [7:0] ethernet_rf_status;
|
|
|
|
// Genesys2 Ethernet mode uses the board RTL8211E-VL RGMII PHY.
|
|
eth_rf_genesys2 u_ethernet_rf (
|
|
.mgmt_clk(fabric_clk),
|
|
.mgmt_rst(fabric_reset),
|
|
.rf_clk(gps_rf_clk_gen),
|
|
.rf_rst(fabric_reset),
|
|
.eth_rxck(eth_rxck),
|
|
.eth_rxd(eth_rxd),
|
|
.eth_rxctl(eth_rxctl),
|
|
.eth_txck(eth_txck),
|
|
.eth_txd(eth_txd),
|
|
.eth_txctl(eth_txctl),
|
|
.eth_phyrst_n(eth_phyrst_n),
|
|
.eth_int_b(eth_int_b),
|
|
.eth_pme_b(eth_pme_b),
|
|
.eth_mdio(eth_mdio),
|
|
.eth_mdc(eth_mdc),
|
|
.gps_rf_data(ethernet_rf_data),
|
|
.status(ethernet_rf_status)
|
|
);
|
|
|
|
assign gps_rf_data_selected = ethernet_rf_data;
|
|
"""
|
|
led_prefix = "ethernet_rf_status[7], ethernet_rf_status[6], ethernet_rf_status[5], ethernet_rf_status[4]"
|
|
else:
|
|
eth_block = """\
|
|
assign gps_rf_data_selected = 4'd0;
|
|
"""
|
|
|
|
content = f"""`timescale 1ns/1ps
|
|
|
|
module genesys2_rocket_top (
|
|
input wire sysclk_p,
|
|
input wire sysclk_n,
|
|
input wire cpu_resetn,
|
|
// Digilent labels these from the PC/FTDI side: TX_IN is FPGA RX, RX_OUT is FPGA TX.
|
|
input wire uart_tx_in,
|
|
output wire uart_rx_out,
|
|
{rf_top_ports}{eth_top_ports}{pmod_spi_top_ports}{pmod_irq_top_ports}{pps_top_ports}\
|
|
inout wire [3:0] qspi_d,
|
|
output wire qspi_csn,
|
|
output wire [7:0] led
|
|
);
|
|
wire sysclk_200;
|
|
wire fabric_clk;
|
|
wire gps_acq_clk_gen;
|
|
wire gps_trck_clk_gen;
|
|
wire gps_rf_clk_selected;
|
|
wire [3:0] gps_rf_data_selected;
|
|
wire gps_rf_ready;
|
|
wire fabric_clkfb;
|
|
wire fabric_clkfb_buf;
|
|
wire gps_ref_clkfb;
|
|
wire gps_ref_clkfb_buf;
|
|
wire gps_ref_clk_gen;
|
|
wire pll_gps_ref_clk;
|
|
wire gps_ref_pll_locked;
|
|
wire gps_clkfb;
|
|
wire gps_clkfb_buf;
|
|
wire pll_gps_acq_clk;
|
|
wire pll_fabric_clk;
|
|
wire pll_gps_trck_clk;
|
|
wire fabric_pll_locked;
|
|
wire gps_domain_pll_locked;
|
|
wire gps_clock_locked = gps_ref_pll_locked & gps_domain_pll_locked;
|
|
wire board_reset = ~cpu_resetn;
|
|
{rf_extra_wires}
|
|
|
|
IBUFDS #(
|
|
.DIFF_TERM("FALSE"),
|
|
.IBUF_LOW_PWR("FALSE")
|
|
) u_sysclk_ibufds (
|
|
.I(sysclk_p),
|
|
.IB(sysclk_n),
|
|
.O(sysclk_200)
|
|
);
|
|
|
|
MMCME2_ADV #(
|
|
.BANDWIDTH("OPTIMIZED"),
|
|
.CLKFBOUT_MULT_F(5.000),
|
|
.CLKFBOUT_PHASE(0.000),
|
|
.CLKIN1_PERIOD(5.000),
|
|
.CLKIN2_PERIOD(0.000),
|
|
.CLKOUT0_DIVIDE_F(12.500),
|
|
.CLKOUT0_PHASE(0.000),
|
|
.CLKOUT0_DUTY_CYCLE(0.500),
|
|
.CLKOUT1_DIVIDE(20),
|
|
.CLKOUT1_PHASE(0.000),
|
|
.CLKOUT1_DUTY_CYCLE(0.500),
|
|
.CLKOUT2_DIVIDE(8),
|
|
.CLKOUT2_PHASE(0.000),
|
|
.CLKOUT2_DUTY_CYCLE(0.500),
|
|
.DIVCLK_DIVIDE(1),
|
|
.REF_JITTER1(0.010),
|
|
.REF_JITTER2(0.010),
|
|
.STARTUP_WAIT("FALSE")
|
|
) u_clock_mmcm (
|
|
.CLKIN1(sysclk_200),
|
|
.CLKIN2(1'b0),
|
|
.CLKINSEL(1'b1),
|
|
.CLKFBIN(fabric_clkfb_buf),
|
|
.CLKFBOUT(fabric_clkfb),
|
|
.CLKFBOUTB(),
|
|
.CLKOUT0(),
|
|
.CLKOUT0B(),
|
|
.CLKOUT1(pll_fabric_clk),
|
|
.CLKOUT1B(),
|
|
.CLKOUT2(),
|
|
.CLKOUT2B(),
|
|
.CLKOUT3(),
|
|
.CLKOUT3B(),
|
|
.CLKOUT4(),
|
|
.CLKOUT5(),
|
|
.CLKOUT6(),
|
|
.DADDR(7'd0),
|
|
.DCLK(1'b0),
|
|
.DEN(1'b0),
|
|
.DI(16'd0),
|
|
.DWE(1'b0),
|
|
.DO(),
|
|
.DRDY(),
|
|
.LOCKED(fabric_pll_locked),
|
|
.PSCLK(1'b0),
|
|
.PSEN(1'b0),
|
|
.PSINCDEC(1'b0),
|
|
.PSDONE(),
|
|
.PWRDWN(1'b0),
|
|
.RST(board_reset)
|
|
);
|
|
|
|
BUFG u_pll_feedback_buf (
|
|
.I(fabric_clkfb),
|
|
.O(fabric_clkfb_buf)
|
|
);
|
|
|
|
BUFG u_fabric_clk_buf (
|
|
.I(pll_fabric_clk),
|
|
.O(fabric_clk)
|
|
);
|
|
|
|
{rf_clock_block}
|
|
|
|
// GPS processing clocks are synthesized from the RF sample clock, not the
|
|
// board crystal. Two MMCM stages keep 80/125 MHz within 0.01 ppm of nominal
|
|
// for the 16.367981 MHz sampler while leaving the Rocket fabric independent.
|
|
MMCME2_ADV #(
|
|
.BANDWIDTH("OPTIMIZED"),
|
|
.CLKFBOUT_MULT_F(58.125),
|
|
.CLKFBOUT_PHASE(0.000),
|
|
.CLKIN1_PERIOD(61.095),
|
|
.CLKIN2_PERIOD(0.000),
|
|
.CLKOUT0_DIVIDE_F(17.125),
|
|
.CLKOUT0_PHASE(0.000),
|
|
.CLKOUT0_DUTY_CYCLE(0.500),
|
|
.DIVCLK_DIVIDE(1),
|
|
.REF_JITTER1(0.010),
|
|
.REF_JITTER2(0.010),
|
|
.STARTUP_WAIT("FALSE")
|
|
) u_gps_ref_mmcm (
|
|
.CLKIN1(gps_rf_clk_selected),
|
|
.CLKIN2(1'b0),
|
|
.CLKINSEL(1'b1),
|
|
.CLKFBIN(gps_ref_clkfb_buf),
|
|
.CLKFBOUT(gps_ref_clkfb),
|
|
.CLKFBOUTB(),
|
|
.CLKOUT0(pll_gps_ref_clk),
|
|
.CLKOUT0B(),
|
|
.CLKOUT1(),
|
|
.CLKOUT1B(),
|
|
.CLKOUT2(),
|
|
.CLKOUT2B(),
|
|
.CLKOUT3(),
|
|
.CLKOUT3B(),
|
|
.CLKOUT4(),
|
|
.CLKOUT5(),
|
|
.CLKOUT6(),
|
|
.DADDR(7'd0),
|
|
.DCLK(1'b0),
|
|
.DEN(1'b0),
|
|
.DI(16'd0),
|
|
.DWE(1'b0),
|
|
.DO(),
|
|
.DRDY(),
|
|
.LOCKED(gps_ref_pll_locked),
|
|
.PSCLK(1'b0),
|
|
.PSEN(1'b0),
|
|
.PSINCDEC(1'b0),
|
|
.PSDONE(),
|
|
.PWRDWN(1'b0),
|
|
.RST(board_reset)
|
|
);
|
|
|
|
BUFG u_gps_ref_feedback_buf (
|
|
.I(gps_ref_clkfb),
|
|
.O(gps_ref_clkfb_buf)
|
|
);
|
|
|
|
BUFG u_gps_ref_clk_buf (
|
|
.I(pll_gps_ref_clk),
|
|
.O(gps_ref_clk_gen)
|
|
);
|
|
|
|
MMCME2_ADV #(
|
|
.BANDWIDTH("OPTIMIZED"),
|
|
.CLKFBOUT_MULT_F(18.000),
|
|
.CLKFBOUT_PHASE(0.000),
|
|
.CLKIN1_PERIOD(18.000),
|
|
.CLKIN2_PERIOD(0.000),
|
|
.CLKOUT0_DIVIDE_F(12.500),
|
|
.CLKOUT0_PHASE(0.000),
|
|
.CLKOUT0_DUTY_CYCLE(0.500),
|
|
.CLKOUT1_DIVIDE(8),
|
|
.CLKOUT1_PHASE(0.000),
|
|
.CLKOUT1_DUTY_CYCLE(0.500),
|
|
.DIVCLK_DIVIDE(1),
|
|
.REF_JITTER1(0.010),
|
|
.REF_JITTER2(0.010),
|
|
.STARTUP_WAIT("FALSE")
|
|
) u_gps_domain_mmcm (
|
|
.CLKIN1(gps_ref_clk_gen),
|
|
.CLKIN2(1'b0),
|
|
.CLKINSEL(1'b1),
|
|
.CLKFBIN(gps_clkfb_buf),
|
|
.CLKFBOUT(gps_clkfb),
|
|
.CLKFBOUTB(),
|
|
.CLKOUT0(pll_gps_acq_clk),
|
|
.CLKOUT0B(),
|
|
.CLKOUT1(pll_gps_trck_clk),
|
|
.CLKOUT1B(),
|
|
.CLKOUT2(),
|
|
.CLKOUT2B(),
|
|
.CLKOUT3(),
|
|
.CLKOUT3B(),
|
|
.CLKOUT4(),
|
|
.CLKOUT5(),
|
|
.CLKOUT6(),
|
|
.DADDR(7'd0),
|
|
.DCLK(1'b0),
|
|
.DEN(1'b0),
|
|
.DI(16'd0),
|
|
.DWE(1'b0),
|
|
.DO(),
|
|
.DRDY(),
|
|
.LOCKED(gps_domain_pll_locked),
|
|
.PSCLK(1'b0),
|
|
.PSEN(1'b0),
|
|
.PSINCDEC(1'b0),
|
|
.PSDONE(),
|
|
.PWRDWN(1'b0),
|
|
.RST(board_reset | ~gps_ref_pll_locked)
|
|
);
|
|
|
|
BUFG u_gps_domain_feedback_buf (
|
|
.I(gps_clkfb),
|
|
.O(gps_clkfb_buf)
|
|
);
|
|
|
|
BUFG u_gps_acq_clk_buf (
|
|
.I(pll_gps_acq_clk),
|
|
.O(gps_acq_clk_gen)
|
|
);
|
|
|
|
BUFG u_gps_trck_clk_buf (
|
|
.I(pll_gps_trck_clk),
|
|
.O(gps_trck_clk_gen)
|
|
);
|
|
|
|
// The Rocket/fabric clock and RAM cache must survive loss of the external RF
|
|
// clock. gps_clock_ready independently resets only the GPS DSP domains.
|
|
wire pll_ready_async = fabric_pll_locked & cpu_resetn;
|
|
(* async_reg = "true" *) reg [2:0] pll_ready_sync = 3'b000;
|
|
reg [15:0] reset_shift = 16'hFFFF;
|
|
always @(posedge fabric_clk) begin
|
|
pll_ready_sync <= {{pll_ready_sync[1:0], pll_ready_async}};
|
|
if (!pll_ready_sync[2]) begin
|
|
reset_shift <= 16'hFFFF;
|
|
end else begin
|
|
reset_shift <= {{reset_shift[14:0], 1'b0}};
|
|
end
|
|
end
|
|
|
|
wire fabric_reset = reset_shift[15];
|
|
reg [31:0] heartbeat;
|
|
always @(posedge fabric_clk) begin
|
|
if (fabric_reset) begin
|
|
heartbeat <= 32'd0;
|
|
end else begin
|
|
heartbeat <= heartbeat + 32'd1;
|
|
end
|
|
end
|
|
|
|
{eth_block}
|
|
|
|
{chr(10).join(decl(width, name) for _, width, name in ports if name not in top_passthrough_ports)}
|
|
|
|
wire soc_reset = {"fabric_reset | debug_ndreset" if "debug_ndreset" in port_by_name else "fabric_reset"};
|
|
|
|
{bscan_block}
|
|
{startup_block}
|
|
{pmod_spi_block}
|
|
{pmod_irq_block}
|
|
{chr(10).join(assigns)}
|
|
|
|
assign led = {{
|
|
{led_prefix},
|
|
{led_debug[2]},
|
|
{led_debug[1]},
|
|
{led_debug[0]},
|
|
uart_txd
|
|
}};
|
|
assign uart_rx_out = {"uart_txd" if "uart_txd" in port_by_name else "1'b1"};
|
|
|
|
{axi_slave("mem", "axi4_ram_64", 32) if has_axi_slave("mem", port_by_name) else ""}
|
|
|
|
{axi_slave("mmio", "axi4_slave_tieoff_64", 31) if has_axi_slave("mmio", port_by_name) else ""}
|
|
|
|
(* dont_touch = "true", keep_hierarchy = "yes" *)
|
|
{rocket_module} u_rocket (
|
|
{port_map}
|
|
);
|
|
endmodule
|
|
"""
|
|
|
|
Path(args.out).parent.mkdir(parents=True, exist_ok=True)
|
|
Path(args.out).write_text(content)
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|