gps/hardware/generated/genesys2-soc/freechips.rocketchip.fpga.VCU118RocketConfig.plusArgs

#define PLUSARG_USAGE_OPTIONS "EMULATOR VERILOG PLUSARGS\n\
       +max_core_cycles=INT\n\
                           Kill the emulation after INT rdtime cycles. Off if 0.\n\
                             (default=0)\n\
"
static const char * verilog_plusargs [] = {\
                                            "max_core_cycles",\
                                            0};