onur
120 lines
4.4 KiB
Scala
120 lines
4.4 KiB
Scala
package freechips.rocketchip.fpga
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import chisel3._
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import chisel3.experimental.IntParam
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import chisel3.util.Cat
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import org.chipsalliance.cde.config.Parameters
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import org.chipsalliance.diplomacy.bundlebridge._
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import org.chipsalliance.diplomacy.lazymodule._
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import freechips.rocketchip.diplomacy.AddressSet
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import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegWriteFn}
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import freechips.rocketchip.resources.SimpleDevice
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import freechips.rocketchip.tilelink.TLRegisterNode
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case class MAX2771SPIParams(
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address: BigInt = 0x10016000L,
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inputClockHz: Int = 100000000,
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maxSclkHz: Int = 4000000) {
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require(inputClockHz > 0, "MAX2771 SPI input clock must be positive")
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require(maxSclkHz > 0 && maxSclkHz <= 4000000,
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"MAX2771 data sheet limits SCLK to 4 MHz")
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val halfPeriodCycles: Int = (inputClockHz + 2 * maxSclkHz - 1) / (2 * maxSclkHz)
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val actualSclkHz: Int = inputClockHz / (2 * halfPeriodCycles)
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}
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class MAX2771SPIEngineBlackBox(params: MAX2771SPIParams) extends BlackBox(Map(
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"CLOCK_HZ" -> IntParam(params.inputClockHz),
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"MAX_SCLK_HZ" -> IntParam(params.maxSclkHz))) {
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override def desiredName: String = "max2771_spi_engine"
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val io = IO(new Bundle {
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val clk = Input(Clock())
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val rst_n = Input(Bool())
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val start = Input(Bool())
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val read_not_write = Input(Bool())
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val address = Input(UInt(4.W))
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val write_data = Input(UInt(32.W))
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val read_data = Output(UInt(32.W))
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val busy = Output(Bool())
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val ready = Output(Bool())
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val sclk = Output(Bool())
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val csn = Output(Bool())
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val sdata_i = Input(Bool())
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val sdata_o = Output(Bool())
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val sdata_oe = Output(Bool())
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})
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}
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class TLMAX2771SPI(params: MAX2771SPIParams, beatBytes: Int)(implicit p: Parameters)
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extends LazyModule {
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val device = new SimpleDevice("max2771-spi", Seq("analog-devices,max2771-spi"))
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val sclkNode = BundleBridgeSource(() => Bool())
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val csnNode = BundleBridgeSource(() => Bool())
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val sdataInNode = BundleBridgeSink[Bool]()
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val sdataOutNode = BundleBridgeSource(() => Bool())
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val sdataOeNode = BundleBridgeSource(() => Bool())
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val node = TLRegisterNode(
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address = Seq(AddressSet(params.address, 0xfff)),
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device = device,
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beatBytes = beatBytes,
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concurrency = 1)
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lazy val module = new Impl
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class Impl extends LazyModuleImp(this) {
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val engine = Module(new MAX2771SPIEngineBlackBox(params))
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val writeData = RegInit(0.U(32.W))
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val start = WireDefault(false.B)
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val commandRead = WireDefault(false.B)
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val commandAddress = WireDefault(0.U(4.W))
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engine.io.clk := clock
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engine.io.rst_n := !reset.asBool
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engine.io.start := start
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engine.io.read_not_write := commandRead
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engine.io.address := commandAddress
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engine.io.write_data := writeData
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engine.io.sdata_i := sdataInNode.bundle
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sclkNode.bundle := engine.io.sclk
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csnNode.bundle := engine.io.csn
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sdataOutNode.bundle := engine.io.sdata_o
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sdataOeNode.bundle := engine.io.sdata_oe
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val commandWrite = RegWriteFn { (valid, data) =>
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commandRead := data(8)
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commandAddress := data(3, 0)
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start := valid && engine.io.ready
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engine.io.ready
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}
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val writeDataWrite = RegWriteFn { (valid, data) =>
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when(valid && engine.io.ready) { writeData := data }
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engine.io.ready
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}
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val status = Cat(0.U(30.W), engine.io.busy, engine.io.ready)
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node.regmap(
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0x00 -> Seq(RegField.w(32, commandWrite,
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RegFieldDesc("command", "bits[3:0] register address, bit8 read; write starts one 48-clock frame"))),
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0x04 -> Seq(RegField.w(32, writeDataWrite,
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RegFieldDesc("write_data", "32-bit MAX2771 register write data"))),
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0x08 -> Seq(RegField.r(32, engine.io.read_data,
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RegFieldDesc("read_data", "last 32-bit MAX2771 register read data"))),
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0x0c -> Seq(RegField.r(32, status,
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RegFieldDesc("status", "bit0 ready, bit1 busy"))),
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0x10 -> Seq(RegField.r(32, params.inputClockHz.U,
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RegFieldDesc("input_clock_hz", "peripheral input clock frequency"))),
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0x14 -> Seq(RegField.r(32, params.actualSclkHz.U,
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RegFieldDesc("sclk_hz", "actual integer MAX2771 serial clock frequency"))),
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0x18 -> Seq(RegField.r(32, params.halfPeriodCycles.U,
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RegFieldDesc("half_period_cycles", "input-clock cycles per SCLK half-period"))),
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0x1c -> Seq(RegField.r(32, "h4d415831".U,
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RegFieldDesc("identification", "ASCII MAX1 peripheral identification")))
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)
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}
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}
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