onur
33 lines
1.2 KiB
Systemverilog
33 lines
1.2 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module AMOALU(
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input [7:0] io_mask,
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input [4:0] io_cmd,
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input [63:0] io_lhs,
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io_rhs,
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output [63:0] io_out_unmasked
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);
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wire _logic_xor_T_1 = io_cmd == 5'hA;
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wire logic_and = _logic_xor_T_1 | io_cmd == 5'hB;
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wire logic_xor = io_cmd == 5'h9 | _logic_xor_T_1;
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wire [63:0] adder_out_mask = {32'hFFFFFFFF, io_mask[3], 31'h7FFFFFFF};
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assign io_out_unmasked =
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io_cmd == 5'h8
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? (io_lhs & adder_out_mask) + (io_rhs & adder_out_mask)
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: logic_and | logic_xor
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? (logic_and ? io_lhs & io_rhs : 64'h0) | (logic_xor ? io_lhs ^ io_rhs : 64'h0)
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: ((io_mask[4]
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? (io_lhs[63] == io_rhs[63]
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? io_lhs[63:32] < io_rhs[63:32] | io_lhs[63:32] == io_rhs[63:32]
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& io_lhs[31:0] < io_rhs[31:0]
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: io_cmd[1] ? io_rhs[63] : io_lhs[63])
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: io_lhs[31] == io_rhs[31]
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? io_lhs[31:0] < io_rhs[31:0]
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: io_cmd[1] ? io_rhs[31] : io_lhs[31])
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? io_cmd == 5'hC | io_cmd == 5'hE
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: io_cmd == 5'hD | io_cmd == 5'hF)
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? io_lhs
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: io_rhs;
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endmodule
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