onur
108 lines
3.2 KiB
Systemverilog
108 lines
3.2 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module AsyncQueueSource_TLBundleA_a9d32s1k1z2u(
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input clock,
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reset,
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output io_enq_ready,
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input io_enq_valid,
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input [2:0] io_enq_bits_opcode,
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input [8:0] io_enq_bits_address,
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input [31:0] io_enq_bits_data,
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output [2:0] io_async_mem_0_opcode,
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output [8:0] io_async_mem_0_address,
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output [31:0] io_async_mem_0_data,
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input io_async_ridx,
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output io_async_widx,
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input io_async_safe_ridx_valid,
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output io_async_safe_widx_valid,
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io_async_safe_source_reset_n,
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input io_async_safe_sink_reset_n
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);
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wire io_enq_ready_0;
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wire _sink_valid_io_out;
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wire _sink_extend_io_out;
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wire _source_valid_0_io_out;
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wire _ridx_ridx_gray_io_q;
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reg [2:0] mem_0_opcode;
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reg [8:0] mem_0_address;
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reg [31:0] mem_0_data;
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wire _widx_T_1 = io_enq_ready_0 & io_enq_valid;
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reg widx_widx_bin;
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reg ready_reg;
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assign io_enq_ready_0 = ready_reg & _sink_valid_io_out;
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reg widx_gray;
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always @(posedge clock) begin
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if (_widx_T_1) begin
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mem_0_opcode <= io_enq_bits_opcode;
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mem_0_address <= io_enq_bits_address;
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mem_0_data <= io_enq_bits_data;
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end
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end // always @(posedge)
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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widx_widx_bin <= 1'h0;
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ready_reg <= 1'h0;
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widx_gray <= 1'h0;
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end
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else begin
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automatic logic widx;
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widx = _sink_valid_io_out & widx_widx_bin + _widx_T_1;
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widx_widx_bin <= widx;
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ready_reg <= _sink_valid_io_out & widx != ~_ridx_ridx_gray_io_q;
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widx_gray <= widx;
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end
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end // always @(posedge, posedge)
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`ifdef ENABLE_INITIAL_REG_
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`ifdef FIRRTL_BEFORE_INITIAL
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`FIRRTL_BEFORE_INITIAL
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`endif // FIRRTL_BEFORE_INITIAL
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initial begin
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if (reset) begin
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widx_widx_bin = 1'h0;
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ready_reg = 1'h0;
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widx_gray = 1'h0;
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end
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL
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`FIRRTL_AFTER_INITIAL
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`endif // FIRRTL_AFTER_INITIAL
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`endif // ENABLE_INITIAL_REG_
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AsyncResetSynchronizerShiftReg_w1_d3_i0 ridx_ridx_gray (
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.clock (clock),
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.reset (reset),
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.io_d (io_async_ridx),
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.io_q (_ridx_ridx_gray_io_q)
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);
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AsyncValidSync source_valid_0 (
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.io_in (1'h1),
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.io_out (_source_valid_0_io_out),
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.clock (clock),
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.reset (reset | ~io_async_safe_sink_reset_n)
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);
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AsyncValidSync source_valid_1 (
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.io_in (_source_valid_0_io_out),
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.io_out (io_async_safe_widx_valid),
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.clock (clock),
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.reset (reset | ~io_async_safe_sink_reset_n)
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);
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AsyncValidSync sink_extend (
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.io_in (io_async_safe_ridx_valid),
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.io_out (_sink_extend_io_out),
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.clock (clock),
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.reset (reset | ~io_async_safe_sink_reset_n)
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);
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AsyncValidSync sink_valid (
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.io_in (_sink_extend_io_out),
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.io_out (_sink_valid_io_out),
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.clock (clock),
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.reset (reset)
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);
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assign io_enq_ready = io_enq_ready_0;
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assign io_async_mem_0_opcode = mem_0_opcode;
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assign io_async_mem_0_address = mem_0_address;
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assign io_async_mem_0_data = mem_0_data;
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assign io_async_widx = widx_gray;
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assign io_async_safe_source_reset_n = ~reset;
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endmodule
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