onur
42 lines
900 B
Systemverilog
42 lines
900 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0(
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input clock,
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reset,
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io_d,
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output io_q
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);
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reg sync_0;
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reg sync_1;
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reg sync_2;
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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sync_0 <= 1'h0;
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sync_1 <= 1'h0;
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sync_2 <= 1'h0;
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end
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else begin
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sync_0 <= sync_1;
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sync_1 <= sync_2;
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sync_2 <= io_d;
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end
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end // always @(posedge, posedge)
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`ifdef ENABLE_INITIAL_REG_
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`ifdef FIRRTL_BEFORE_INITIAL
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`FIRRTL_BEFORE_INITIAL
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`endif // FIRRTL_BEFORE_INITIAL
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initial begin
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if (reset) begin
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sync_0 = 1'h0;
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sync_1 = 1'h0;
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sync_2 = 1'h0;
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end
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL
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`FIRRTL_AFTER_INITIAL
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`endif // FIRRTL_AFTER_INITIAL
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`endif // ENABLE_INITIAL_REG_
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assign io_q = sync_0;
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endmodule
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