gps/hardware/generated/genesys2-soc-verilog/AsyncResetSynchronizerShiftReg_w1_d3_i0_1.sv

// Generated by CIRCT firtool-1.151.0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_1(
  input  clock,
         reset,
         io_d,
  output io_q
);

  AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain (
    .clock (clock),
    .reset (reset),
    .io_d  (io_d),
    .io_q  (io_q)
  );
endmodule