onur
17 lines
315 B
Systemverilog
17 lines
315 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module ClockCrossingReg_w15(
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input clock,
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input [14:0] io_d,
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output [14:0] io_q,
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input io_en
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);
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reg [14:0] cdc_reg;
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always @(posedge clock) begin
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if (io_en)
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cdc_reg <= io_d;
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end // always @(posedge)
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assign io_q = cdc_reg;
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endmodule
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