onur
31 lines
1.3 KiB
Systemverilog
31 lines
1.3 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module ClockGroupAggregator_aggregator(
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input auto_in_member_aggregator_3_clock,
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auto_in_member_aggregator_3_reset,
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auto_in_member_aggregator_2_clock,
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auto_in_member_aggregator_2_reset,
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auto_in_member_aggregator_1_clock,
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auto_in_member_aggregator_1_reset,
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auto_in_member_aggregator_0_clock,
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auto_in_member_aggregator_0_reset,
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output auto_out_member_sbus_3_clock,
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auto_out_member_sbus_3_reset,
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auto_out_member_sbus_2_clock,
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auto_out_member_sbus_2_reset,
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auto_out_member_sbus_1_clock,
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auto_out_member_sbus_1_reset,
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auto_out_member_sbus_0_clock,
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auto_out_member_sbus_0_reset
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);
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assign auto_out_member_sbus_3_clock = auto_in_member_aggregator_3_clock;
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assign auto_out_member_sbus_3_reset = auto_in_member_aggregator_3_reset;
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assign auto_out_member_sbus_2_clock = auto_in_member_aggregator_2_clock;
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assign auto_out_member_sbus_2_reset = auto_in_member_aggregator_2_reset;
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assign auto_out_member_sbus_1_clock = auto_in_member_aggregator_1_clock;
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assign auto_out_member_sbus_1_reset = auto_in_member_aggregator_1_reset;
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assign auto_out_member_sbus_0_clock = auto_in_member_aggregator_0_clock;
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assign auto_out_member_sbus_0_reset = auto_in_member_aggregator_0_reset;
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endmodule
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