onur
31 lines
1010 B
Systemverilog
31 lines
1010 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module DCacheDataArray(
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input clock,
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io_req_valid,
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input [19:0] io_req_bits_addr,
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input io_req_bits_write,
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input [63:0] io_req_bits_wdata,
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input [7:0] io_req_bits_eccMask,
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output [63:0] io_resp_0
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);
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wire rockettile_dcache_data_arrays_0_rdata_data_en;
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wire rockettile_dcache_data_arrays_0_rdata_MPORT_en;
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assign rockettile_dcache_data_arrays_0_rdata_MPORT_en =
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io_req_valid & io_req_bits_write;
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assign rockettile_dcache_data_arrays_0_rdata_data_en =
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io_req_valid & ~io_req_bits_write;
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rockettile_dcache_data_arrays_0_131072x64 rockettile_dcache_data_arrays_0_ext (
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.RW0_addr (io_req_bits_addr[19:3]),
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.RW0_en
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(rockettile_dcache_data_arrays_0_rdata_data_en
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| rockettile_dcache_data_arrays_0_rdata_MPORT_en),
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.RW0_clk (clock),
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.RW0_wmode (io_req_bits_write),
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.RW0_wdata (io_req_bits_wdata),
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.RW0_rdata (io_resp_0),
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.RW0_wmask (io_req_bits_eccMask)
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);
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endmodule
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