onur
173 lines
6.4 KiB
Systemverilog
173 lines
6.4 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module DivSqrtRawFN_small_1(
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input clock,
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reset,
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output io_inReady,
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input io_inValid,
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io_sqrtOp,
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io_a_isNaN,
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io_a_isInf,
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io_a_isZero,
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io_a_sign,
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input [12:0] io_a_sExp,
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input [53:0] io_a_sig,
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input io_b_isNaN,
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io_b_isInf,
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io_b_isZero,
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io_b_sign,
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input [12:0] io_b_sExp,
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input [53:0] io_b_sig,
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input [2:0] io_roundingMode,
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output io_rawOutValid_div,
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io_rawOutValid_sqrt,
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output [2:0] io_roundingModeOut,
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output io_invalidExc,
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io_infiniteExc,
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io_rawOut_isNaN,
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io_rawOut_isInf,
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io_rawOut_isZero,
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io_rawOut_sign,
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output [12:0] io_rawOut_sExp,
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output [55:0] io_rawOut_sig
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);
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reg [5:0] cycleNum;
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reg inReady;
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reg rawOutValid;
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reg sqrtOp_Z;
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reg majorExc_Z;
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reg isNaN_Z;
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reg isInf_Z;
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reg isZero_Z;
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reg sign_Z;
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reg [12:0] sExp_Z;
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reg [52:0] fractB_Z;
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reg [2:0] roundingMode_Z;
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reg [54:0] rem_Z;
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reg notZeroRem_Z;
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reg [54:0] sigX_Z;
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always @(posedge clock) begin
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automatic logic oddSqrt_S = io_sqrtOp & io_a_sExp[0];
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automatic logic entering;
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automatic logic _sigX_Z_T_7;
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automatic logic [55:0] rem;
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automatic logic [54:0] _trialTerm_T_3 =
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inReady & ~io_sqrtOp ? {io_b_sig, 1'h0} : 55'h0;
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automatic logic [54:0] _trialTerm_T_9;
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automatic logic [57:0] trialRem;
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automatic logic newBit;
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automatic logic _GEN;
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entering = inReady & io_inValid;
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_sigX_Z_T_7 = inReady & oddSqrt_S;
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rem =
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{1'h0, inReady & ~oddSqrt_S ? {io_a_sig, 1'h0} : 55'h0}
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| (_sigX_Z_T_7 ? {io_a_sig[52:51] - 2'h1, io_a_sig[50:0], 3'h0} : 56'h0)
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| (inReady ? 56'h0 : {rem_Z, 1'h0});
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_trialTerm_T_9 =
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{_trialTerm_T_3[54],
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_trialTerm_T_3[53:0] | {inReady & io_sqrtOp & ~(io_a_sExp[0]), 53'h0}}
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| (_sigX_Z_T_7 ? 55'h50000000000000 : 55'h0);
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trialRem =
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{2'h0, rem}
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- {2'h0,
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{1'h0,
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_trialTerm_T_9[54],
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{_trialTerm_T_9[53], _trialTerm_T_9[52:0] | (inReady ? 53'h0 : fractB_Z)}
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| {~inReady & ~sqrtOp_Z, 53'h0}}
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| (~inReady & sqrtOp_Z ? {sigX_Z, 1'h0} : 56'h0)};
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newBit = $signed(trialRem) > -58'sh1;
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_GEN = entering | ~inReady;
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if (reset) begin
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cycleNum <= 6'h0;
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inReady <= 1'h1;
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rawOutValid <= 1'h0;
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end
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else if ((|cycleNum) | entering) begin
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automatic logic specialCaseA_S = io_a_isNaN | io_a_isInf | io_a_isZero;
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automatic logic normalCase_S =
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io_sqrtOp
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? ~specialCaseA_S & ~io_a_sign
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: ~specialCaseA_S & ~(io_b_isNaN | io_b_isInf | io_b_isZero);
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automatic logic skipCycle2 = cycleNum == 6'h3 & sigX_Z[54];
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automatic logic [5:0] _cycleNum_T_15;
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_cycleNum_T_15 =
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{5'h0, entering & ~normalCase_S}
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| (entering & normalCase_S
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? (io_sqrtOp ? (io_a_sExp[0] ? 6'h35 : 6'h36) : 6'h37)
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: 6'h0) | (entering | skipCycle2 ? 6'h0 : cycleNum - 6'h1);
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cycleNum <= {_cycleNum_T_15[5:1], _cycleNum_T_15[0] | skipCycle2};
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inReady <=
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entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 6'h1 < 6'h2
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| skipCycle2;
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rawOutValid <=
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entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 6'h1 == 6'h1
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| skipCycle2;
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end
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if (entering) begin
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automatic logic notSigNaNIn_invalidExc_S_div =
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io_a_isZero & io_b_isZero | io_a_isInf & io_b_isInf;
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automatic logic notSigNaNIn_invalidExc_S_sqrt =
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~io_a_isNaN & ~io_a_isZero & io_a_sign;
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automatic logic [13:0] sExpQuot_S_div =
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{io_a_sExp[12], io_a_sExp} + {{3{io_b_sExp[11]}}, ~(io_b_sExp[10:0])};
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sqrtOp_Z <= io_sqrtOp;
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majorExc_Z <=
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io_sqrtOp
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? io_a_isNaN & ~(io_a_sig[51]) | notSigNaNIn_invalidExc_S_sqrt
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: io_a_isNaN & ~(io_a_sig[51]) | io_b_isNaN & ~(io_b_sig[51])
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| notSigNaNIn_invalidExc_S_div | ~io_a_isNaN & ~io_a_isInf & io_b_isZero;
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isNaN_Z <=
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io_sqrtOp
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? io_a_isNaN | notSigNaNIn_invalidExc_S_sqrt
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: io_a_isNaN | io_b_isNaN | notSigNaNIn_invalidExc_S_div;
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isInf_Z <= ~io_sqrtOp & io_b_isZero | io_a_isInf;
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isZero_Z <= ~io_sqrtOp & io_b_isInf | io_a_isZero;
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sign_Z <= io_a_sign ^ ~io_sqrtOp & io_b_sign;
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sExp_Z <=
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io_sqrtOp
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? {io_a_sExp[12], io_a_sExp[12:1]} + 13'h400
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: {$signed(sExpQuot_S_div) > 14'shDFF ? 4'h6 : sExpQuot_S_div[12:9],
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sExpQuot_S_div[8:0]};
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roundingMode_Z <= io_roundingMode;
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end
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if (entering | ~inReady & sqrtOp_Z) begin
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automatic logic [52:0] _fractB_Z_T_4 =
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inReady & ~io_sqrtOp ? {io_b_sig[51:0], 1'h0} : 53'h0;
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automatic logic _fractB_Z_T_10 = inReady & io_sqrtOp;
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automatic logic [52:0] _fractB_Z_T_20 =
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{_fractB_Z_T_4[52], _fractB_Z_T_4[51:0] | {_fractB_Z_T_10 & io_a_sExp[0], 51'h0}}
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| {_fractB_Z_T_10 & ~(io_a_sExp[0]), 52'h0};
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fractB_Z <=
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{_fractB_Z_T_20[52], _fractB_Z_T_20[51:0] | (inReady ? 52'h0 : fractB_Z[52:1])};
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end
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if (_GEN) begin
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automatic logic [54:0] _sigX_Z_T_3;
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automatic logic [53:0] _GEN_0;
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automatic logic [63:0] _bitMask_T = 64'h1 << cycleNum;
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_sigX_Z_T_3 = inReady & ~io_sqrtOp ? {newBit, 54'h0} : 55'h0;
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_GEN_0 = _sigX_Z_T_3[53:0] | {inReady & io_sqrtOp, 53'h0};
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rem_Z <= newBit ? trialRem[54:0] : rem[54:0];
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sigX_Z <=
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{_sigX_Z_T_3[54],
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_GEN_0[53],
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_GEN_0[52:0] | (_sigX_Z_T_7 ? {newBit, 52'h0} : 53'h0)}
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| (inReady ? 55'h0 : sigX_Z) | (~inReady & newBit ? _bitMask_T[56:2] : 55'h0);
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end
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if (_GEN & (inReady | newBit))
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notZeroRem_Z <= |trialRem;
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end // always @(posedge)
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assign io_inReady = inReady;
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assign io_rawOutValid_div = rawOutValid & ~sqrtOp_Z;
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assign io_rawOutValid_sqrt = rawOutValid & sqrtOp_Z;
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assign io_roundingModeOut = roundingMode_Z;
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assign io_invalidExc = majorExc_Z & isNaN_Z;
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assign io_infiniteExc = majorExc_Z & ~isNaN_Z;
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assign io_rawOut_isNaN = isNaN_Z;
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assign io_rawOut_isInf = isInf_Z;
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assign io_rawOut_isZero = isZero_Z;
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assign io_rawOut_sign = sign_Z;
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assign io_rawOut_sExp = sExp_Z;
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assign io_rawOut_sig = {sigX_Z, notZeroRem_Z};
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endmodule
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