onur
61 lines
2.3 KiB
Systemverilog
61 lines
2.3 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module DivSqrtRecFNToRaw_small(
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input clock,
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reset,
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output io_inReady,
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input io_inValid,
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io_sqrtOp,
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input [32:0] io_a,
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io_b,
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input [2:0] io_roundingMode,
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output io_rawOutValid_div,
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io_rawOutValid_sqrt,
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output [2:0] io_roundingModeOut,
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output io_invalidExc,
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io_infiniteExc,
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io_rawOut_isNaN,
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io_rawOut_isInf,
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io_rawOut_isZero,
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io_rawOut_sign,
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output [9:0] io_rawOut_sExp,
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output [26:0] io_rawOut_sig
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);
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wire _divSqrtRawFN_io_a_out_sig_T = |(io_a[31:29]);
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wire divSqrtRawFN_io_a_isSpecial = &(io_a[31:30]);
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wire _divSqrtRawFN_io_b_out_sig_T = |(io_b[31:29]);
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wire divSqrtRawFN_io_b_isSpecial = &(io_b[31:30]);
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DivSqrtRawFN_small divSqrtRawFN (
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.clock (clock),
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.reset (reset),
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.io_inReady (io_inReady),
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.io_inValid (io_inValid),
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.io_sqrtOp (io_sqrtOp),
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.io_a_isNaN (divSqrtRawFN_io_a_isSpecial & io_a[29]),
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.io_a_isInf (divSqrtRawFN_io_a_isSpecial & ~(io_a[29])),
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.io_a_isZero (~_divSqrtRawFN_io_a_out_sig_T),
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.io_a_sign (io_a[32]),
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.io_a_sExp ({1'h0, io_a[31:23]}),
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.io_a_sig ({1'h0, _divSqrtRawFN_io_a_out_sig_T, io_a[22:0]}),
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.io_b_isNaN (divSqrtRawFN_io_b_isSpecial & io_b[29]),
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.io_b_isInf (divSqrtRawFN_io_b_isSpecial & ~(io_b[29])),
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.io_b_isZero (~_divSqrtRawFN_io_b_out_sig_T),
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.io_b_sign (io_b[32]),
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.io_b_sExp ({1'h0, io_b[31:23]}),
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.io_b_sig ({1'h0, _divSqrtRawFN_io_b_out_sig_T, io_b[22:0]}),
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.io_roundingMode (io_roundingMode),
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.io_rawOutValid_div (io_rawOutValid_div),
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.io_rawOutValid_sqrt (io_rawOutValid_sqrt),
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.io_roundingModeOut (io_roundingModeOut),
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.io_invalidExc (io_invalidExc),
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.io_infiniteExc (io_infiniteExc),
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.io_rawOut_isNaN (io_rawOut_isNaN),
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.io_rawOut_isInf (io_rawOut_isInf),
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.io_rawOut_isZero (io_rawOut_isZero),
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.io_rawOut_sign (io_rawOut_sign),
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.io_rawOut_sExp (io_rawOut_sExp),
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.io_rawOut_sig (io_rawOut_sig)
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);
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endmodule
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