onur
51 lines
2.0 KiB
Systemverilog
51 lines
2.0 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module FPGASPIClockSinkDomain(
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output auto_dev_in_a_ready,
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input auto_dev_in_a_valid,
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input [2:0] auto_dev_in_a_bits_opcode,
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input [1:0] auto_dev_in_a_bits_size,
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input [5:0] auto_dev_in_a_bits_source,
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input [28:0] auto_dev_in_a_bits_address,
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input [7:0] auto_dev_in_a_bits_mask,
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input [63:0] auto_dev_in_a_bits_data,
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input auto_dev_in_d_ready,
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output auto_dev_in_d_valid,
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output [2:0] auto_dev_in_d_bits_opcode,
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output [1:0] auto_dev_in_d_bits_size,
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output [5:0] auto_dev_in_d_bits_source,
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output [63:0] auto_dev_in_d_bits_data,
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output [3:0] auto_dev_dq_oe_out,
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auto_dev_dq_out_out,
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input [3:0] auto_dev_dq_in_in,
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output auto_dev_csn_out,
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auto_dev_sck_out,
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input auto_clock_in_clock,
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auto_clock_in_reset
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);
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TLFpgaSPI dev (
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.clock (auto_clock_in_clock),
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.reset (auto_clock_in_reset),
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.auto_in_a_ready (auto_dev_in_a_ready),
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.auto_in_a_valid (auto_dev_in_a_valid),
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.auto_in_a_bits_opcode (auto_dev_in_a_bits_opcode),
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.auto_in_a_bits_size (auto_dev_in_a_bits_size),
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.auto_in_a_bits_source (auto_dev_in_a_bits_source),
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.auto_in_a_bits_address (auto_dev_in_a_bits_address),
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.auto_in_a_bits_mask (auto_dev_in_a_bits_mask),
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.auto_in_a_bits_data (auto_dev_in_a_bits_data),
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.auto_in_d_ready (auto_dev_in_d_ready),
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.auto_in_d_valid (auto_dev_in_d_valid),
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.auto_in_d_bits_opcode (auto_dev_in_d_bits_opcode),
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.auto_in_d_bits_size (auto_dev_in_d_bits_size),
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.auto_in_d_bits_source (auto_dev_in_d_bits_source),
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.auto_in_d_bits_data (auto_dev_in_d_bits_data),
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.auto_dq_oe_out (auto_dev_dq_oe_out),
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.auto_dq_out_out (auto_dev_dq_out_out),
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.auto_dq_in_in (auto_dev_dq_in_in),
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.auto_csn_out (auto_dev_csn_out),
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.auto_sck_out (auto_dev_sck_out)
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);
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endmodule
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