onur
260 lines
12 KiB
Systemverilog
260 lines
12 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module FPToInt(
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input clock,
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io_in_valid,
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io_in_bits_ren2,
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input [1:0] io_in_bits_typeTagOut,
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input io_in_bits_wflags,
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input [2:0] io_in_bits_rm,
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input [1:0] io_in_bits_typ,
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io_in_bits_fmt,
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input [64:0] io_in_bits_in1,
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io_in_bits_in2,
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output [2:0] io_out_bits_in_rm,
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output [64:0] io_out_bits_in_in1,
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io_out_bits_in_in2,
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output io_out_bits_lt,
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output [63:0] io_out_bits_store,
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io_out_bits_toint,
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output [4:0] io_out_bits_exc
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);
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wire [63:0] toint;
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wire _narrow_io_signedOut_T;
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wire intType;
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wire [2:0] _narrow_io_intExceptionFlags;
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wire [63:0] _conv_io_out;
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wire [2:0] _conv_io_intExceptionFlags;
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wire _dcmp_io_lt;
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wire _dcmp_io_eq;
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wire [4:0] _dcmp_io_exceptionFlags;
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reg in_ren2;
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reg [1:0] in_typeTagOut;
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reg in_wflags;
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reg [2:0] in_rm;
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reg [1:0] in_typ;
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reg [1:0] in_fmt;
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reg [64:0] in_in1;
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reg [64:0] in_in2;
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wire [12:0] _GEN = {1'h0, in_in1[63:52]};
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wire [52:0] _toint_ieee_unrecoded_denormFract_T_1 =
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{1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52];
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wire toint_ieee_prevUnrecoded_rawIn_isSpecial = &{in_in1[52], in_in1[30]};
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wire toint_ieee_prevUnrecoded_rawIn_isInf =
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toint_ieee_prevUnrecoded_rawIn_isSpecial & ~(in_in1[29]);
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wire toint_ieee_prevUnrecoded_isSubnormal =
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$signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82;
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wire [23:0] _toint_ieee_prevUnrecoded_denormFract_T_1 =
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{1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23];
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wire toint_ieee_unrecoded_rawIn_isSpecial_1 = &(in_in1[63:62]);
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wire toint_ieee_unrecoded_rawIn_1_isInf =
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toint_ieee_unrecoded_rawIn_isSpecial_1 & ~(in_in1[61]);
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wire toint_ieee_unrecoded_isSubnormal_1 = $signed(_GEN) < 13'sh402;
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wire [52:0] _toint_ieee_unrecoded_denormFract_T_3 =
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{1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52];
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wire [51:0] toint_ieee_unrecoded_fractOut_1 =
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toint_ieee_unrecoded_isSubnormal_1
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? _toint_ieee_unrecoded_denormFract_T_3[51:0]
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: toint_ieee_unrecoded_rawIn_1_isInf ? 52'h0 : in_in1[51:0];
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wire toint_ieee_prevUnrecoded_rawIn_isSpecial_1 = &{in_in1[52], in_in1[30]};
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wire toint_ieee_prevUnrecoded_rawIn_1_isInf =
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toint_ieee_prevUnrecoded_rawIn_isSpecial_1 & ~(in_in1[29]);
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wire toint_ieee_prevUnrecoded_isSubnormal_1 =
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$signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82;
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wire [23:0] _toint_ieee_prevUnrecoded_denormFract_T_3 =
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{1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23];
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wire [63:0] toint_ieee =
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in_typeTagOut[0]
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? {in_in1[64],
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(toint_ieee_unrecoded_isSubnormal_1 ? 11'h0 : in_in1[62:52] + 11'h3FF)
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| {11{toint_ieee_unrecoded_rawIn_isSpecial_1 & in_in1[61]
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| toint_ieee_unrecoded_rawIn_1_isInf}},
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toint_ieee_unrecoded_fractOut_1[51:32],
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(&(in_in1[63:61]))
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? {in_in1[31],
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(toint_ieee_prevUnrecoded_isSubnormal_1 ? 8'h0 : in_in1[30:23] + 8'h7F)
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| {8{toint_ieee_prevUnrecoded_rawIn_isSpecial_1 & in_in1[29]
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| toint_ieee_prevUnrecoded_rawIn_1_isInf}},
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toint_ieee_prevUnrecoded_isSubnormal_1
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? _toint_ieee_prevUnrecoded_denormFract_T_3[22:0]
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: toint_ieee_prevUnrecoded_rawIn_1_isInf ? 23'h0 : in_in1[22:0]}
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: toint_ieee_unrecoded_fractOut_1[31:0]}
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: {2{(&(in_in1[63:61]))
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? {in_in1[31],
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(toint_ieee_prevUnrecoded_isSubnormal ? 8'h0 : in_in1[30:23] + 8'h7F)
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| {8{toint_ieee_prevUnrecoded_rawIn_isSpecial & in_in1[29]
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| toint_ieee_prevUnrecoded_rawIn_isInf}},
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toint_ieee_prevUnrecoded_isSubnormal
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? _toint_ieee_prevUnrecoded_denormFract_T_1[22:0]
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: toint_ieee_prevUnrecoded_rawIn_isInf ? 23'h0 : in_in1[22:0]}
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: $signed(_GEN) < 13'sh402
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? _toint_ieee_unrecoded_denormFract_T_1[31:0]
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: (&(in_in1[63:62])) & ~(in_in1[61]) ? 32'h0 : in_in1[31:0]}};
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wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_1 =
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{1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52];
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wire io_out_bits_store_prevUnrecoded_rawIn_isSpecial = &{in_in1[52], in_in1[30]};
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wire io_out_bits_store_prevUnrecoded_rawIn_isInf =
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io_out_bits_store_prevUnrecoded_rawIn_isSpecial & ~(in_in1[29]);
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wire io_out_bits_store_prevUnrecoded_isSubnormal =
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$signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82;
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wire [23:0] _io_out_bits_store_prevUnrecoded_denormFract_T_1 =
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{1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23];
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wire io_out_bits_store_unrecoded_rawIn_isSpecial_1 = &(in_in1[63:62]);
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wire io_out_bits_store_unrecoded_rawIn_1_isInf =
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io_out_bits_store_unrecoded_rawIn_isSpecial_1 & ~(in_in1[61]);
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wire io_out_bits_store_unrecoded_isSubnormal_1 = $signed(_GEN) < 13'sh402;
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wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_3 =
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{1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52];
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wire [51:0] io_out_bits_store_unrecoded_fractOut_1 =
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io_out_bits_store_unrecoded_isSubnormal_1
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? _io_out_bits_store_unrecoded_denormFract_T_3[51:0]
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: io_out_bits_store_unrecoded_rawIn_1_isInf ? 52'h0 : in_in1[51:0];
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wire io_out_bits_store_prevUnrecoded_rawIn_isSpecial_1 =
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&{in_in1[52], in_in1[30]};
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wire io_out_bits_store_prevUnrecoded_rawIn_1_isInf =
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io_out_bits_store_prevUnrecoded_rawIn_isSpecial_1 & ~(in_in1[29]);
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wire io_out_bits_store_prevUnrecoded_isSubnormal_1 =
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$signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82;
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wire [23:0] _io_out_bits_store_prevUnrecoded_denormFract_T_3 =
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{1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23];
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wire [8:0] _classify_out_expOut_commonCase_T = in_in1[60:52] - 9'h100;
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wire [8:0] classify_out_expOut =
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in_in1[63:61] == 3'h0 | in_in1[63:61] > 3'h5
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? {in_in1[63:61], _classify_out_expOut_commonCase_T[5:0]}
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: _classify_out_expOut_commonCase_T;
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wire _classify_out_isNormal_T = classify_out_expOut[8:7] == 2'h1;
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wire classify_out_isSubnormal =
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classify_out_expOut[8:6] == 3'h1 | _classify_out_isNormal_T
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& classify_out_expOut[6:0] < 7'h2;
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wire classify_out_isNormal =
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_classify_out_isNormal_T & (|(classify_out_expOut[6:1]))
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| classify_out_expOut[8:7] == 2'h2;
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wire classify_out_isZero = classify_out_expOut[8:6] == 3'h0;
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wire classify_out_isInf =
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(&(classify_out_expOut[8:7])) & ~(classify_out_expOut[6]);
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wire classify_out_isNaN = &(classify_out_expOut[8:6]);
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wire _classify_out_isNormal_T_4 = in_in1[63:62] == 2'h1;
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wire classify_out_isSubnormal_1 =
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in_in1[63:61] == 3'h1 | _classify_out_isNormal_T_4 & in_in1[61:52] < 10'h2;
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wire classify_out_isNormal_1 =
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_classify_out_isNormal_T_4 & (|(in_in1[61:53])) | in_in1[63:62] == 2'h2;
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wire classify_out_isZero_1 = in_in1[63:61] == 3'h0;
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wire classify_out_isInf_1 = (&(in_in1[63:62])) & ~(in_in1[61]);
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wire classify_out_isNaN_1 = &(in_in1[63:61]);
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assign intType = in_wflags ? ~in_ren2 & in_typ[1] : ~(in_rm[0]) & in_fmt[0];
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assign _narrow_io_signedOut_T = in_typ[0];
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wire excSign = in_in1[64] & in_in1[63:61] != 3'h7;
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wire invalid = _conv_io_intExceptionFlags[2] | _narrow_io_intExceptionFlags[1];
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assign toint =
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in_wflags
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? (in_ren2
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? {63'h0, |(~(in_rm[1:0]) & {_dcmp_io_lt, _dcmp_io_eq})}
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| {toint_ieee[63:32], 32'h0}
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: ~(in_typ[1]) & invalid
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? {_conv_io_out[63:32], ~_narrow_io_signedOut_T == excSign, {31{~excSign}}}
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: _conv_io_out)
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: in_rm[0]
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? {54'h0,
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in_typeTagOut[0]
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? {classify_out_isNaN_1 & in_in1[51],
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classify_out_isNaN_1 & ~(in_in1[51]),
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classify_out_isInf_1 & ~(in_in1[64]),
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classify_out_isNormal_1 & ~(in_in1[64]),
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classify_out_isSubnormal_1 & ~(in_in1[64]),
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classify_out_isZero_1 & ~(in_in1[64]),
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classify_out_isZero_1 & in_in1[64],
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classify_out_isSubnormal_1 & in_in1[64],
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classify_out_isNormal_1 & in_in1[64],
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classify_out_isInf_1 & in_in1[64]}
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: {classify_out_isNaN & in_in1[51],
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classify_out_isNaN & ~(in_in1[51]),
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classify_out_isInf & ~(in_in1[64]),
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classify_out_isNormal & ~(in_in1[64]),
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classify_out_isSubnormal & ~(in_in1[64]),
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classify_out_isZero & ~(in_in1[64]),
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classify_out_isZero & in_in1[64],
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classify_out_isSubnormal & in_in1[64],
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classify_out_isNormal & in_in1[64],
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classify_out_isInf & in_in1[64]}} | {toint_ieee[63:32], 32'h0}
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: toint_ieee;
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always @(posedge clock) begin
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if (io_in_valid) begin
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in_ren2 <= io_in_bits_ren2;
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in_typeTagOut <= io_in_bits_typeTagOut;
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in_wflags <= io_in_bits_wflags;
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in_rm <= io_in_bits_rm;
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in_typ <= io_in_bits_typ;
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in_fmt <= io_in_bits_fmt;
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in_in1 <= io_in_bits_in1;
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in_in2 <= io_in_bits_in2;
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end
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end // always @(posedge)
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CompareRecFN dcmp (
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.io_a (in_in1),
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.io_b (in_in2),
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.io_signaling (~(in_rm[1])),
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.io_lt (_dcmp_io_lt),
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.io_eq (_dcmp_io_eq),
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.io_exceptionFlags (_dcmp_io_exceptionFlags)
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);
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RecFNToIN conv (
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.io_in (in_in1),
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.io_roundingMode (in_rm),
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.io_signedOut (~_narrow_io_signedOut_T),
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.io_out (_conv_io_out),
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.io_intExceptionFlags (_conv_io_intExceptionFlags)
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);
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RecFNToIN_1 narrow (
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.io_in (in_in1),
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.io_roundingMode (in_rm),
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.io_signedOut (~_narrow_io_signedOut_T),
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.io_intExceptionFlags (_narrow_io_intExceptionFlags)
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);
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assign io_out_bits_in_rm = in_rm;
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assign io_out_bits_in_in1 = in_in1;
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assign io_out_bits_in_in2 = in_in2;
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assign io_out_bits_lt =
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_dcmp_io_lt | $signed(in_in1) < 65'sh0 & $signed(in_in2) > -65'sh1;
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assign io_out_bits_store =
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in_typeTagOut[0]
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? {in_in1[64],
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(io_out_bits_store_unrecoded_isSubnormal_1 ? 11'h0 : in_in1[62:52] + 11'h3FF)
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| {11{io_out_bits_store_unrecoded_rawIn_isSpecial_1 & in_in1[61]
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| io_out_bits_store_unrecoded_rawIn_1_isInf}},
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io_out_bits_store_unrecoded_fractOut_1[51:32],
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(&(in_in1[63:61]))
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? {in_in1[31],
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(io_out_bits_store_prevUnrecoded_isSubnormal_1
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? 8'h0
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: in_in1[30:23] + 8'h7F)
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| {8{io_out_bits_store_prevUnrecoded_rawIn_isSpecial_1 & in_in1[29]
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| io_out_bits_store_prevUnrecoded_rawIn_1_isInf}},
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io_out_bits_store_prevUnrecoded_isSubnormal_1
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? _io_out_bits_store_prevUnrecoded_denormFract_T_3[22:0]
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: io_out_bits_store_prevUnrecoded_rawIn_1_isInf ? 23'h0 : in_in1[22:0]}
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: io_out_bits_store_unrecoded_fractOut_1[31:0]}
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: {2{(&(in_in1[63:61]))
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? {in_in1[31],
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(io_out_bits_store_prevUnrecoded_isSubnormal
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? 8'h0
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: in_in1[30:23] + 8'h7F)
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| {8{io_out_bits_store_prevUnrecoded_rawIn_isSpecial & in_in1[29]
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| io_out_bits_store_prevUnrecoded_rawIn_isInf}},
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io_out_bits_store_prevUnrecoded_isSubnormal
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? _io_out_bits_store_prevUnrecoded_denormFract_T_1[22:0]
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: io_out_bits_store_prevUnrecoded_rawIn_isInf ? 23'h0 : in_in1[22:0]}
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: $signed(_GEN) < 13'sh402
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? _io_out_bits_store_unrecoded_denormFract_T_1[31:0]
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: (&(in_in1[63:62])) & ~(in_in1[61]) ? 32'h0 : in_in1[31:0]}};
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assign io_out_bits_toint = intType ? toint : {{32{toint[31]}}, toint[31:0]};
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assign io_out_bits_exc =
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in_wflags
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? (in_ren2
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? _dcmp_io_exceptionFlags
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: in_typ[1]
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? {|(_conv_io_intExceptionFlags[2:1]), 3'h0, _conv_io_intExceptionFlags[0]}
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: {invalid, 3'h0, ~invalid & _conv_io_intExceptionFlags[0]})
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: 5'h0;
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endmodule
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