onur
133 lines
5.2 KiB
Systemverilog
133 lines
5.2 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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// Users can define 'PRINTF_COND' to add an extra gate to prints.
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`ifndef PRINTF_COND_
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`ifdef PRINTF_COND
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`define PRINTF_COND_ (`PRINTF_COND)
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`else // PRINTF_COND
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`define PRINTF_COND_ 1
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`endif // PRINTF_COND
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`endif // not def PRINTF_COND_
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module IBuf(
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input clock,
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reset,
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output io_imem_ready,
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input io_imem_valid,
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input [33:0] io_imem_bits_pc,
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input [31:0] io_imem_bits_data,
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input io_imem_bits_xcpt_pf_inst,
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io_imem_bits_xcpt_gf_inst,
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io_imem_bits_xcpt_ae_inst,
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io_imem_bits_replay,
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io_kill,
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output [33:0] io_pc,
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input io_inst_0_ready,
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output io_inst_0_valid,
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io_inst_0_bits_xcpt0_pf_inst,
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io_inst_0_bits_xcpt0_gf_inst,
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io_inst_0_bits_xcpt0_ae_inst,
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io_inst_0_bits_xcpt1_pf_inst,
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io_inst_0_bits_xcpt1_gf_inst,
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io_inst_0_bits_xcpt1_ae_inst,
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io_inst_0_bits_replay,
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io_inst_0_bits_rvc,
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output [31:0] io_inst_0_bits_inst_bits,
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output [4:0] io_inst_0_bits_inst_rd,
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io_inst_0_bits_inst_rs1,
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io_inst_0_bits_inst_rs2,
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io_inst_0_bits_inst_rs3,
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output [31:0] io_inst_0_bits_raw
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);
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wire [1:0] nReady;
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wire _exp_io_rvc;
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reg nBufValid;
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reg [33:0] buf_pc;
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reg [31:0] buf_data;
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reg buf_xcpt_pf_inst;
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reg buf_xcpt_gf_inst;
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reg buf_xcpt_ae_inst;
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reg buf_replay;
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wire [1:0] _GEN = {1'h0, io_imem_bits_pc[1]};
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wire [1:0] _nIC_T_2 = 2'h2 - _GEN;
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wire [1:0] _GEN_0 = {1'h0, nBufValid};
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wire [1:0] _nICReady_T = nReady - _GEN_0;
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wire _nBufValid_T = nReady >= _GEN_0;
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wire [1:0] _nBufValid_T_6 = _nIC_T_2 - _nICReady_T;
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wire [190:0] _icData_T_4 =
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{63'h0,
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{4{io_imem_bits_data[31:16]}},
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io_imem_bits_data,
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{2{io_imem_bits_data[15:0]}}} << {185'h0, _GEN_0 - 2'h2 - _GEN, 4'h0};
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wire [62:0] _icMask_T_2 = 63'hFFFFFFFF << {58'h0, nBufValid, 4'h0};
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wire [31:0] inst =
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_icData_T_4[95:64] & _icMask_T_2[31:0] | buf_data & ~(_icMask_T_2[31:0]);
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wire [3:0] _valid_T = 4'h1 << (io_imem_valid ? _nIC_T_2 : 2'h0) + _GEN_0;
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wire [1:0] _valid_T_1 = _valid_T[1:0] - 2'h1;
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wire [1:0] _bufMask_T_1 = (2'h1 << _GEN_0) - 2'h1;
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wire [1:0] buf_replay_0 = buf_replay ? _bufMask_T_1 : 2'h0;
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wire [1:0] ic_replay =
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buf_replay_0 | (io_imem_bits_replay ? _valid_T_1 & ~_bufMask_T_1 : 2'h0);
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wire full_insn = _exp_io_rvc | _valid_T_1[1] | buf_replay_0[0];
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wire [2:0] _io_inst_0_bits_xcpt1_WIRE_1 =
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_exp_io_rvc
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? 3'h0
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: {_bufMask_T_1[1] ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst,
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_bufMask_T_1[1] ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst,
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_bufMask_T_1[1] ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst};
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assign nReady = full_insn ? (_exp_io_rvc ? 2'h1 : 2'h2) : 2'h0;
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always @(posedge clock) begin
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automatic logic _GEN_1;
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_GEN_1 = io_imem_valid & _nBufValid_T & _nICReady_T < _nIC_T_2 & ~(_nBufValid_T_6[1]);
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if (reset)
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nBufValid <= 1'h0;
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else
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nBufValid <=
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~io_kill
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& (io_inst_0_ready
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? (_GEN_1
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? _nBufValid_T_6[0]
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: ~(_nBufValid_T | ~nBufValid) & nBufValid - nReady[0])
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: nBufValid);
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if (io_inst_0_ready & _GEN_1) begin
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automatic logic [63:0] _buf_data_T_1 =
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{{2{io_imem_bits_data[31:16]}}, io_imem_bits_data}
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>> {58'h0, _GEN + _nICReady_T, 4'h0};
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buf_pc <=
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{io_imem_bits_pc[33:2], 2'h0}
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| {32'h0, io_imem_bits_pc[1:0] + {_nICReady_T[0], 1'h0}};
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buf_data <= {16'h0, _buf_data_T_1[15:0]};
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buf_xcpt_pf_inst <= io_imem_bits_xcpt_pf_inst;
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buf_xcpt_gf_inst <= io_imem_bits_xcpt_gf_inst;
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buf_xcpt_ae_inst <= io_imem_bits_xcpt_ae_inst;
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buf_replay <= io_imem_bits_replay;
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end
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end // always @(posedge)
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RVCExpander exp (
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.io_in (inst),
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.io_out_bits (io_inst_0_bits_inst_bits),
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.io_out_rd (io_inst_0_bits_inst_rd),
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.io_out_rs1 (io_inst_0_bits_inst_rs1),
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.io_out_rs2 (io_inst_0_bits_inst_rs2),
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.io_out_rs3 (io_inst_0_bits_inst_rs3),
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.io_rvc (_exp_io_rvc)
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);
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assign io_imem_ready =
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io_inst_0_ready & _nBufValid_T & (_nICReady_T >= _nIC_T_2 | ~(_nBufValid_T_6[1]));
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assign io_pc = nBufValid ? buf_pc : io_imem_bits_pc;
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assign io_inst_0_valid = _valid_T_1[0] & full_insn;
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assign io_inst_0_bits_xcpt0_pf_inst =
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_bufMask_T_1[0] ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst;
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assign io_inst_0_bits_xcpt0_gf_inst =
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_bufMask_T_1[0] ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst;
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assign io_inst_0_bits_xcpt0_ae_inst =
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_bufMask_T_1[0] ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst;
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assign io_inst_0_bits_xcpt1_pf_inst = _io_inst_0_bits_xcpt1_WIRE_1[2];
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assign io_inst_0_bits_xcpt1_gf_inst = _io_inst_0_bits_xcpt1_WIRE_1[1];
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assign io_inst_0_bits_xcpt1_ae_inst = _io_inst_0_bits_xcpt1_WIRE_1[0];
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assign io_inst_0_bits_replay = ic_replay[0] | ~_exp_io_rvc & ic_replay[1];
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assign io_inst_0_bits_rvc = _exp_io_rvc;
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assign io_inst_0_bits_raw = inst;
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endmodule
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