onur
15 lines
267 B
Systemverilog
15 lines
267 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module IntSyncAsyncCrossingSink_n1x1(
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input clock,
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auto_in_sync_0,
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output auto_out_0
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);
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SynchronizerShiftReg_w1_d3 chain (
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.clock (clock),
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.io_d (auto_in_sync_0),
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.io_q (auto_out_0)
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);
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endmodule
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