onur
10 lines
182 B
Systemverilog
10 lines
182 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module IntSyncCrossingSource_n1x1_Registered(
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input auto_in_0,
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output auto_out_sync_0
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);
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assign auto_out_sync_0 = auto_in_0;
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endmodule
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