onur
22 lines
455 B
Systemverilog
22 lines
455 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module IntSyncCrossingSource_n1x2(
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input clock,
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reset,
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auto_in_0,
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auto_in_1,
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output auto_out_sync_0,
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auto_out_sync_1
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);
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wire [1:0] _reg_io_q;
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AsyncResetRegVec_w2_i0 reg_0 (
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.clock (clock),
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.reset (reset),
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.io_d ({auto_in_1, auto_in_0}),
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.io_q (_reg_io_q)
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);
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assign auto_out_sync_0 = _reg_io_q[0];
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assign auto_out_sync_1 = _reg_io_q[1];
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endmodule
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