onur
291 lines
24 KiB
Systemverilog
291 lines
24 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module MulAddRecFNToRaw_postMul_1(
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input io_fromPreMul_isSigNaNAny,
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io_fromPreMul_isNaNAOrB,
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io_fromPreMul_isInfA,
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io_fromPreMul_isZeroA,
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io_fromPreMul_isInfB,
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io_fromPreMul_isZeroB,
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io_fromPreMul_signProd,
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io_fromPreMul_isNaNC,
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io_fromPreMul_isInfC,
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io_fromPreMul_isZeroC,
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input [12:0] io_fromPreMul_sExpSum,
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input io_fromPreMul_doSubMags,
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io_fromPreMul_CIsDominant,
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input [5:0] io_fromPreMul_CDom_CAlignDist,
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input [54:0] io_fromPreMul_highAlignedSigC,
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input io_fromPreMul_bit0AlignedSigC,
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input [106:0] io_mulAddResult,
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input [2:0] io_roundingMode,
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output io_invalidExc,
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io_rawOut_isNaN,
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io_rawOut_isInf,
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io_rawOut_isZero,
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io_rawOut_sign,
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output [12:0] io_rawOut_sExp,
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output [55:0] io_rawOut_sig
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);
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wire roundingMode_min = io_roundingMode == 3'h2;
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wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags;
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wire [54:0] _sigSum_T_3 =
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io_mulAddResult[106]
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? io_fromPreMul_highAlignedSigC + 55'h1
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: io_fromPreMul_highAlignedSigC;
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wire [107:0] CDom_absSigSum =
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io_fromPreMul_doSubMags
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? ~{_sigSum_T_3, io_mulAddResult[105:53]}
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: {1'h0,
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io_fromPreMul_highAlignedSigC[54:53],
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_sigSum_T_3[52:0],
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io_mulAddResult[105:54]};
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wire [170:0] _CDom_mainSig_T = {63'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist;
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wire [16:0] CDom_reduced4SigExtra_shift =
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$unsigned($signed(17'sh10000 >>> ~(io_fromPreMul_CDom_CAlignDist[5:2])));
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wire [7:0] _CDom_reduced4SigExtra_T_15 =
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{4'h0, CDom_reduced4SigExtra_shift[8:5]} | {CDom_reduced4SigExtra_shift[4:1], 4'h0};
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wire [7:0] _CDom_reduced4SigExtra_T_25 =
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{2'h0, _CDom_reduced4SigExtra_T_15[7:2] & 6'h33}
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| {_CDom_reduced4SigExtra_T_15[5:0] & 6'h33, 2'h0};
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wire [108:0] notCDom_absSigSum =
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_sigSum_T_3[2]
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? ~{_sigSum_T_3[1:0], io_mulAddResult[105:0], io_fromPreMul_bit0AlignedSigC}
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: {_sigSum_T_3[1:0], io_mulAddResult[105:0], io_fromPreMul_bit0AlignedSigC}
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+ {108'h0, io_fromPreMul_doSubMags};
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wire notCDom_reduced2AbsSigSum_reducedVec_1 = |(notCDom_absSigSum[3:2]);
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wire notCDom_reduced2AbsSigSum_reducedVec_2 = |(notCDom_absSigSum[5:4]);
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wire notCDom_reduced2AbsSigSum_reducedVec_3 = |(notCDom_absSigSum[7:6]);
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wire notCDom_reduced2AbsSigSum_reducedVec_4 = |(notCDom_absSigSum[9:8]);
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wire notCDom_reduced2AbsSigSum_reducedVec_5 = |(notCDom_absSigSum[11:10]);
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wire notCDom_reduced2AbsSigSum_reducedVec_6 = |(notCDom_absSigSum[13:12]);
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wire notCDom_reduced2AbsSigSum_reducedVec_7 = |(notCDom_absSigSum[15:14]);
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wire notCDom_reduced2AbsSigSum_reducedVec_8 = |(notCDom_absSigSum[17:16]);
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wire notCDom_reduced2AbsSigSum_reducedVec_9 = |(notCDom_absSigSum[19:18]);
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wire notCDom_reduced2AbsSigSum_reducedVec_10 = |(notCDom_absSigSum[21:20]);
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wire notCDom_reduced2AbsSigSum_reducedVec_11 = |(notCDom_absSigSum[23:22]);
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wire notCDom_reduced2AbsSigSum_reducedVec_12 = |(notCDom_absSigSum[25:24]);
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wire notCDom_reduced2AbsSigSum_reducedVec_13 = |(notCDom_absSigSum[27:26]);
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wire notCDom_reduced2AbsSigSum_reducedVec_14 = |(notCDom_absSigSum[29:28]);
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wire notCDom_reduced2AbsSigSum_reducedVec_15 = |(notCDom_absSigSum[31:30]);
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wire notCDom_reduced2AbsSigSum_reducedVec_16 = |(notCDom_absSigSum[33:32]);
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wire notCDom_reduced2AbsSigSum_reducedVec_17 = |(notCDom_absSigSum[35:34]);
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wire notCDom_reduced2AbsSigSum_reducedVec_18 = |(notCDom_absSigSum[37:36]);
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wire notCDom_reduced2AbsSigSum_reducedVec_19 = |(notCDom_absSigSum[39:38]);
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wire notCDom_reduced2AbsSigSum_reducedVec_20 = |(notCDom_absSigSum[41:40]);
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wire notCDom_reduced2AbsSigSum_reducedVec_21 = |(notCDom_absSigSum[43:42]);
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wire notCDom_reduced2AbsSigSum_reducedVec_22 = |(notCDom_absSigSum[45:44]);
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wire notCDom_reduced2AbsSigSum_reducedVec_23 = |(notCDom_absSigSum[47:46]);
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wire notCDom_reduced2AbsSigSum_reducedVec_24 = |(notCDom_absSigSum[49:48]);
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wire notCDom_reduced2AbsSigSum_reducedVec_25 = |(notCDom_absSigSum[51:50]);
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wire [5:0] notCDom_normDistReduced2 =
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notCDom_absSigSum[108]
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? 6'h0
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: (|(notCDom_absSigSum[107:106]))
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? 6'h1
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: (|(notCDom_absSigSum[105:104]))
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? 6'h2
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: (|(notCDom_absSigSum[103:102]))
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? 6'h3
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: (|(notCDom_absSigSum[101:100]))
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? 6'h4
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: (|(notCDom_absSigSum[99:98]))
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? 6'h5
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: (|(notCDom_absSigSum[97:96]))
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? 6'h6
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: (|(notCDom_absSigSum[95:94]))
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? 6'h7
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: (|(notCDom_absSigSum[93:92]))
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? 6'h8
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: (|(notCDom_absSigSum[91:90]))
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? 6'h9
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: (|(notCDom_absSigSum[89:88]))
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? 6'hA
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: (|(notCDom_absSigSum[87:86]))
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? 6'hB
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: (|(notCDom_absSigSum[85:84]))
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? 6'hC
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: (|(notCDom_absSigSum[83:82]))
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? 6'hD
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: (|(notCDom_absSigSum[81:80]))
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? 6'hE
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: (|(notCDom_absSigSum[79:78]))
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? 6'hF
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: (|(notCDom_absSigSum[77:76]))
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? 6'h10
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: (|(notCDom_absSigSum[75:74]))
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? 6'h11
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: (|(notCDom_absSigSum[73:72]))
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? 6'h12
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: (|(notCDom_absSigSum[71:70]))
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? 6'h13
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: (|(notCDom_absSigSum[69:68]))
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? 6'h14
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: (|(notCDom_absSigSum[67:66]))
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? 6'h15
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: (|(notCDom_absSigSum[65:64]))
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? 6'h16
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: (|(notCDom_absSigSum[63:62]))
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? 6'h17
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: (|(notCDom_absSigSum[61:60]))
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? 6'h18
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: (|(notCDom_absSigSum[59:58]))
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? 6'h19
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: (|(notCDom_absSigSum[57:56]))
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? 6'h1A
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: (|(notCDom_absSigSum[55:54]))
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? 6'h1B
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: (|(notCDom_absSigSum[53:52]))
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? 6'h1C
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: notCDom_reduced2AbsSigSum_reducedVec_25
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? 6'h1D
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: notCDom_reduced2AbsSigSum_reducedVec_24
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? 6'h1E
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: notCDom_reduced2AbsSigSum_reducedVec_23
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? 6'h1F
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: notCDom_reduced2AbsSigSum_reducedVec_22
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? 6'h20
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: notCDom_reduced2AbsSigSum_reducedVec_21
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? 6'h21
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: notCDom_reduced2AbsSigSum_reducedVec_20
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? 6'h22
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: notCDom_reduced2AbsSigSum_reducedVec_19
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? 6'h23
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: notCDom_reduced2AbsSigSum_reducedVec_18
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? 6'h24
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: notCDom_reduced2AbsSigSum_reducedVec_17
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? 6'h25
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: notCDom_reduced2AbsSigSum_reducedVec_16
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? 6'h26
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: notCDom_reduced2AbsSigSum_reducedVec_15
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? 6'h27
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: notCDom_reduced2AbsSigSum_reducedVec_14
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? 6'h28
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: notCDom_reduced2AbsSigSum_reducedVec_13
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? 6'h29
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: notCDom_reduced2AbsSigSum_reducedVec_12
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? 6'h2A
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: notCDom_reduced2AbsSigSum_reducedVec_11
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? 6'h2B
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: notCDom_reduced2AbsSigSum_reducedVec_10
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? 6'h2C
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: notCDom_reduced2AbsSigSum_reducedVec_9
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? 6'h2D
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: notCDom_reduced2AbsSigSum_reducedVec_8
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? 6'h2E
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: notCDom_reduced2AbsSigSum_reducedVec_7
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? 6'h2F
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: notCDom_reduced2AbsSigSum_reducedVec_6
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? 6'h30
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: notCDom_reduced2AbsSigSum_reducedVec_5
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? 6'h31
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: notCDom_reduced2AbsSigSum_reducedVec_4
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? 6'h32
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: notCDom_reduced2AbsSigSum_reducedVec_3
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? 6'h33
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: notCDom_reduced2AbsSigSum_reducedVec_2
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? 6'h34
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: notCDom_reduced2AbsSigSum_reducedVec_1
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? 6'h35
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: 6'h36;
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wire [235:0] _notCDom_mainSig_T =
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{127'h0, notCDom_absSigSum} << {229'h0, notCDom_normDistReduced2, 1'h0};
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wire [32:0] notCDom_reduced4SigExtra_shift =
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$unsigned($signed(33'sh100000000 >>> ~(notCDom_normDistReduced2[5:1])));
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wire [7:0] _notCDom_reduced4SigExtra_T_15 =
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{4'h0, notCDom_reduced4SigExtra_shift[8:5]}
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| {notCDom_reduced4SigExtra_shift[4:1], 4'h0};
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wire [7:0] _notCDom_reduced4SigExtra_T_25 =
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{2'h0, _notCDom_reduced4SigExtra_T_15[7:2] & 6'h33}
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| {_notCDom_reduced4SigExtra_T_15[5:0] & 6'h33, 2'h0};
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wire notCDom_completeCancellation = _notCDom_mainSig_T[109:108] == 2'h0;
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wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB;
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wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC;
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wire notNaN_addZeros =
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(io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC;
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assign io_invalidExc =
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io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB
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| io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB
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& notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags;
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assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC;
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assign io_rawOut_isInf = notNaN_isInfOut;
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assign io_rawOut_isZero =
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notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation;
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assign io_rawOut_sign =
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notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC
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| notNaN_addZeros & io_roundingMode != 3'h2 & io_fromPreMul_signProd & opSignC
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| notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC)
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| ~notNaN_isInfOut & ~notNaN_addZeros
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& (io_fromPreMul_CIsDominant
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? opSignC
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: notCDom_completeCancellation
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? roundingMode_min
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: io_fromPreMul_signProd ^ _sigSum_T_3[2]);
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assign io_rawOut_sExp =
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io_fromPreMul_CIsDominant
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? io_fromPreMul_sExpSum - {12'h0, io_fromPreMul_doSubMags}
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: io_fromPreMul_sExpSum - {6'h0, notCDom_normDistReduced2, 1'h0};
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assign io_rawOut_sig =
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io_fromPreMul_CIsDominant
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? {_CDom_mainSig_T[107:53],
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(|{_CDom_mainSig_T[52:50],
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{|(CDom_absSigSum[49:46]),
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|(CDom_absSigSum[45:42]),
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|(CDom_absSigSum[41:38]),
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|(CDom_absSigSum[37:34]),
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|(CDom_absSigSum[33:30]),
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|(CDom_absSigSum[29:26]),
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|(CDom_absSigSum[25:22]),
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|(CDom_absSigSum[21:18]),
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|(CDom_absSigSum[17:14]),
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|(CDom_absSigSum[13:10]),
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|(CDom_absSigSum[9:6]),
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|(CDom_absSigSum[5:2]),
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|(CDom_absSigSum[1:0])}
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& {{1'h0, _CDom_reduced4SigExtra_T_25[7:1] & 7'h55}
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| {_CDom_reduced4SigExtra_T_25[6:0] & 7'h55, 1'h0},
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CDom_reduced4SigExtra_shift[9],
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CDom_reduced4SigExtra_shift[10],
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CDom_reduced4SigExtra_shift[11],
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CDom_reduced4SigExtra_shift[12],
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CDom_reduced4SigExtra_shift[13]}})
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| (io_fromPreMul_doSubMags
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? io_mulAddResult[52:0] != 53'h1FFFFFFFFFFFFF
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: (|(io_mulAddResult[53:0])))}
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: {_notCDom_mainSig_T[109:55],
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|{_notCDom_mainSig_T[54:52],
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{|{notCDom_reduced2AbsSigSum_reducedVec_25,
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notCDom_reduced2AbsSigSum_reducedVec_24},
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|{notCDom_reduced2AbsSigSum_reducedVec_23,
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notCDom_reduced2AbsSigSum_reducedVec_22},
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|{notCDom_reduced2AbsSigSum_reducedVec_21,
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notCDom_reduced2AbsSigSum_reducedVec_20},
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|{notCDom_reduced2AbsSigSum_reducedVec_19,
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notCDom_reduced2AbsSigSum_reducedVec_18},
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|{notCDom_reduced2AbsSigSum_reducedVec_17,
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notCDom_reduced2AbsSigSum_reducedVec_16},
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|{notCDom_reduced2AbsSigSum_reducedVec_15,
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notCDom_reduced2AbsSigSum_reducedVec_14},
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|{notCDom_reduced2AbsSigSum_reducedVec_13,
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notCDom_reduced2AbsSigSum_reducedVec_12},
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|{notCDom_reduced2AbsSigSum_reducedVec_11,
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notCDom_reduced2AbsSigSum_reducedVec_10},
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|{notCDom_reduced2AbsSigSum_reducedVec_9,
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notCDom_reduced2AbsSigSum_reducedVec_8},
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|{notCDom_reduced2AbsSigSum_reducedVec_7,
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notCDom_reduced2AbsSigSum_reducedVec_6},
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|{notCDom_reduced2AbsSigSum_reducedVec_5,
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notCDom_reduced2AbsSigSum_reducedVec_4},
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|{notCDom_reduced2AbsSigSum_reducedVec_3,
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notCDom_reduced2AbsSigSum_reducedVec_2},
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|{notCDom_reduced2AbsSigSum_reducedVec_1, |(notCDom_absSigSum[1:0])}}
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& {{1'h0, _notCDom_reduced4SigExtra_T_25[7:1] & 7'h55}
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| {_notCDom_reduced4SigExtra_T_25[6:0] & 7'h55, 1'h0},
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notCDom_reduced4SigExtra_shift[9],
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notCDom_reduced4SigExtra_shift[10],
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notCDom_reduced4SigExtra_shift[11],
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notCDom_reduced4SigExtra_shift[12],
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notCDom_reduced4SigExtra_shift[13]}}};
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endmodule
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