onur
72 lines
2.9 KiB
Systemverilog
72 lines
2.9 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module PLICClockSinkDomain(
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input auto_plic_int_in_0,
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auto_plic_int_in_1,
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auto_plic_int_in_2,
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auto_plic_int_in_3,
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auto_plic_int_in_4,
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auto_plic_int_in_5,
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auto_plic_int_in_6,
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auto_plic_int_in_7,
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auto_plic_int_in_8,
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auto_plic_int_in_9,
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auto_plic_int_in_10,
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output auto_plic_in_a_ready,
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input auto_plic_in_a_valid,
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input [2:0] auto_plic_in_a_bits_opcode,
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input [1:0] auto_plic_in_a_bits_size,
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input [5:0] auto_plic_in_a_bits_source,
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input [27:0] auto_plic_in_a_bits_address,
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input [7:0] auto_plic_in_a_bits_mask,
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input [63:0] auto_plic_in_a_bits_data,
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input auto_plic_in_d_ready,
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output auto_plic_in_d_valid,
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output [2:0] auto_plic_in_d_bits_opcode,
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output [1:0] auto_plic_in_d_bits_size,
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output [5:0] auto_plic_in_d_bits_source,
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output [63:0] auto_plic_in_d_bits_data,
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output auto_int_in_clock_xing_out_sync_0,
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input auto_clock_in_clock,
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auto_clock_in_reset
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);
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wire _plic_auto_int_out_0;
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TLPLIC plic (
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.clock (auto_clock_in_clock),
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.reset (auto_clock_in_reset),
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.auto_int_in_0 (auto_plic_int_in_0),
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.auto_int_in_1 (auto_plic_int_in_1),
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.auto_int_in_2 (auto_plic_int_in_2),
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.auto_int_in_3 (auto_plic_int_in_3),
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.auto_int_in_4 (auto_plic_int_in_4),
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.auto_int_in_5 (auto_plic_int_in_5),
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.auto_int_in_6 (auto_plic_int_in_6),
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.auto_int_in_7 (auto_plic_int_in_7),
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.auto_int_in_8 (auto_plic_int_in_8),
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.auto_int_in_9 (auto_plic_int_in_9),
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.auto_int_in_10 (auto_plic_int_in_10),
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.auto_int_out_0 (_plic_auto_int_out_0),
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.auto_in_a_ready (auto_plic_in_a_ready),
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.auto_in_a_valid (auto_plic_in_a_valid),
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.auto_in_a_bits_opcode (auto_plic_in_a_bits_opcode),
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.auto_in_a_bits_size (auto_plic_in_a_bits_size),
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.auto_in_a_bits_source (auto_plic_in_a_bits_source),
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.auto_in_a_bits_address (auto_plic_in_a_bits_address),
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.auto_in_a_bits_mask (auto_plic_in_a_bits_mask),
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.auto_in_a_bits_data (auto_plic_in_a_bits_data),
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.auto_in_d_ready (auto_plic_in_d_ready),
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.auto_in_d_valid (auto_plic_in_d_valid),
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.auto_in_d_bits_opcode (auto_plic_in_d_bits_opcode),
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.auto_in_d_bits_size (auto_plic_in_d_bits_size),
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.auto_in_d_bits_source (auto_plic_in_d_bits_source),
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.auto_in_d_bits_data (auto_plic_in_d_bits_data)
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);
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IntSyncCrossingSource_n1x1 intsource (
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.clock (auto_clock_in_clock),
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.reset (auto_clock_in_reset),
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.auto_in_0 (_plic_auto_int_out_0),
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.auto_out_sync_0 (auto_int_in_clock_xing_out_sync_0)
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);
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endmodule
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