onur
79 lines
3.0 KiB
Systemverilog
79 lines
3.0 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module PLICFanIn(
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input [2:0] io_prio_0,
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io_prio_1,
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io_prio_2,
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io_prio_3,
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io_prio_4,
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io_prio_5,
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io_prio_6,
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io_prio_7,
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io_prio_8,
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io_prio_9,
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io_prio_10,
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input [10:0] io_ip,
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output [3:0] io_dev,
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output [2:0] io_max
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);
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wire [3:0] effectivePriority_1 = {io_ip[0], io_prio_0};
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wire [3:0] effectivePriority_2 = {io_ip[1], io_prio_1};
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wire [3:0] effectivePriority_3 = {io_ip[2], io_prio_2};
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wire [3:0] effectivePriority_4 = {io_ip[3], io_prio_3};
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wire [3:0] effectivePriority_5 = {io_ip[4], io_prio_4};
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wire [3:0] effectivePriority_6 = {io_ip[5], io_prio_5};
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wire [3:0] effectivePriority_7 = {io_ip[6], io_prio_6};
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wire [3:0] effectivePriority_8 = {io_ip[7], io_prio_7};
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wire [3:0] effectivePriority_9 = {io_ip[8], io_prio_8};
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wire [3:0] effectivePriority_10 = {io_ip[9], io_prio_9};
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wire [3:0] effectivePriority_11 = {io_ip[10], io_prio_10};
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wire [3:0] left_left_left_1 = effectivePriority_1 < 4'h9 ? 4'h8 : effectivePriority_1;
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wire [3:0] left_left_right_1 =
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effectivePriority_2 >= effectivePriority_3
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? effectivePriority_2
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: effectivePriority_3;
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wire _left_left_T = left_left_left_1 >= left_left_right_1;
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wire [3:0] left_left_1 = _left_left_T ? left_left_left_1 : left_left_right_1;
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wire [3:0] left_right_left_1 =
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effectivePriority_4 >= effectivePriority_5
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? effectivePriority_4
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: effectivePriority_5;
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wire [3:0] left_right_right_1 =
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effectivePriority_6 >= effectivePriority_7
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? effectivePriority_6
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: effectivePriority_7;
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wire _left_right_T = left_right_left_1 >= left_right_right_1;
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wire [3:0] left_right_1 = _left_right_T ? left_right_left_1 : left_right_right_1;
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wire _left_T = left_left_1 >= left_right_1;
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wire [3:0] left_1 = _left_T ? left_left_1 : left_right_1;
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wire [3:0] right_left_1 =
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effectivePriority_8 >= effectivePriority_9
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? effectivePriority_8
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: effectivePriority_9;
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wire [3:0] right_right_1 =
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effectivePriority_10 >= effectivePriority_11
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? effectivePriority_10
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: effectivePriority_11;
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wire _right_T = right_left_1 >= right_right_1;
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wire [3:0] right_1 = _right_T ? right_left_1 : right_right_1;
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wire _GEN = left_1 >= right_1;
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assign io_dev =
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_GEN
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? {1'h0,
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_left_T
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? {1'h0,
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_left_left_T
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? {1'h0, effectivePriority_1 > 4'h8}
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: {1'h1, effectivePriority_2 < effectivePriority_3}}
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: {1'h1,
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_left_right_T
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? {1'h0, effectivePriority_4 < effectivePriority_5}
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: {1'h1, effectivePriority_6 < effectivePriority_7}}}
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: {2'h2,
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_right_T
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? {1'h0, effectivePriority_8 < effectivePriority_9}
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: {1'h1, effectivePriority_10 < effectivePriority_11}};
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assign io_max = _GEN ? left_1[2:0] : right_1[2:0];
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endmodule
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