onur
52 lines
2.3 KiB
Systemverilog
52 lines
2.3 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module RecFNToIN(
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input [64:0] io_in,
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input [2:0] io_roundingMode,
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input io_signedOut,
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output [63:0] io_out,
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output [2:0] io_intExceptionFlags
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);
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wire rawIn_isSpecial = &(io_in[63:62]);
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wire rawIn_isNaN = rawIn_isSpecial & io_in[61];
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wire magJustBelowOne = ~(io_in[63]) & (&(io_in[62:52]));
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wire roundingMode_odd = io_roundingMode == 3'h6;
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wire [115:0] shiftedSig =
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{63'h0, io_in[63], io_in[51:0]} << (io_in[63] ? io_in[57:52] : 6'h0);
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wire [1:0] _roundIncr_near_even_T_6 = {shiftedSig[51], |(shiftedSig[50:0])};
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wire common_inexact =
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io_in[63] ? (|_roundIncr_near_even_T_6) : (|(io_in[63:61]));
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wire roundIncr =
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io_roundingMode == 3'h0
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& (io_in[63] & ((&(shiftedSig[52:51])) | (&_roundIncr_near_even_T_6))
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| magJustBelowOne & (|_roundIncr_near_even_T_6)) | io_roundingMode == 3'h4
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& (io_in[63] & shiftedSig[51] | magJustBelowOne)
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| (io_roundingMode == 3'h2 | roundingMode_odd) & io_in[64] & common_inexact
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| io_roundingMode == 3'h3 & ~(io_in[64]) & common_inexact;
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wire [63:0] complUnroundedInt = {64{io_in[64]}} ^ shiftedSig[115:52];
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wire [63:0] _roundedInt_T_3 =
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roundIncr ^ io_in[64] ? complUnroundedInt + 64'h1 : complUnroundedInt;
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wire magGeOne_atOverflowEdge = io_in[62:52] == 11'h3F;
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wire roundCarryBut2 = (&(shiftedSig[113:52])) & roundIncr;
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wire common_overflow =
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io_in[63]
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? (|(io_in[62:58]))
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| (io_signedOut
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? (io_in[64]
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? magGeOne_atOverflowEdge & ((|(shiftedSig[114:52])) | roundIncr)
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: magGeOne_atOverflowEdge | io_in[62:52] == 11'h3E & roundCarryBut2)
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: io_in[64] | magGeOne_atOverflowEdge & shiftedSig[114] & roundCarryBut2)
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: ~io_signedOut & io_in[64] & roundIncr;
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wire invalidExc = rawIn_isNaN | rawIn_isSpecial & ~(io_in[61]);
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wire excSign = ~rawIn_isNaN & io_in[64];
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assign io_out =
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invalidExc | common_overflow
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? {io_signedOut == excSign, {63{~excSign}}}
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: {_roundedInt_T_3[63:1], _roundedInt_T_3[0] | roundingMode_odd & common_inexact};
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assign io_intExceptionFlags =
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{invalidExc,
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~invalidExc & common_overflow,
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~invalidExc & ~common_overflow & common_inexact};
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endmodule
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