onur
102 lines
5.0 KiB
Systemverilog
102 lines
5.0 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module RoundAnyRawFNToRecFN(
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input io_invalidExc,
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io_infiniteExc,
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io_in_isNaN,
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io_in_isInf,
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io_in_isZero,
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io_in_sign,
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input [9:0] io_in_sExp,
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input [26:0] io_in_sig,
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input [2:0] io_roundingMode,
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output [32:0] io_out,
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output [4:0] io_exceptionFlags
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);
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wire roundingMode_near_even = io_roundingMode == 3'h0;
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wire roundingMode_odd = io_roundingMode == 3'h6;
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wire roundMagUp =
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io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign;
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wire [8:0] _roundMask_T_1 = ~(io_in_sExp[8:0]);
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wire [64:0] _GEN = {59'h0, _roundMask_T_1[5:0]};
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wire [64:0] roundMask_shift = $unsigned($signed(65'sh10000000000000000 >>> _GEN));
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wire [15:0] _roundMask_T_12 =
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{8'h0, roundMask_shift[57:50]} | {roundMask_shift[49:42], 8'h0};
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wire [15:0] _roundMask_T_22 =
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{4'h0, _roundMask_T_12[15:4] & 12'hF0F} | {_roundMask_T_12[11:0] & 12'hF0F, 4'h0};
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wire [15:0] _roundMask_T_32 =
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{2'h0, _roundMask_T_22[15:2] & 14'h3333} | {_roundMask_T_22[13:0] & 14'h3333, 2'h0};
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wire [64:0] roundMask_shift_1 = $unsigned($signed(65'sh10000000000000000 >>> _GEN));
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wire [24:0] _roundMask_T_73 =
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_roundMask_T_1[8]
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? (_roundMask_T_1[7]
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? {~(_roundMask_T_1[6]
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? 22'h0
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: ~{{1'h0, _roundMask_T_32[15:1] & 15'h5555}
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| {_roundMask_T_32[14:0] & 15'h5555, 1'h0},
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roundMask_shift[58],
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roundMask_shift[59],
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roundMask_shift[60],
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roundMask_shift[61],
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roundMask_shift[62],
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roundMask_shift[63]}),
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3'h7}
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: {22'h0,
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_roundMask_T_1[6]
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? {roundMask_shift_1[0], roundMask_shift_1[1], roundMask_shift_1[2]}
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: 3'h0})
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: 25'h0;
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wire _common_underflow_T_4 = _roundMask_T_73[0] | io_in_sig[26];
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wire [25:0] _GEN_0 = {1'h1, ~(_roundMask_T_73[24:1]), ~_common_underflow_T_4};
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wire [25:0] _GEN_1 = {_roundMask_T_73[24:1], _common_underflow_T_4, 1'h1};
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wire [25:0] _roundPosBit_T = io_in_sig[26:1] & _GEN_0 & _GEN_1;
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wire roundPosBit = |_roundPosBit_T;
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wire [25:0] _anyRoundExtra_T = io_in_sig[25:0] & _GEN_1;
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wire anyRound = |{_roundPosBit_T, _anyRoundExtra_T};
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wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4;
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wire [25:0] roundedSig =
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_overflow_roundMagUp_T & roundPosBit | roundMagUp & anyRound
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? {1'h0, io_in_sig[26:2] | {_roundMask_T_73[24:1], _common_underflow_T_4}} + 26'h1
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& ~(roundingMode_near_even & roundPosBit & _anyRoundExtra_T == 26'h0
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? {_roundMask_T_73[24:1], _common_underflow_T_4, 1'h1}
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: 26'h0)
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: {1'h0, io_in_sig[26:2] & {~(_roundMask_T_73[24:1]), ~_common_underflow_T_4}}
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| (roundingMode_odd & anyRound ? _GEN_0 & _GEN_1 : 26'h0);
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wire [10:0] sRoundedExp = {io_in_sExp[9], io_in_sExp} + {9'h0, roundedSig[25:24]};
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wire common_totalUnderflow = $signed(sRoundedExp) < 11'sh6B;
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wire isNaNOut = io_invalidExc | io_in_isNaN;
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wire notNaN_isSpecialInfOut = io_infiniteExc | io_in_isInf;
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wire commonCase = ~isNaNOut & ~notNaN_isSpecialInfOut & ~io_in_isZero;
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wire overflow = commonCase & $signed(sRoundedExp[10:7]) > 4'sh2;
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wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp;
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wire pegMinNonzeroMagOut =
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commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd);
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wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp;
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wire notNaN_isInfOut = notNaN_isSpecialInfOut | overflow & overflow_roundMagUp;
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assign io_out =
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{~isNaNOut & io_in_sign,
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sRoundedExp[8:0] & ~(io_in_isZero | common_totalUnderflow ? 9'h1C0 : 9'h0)
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& ~(pegMinNonzeroMagOut ? 9'h194 : 9'h0) & {1'h1, ~pegMaxFiniteMagOut, 7'h7F}
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& {2'h3, ~notNaN_isInfOut, 6'h3F} | (pegMinNonzeroMagOut ? 9'h6B : 9'h0)
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| (pegMaxFiniteMagOut ? 9'h17F : 9'h0) | (notNaN_isInfOut ? 9'h180 : 9'h0)
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| (isNaNOut ? 9'h1C0 : 9'h0),
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(isNaNOut | io_in_isZero | common_totalUnderflow
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? {isNaNOut, 22'h0}
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: io_in_sig[26] ? roundedSig[23:1] : roundedSig[22:0])
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| {23{pegMaxFiniteMagOut}}};
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assign io_exceptionFlags =
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{io_invalidExc,
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io_infiniteExc,
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overflow,
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commonCase
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& (common_totalUnderflow | anyRound & io_in_sExp[9:8] != 2'h1
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& (io_in_sig[26] ? _roundMask_T_73[1] : _common_underflow_T_4)
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& ~(~(io_in_sig[26] ? _roundMask_T_73[2] : _roundMask_T_73[1])
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& (io_in_sig[26] ? roundedSig[25] : roundedSig[24]) & roundPosBit
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& (_overflow_roundMagUp_T & (io_in_sig[26] ? io_in_sig[2] : io_in_sig[1])
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| roundMagUp & (|{io_in_sig[26] & io_in_sig[2], io_in_sig[1:0]})))),
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overflow | commonCase
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& (|{common_totalUnderflow, _roundPosBit_T, _anyRoundExtra_T})};
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endmodule
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