onur
15 lines
257 B
Systemverilog
15 lines
257 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module SynchronizerShiftReg_w1_d3(
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input clock,
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io_d,
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output io_q
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);
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NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain (
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.clock (clock),
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.io_d (io_d),
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.io_q (io_q)
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);
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endmodule
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